diff --git a/slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServer_developer b/slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServer_developer
index 42fd78da8..b6256c360 100755
Binary files a/slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServer_developer and b/slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServer_developer differ
diff --git a/slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c b/slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c
index e01dd8b4b..791d2bcd5 100644
--- a/slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c
+++ b/slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c
@@ -860,6 +860,7 @@ int	setPeriodBurst(int64_t val) {
 }
 
 int64_t	getPeriodBurst() {
+	FILE_LOG(logDEBUG, ("Getting period [Burst mode]\n"));
 	return get64BitReg(ASIC_INT_PERIOD_LSB_REG, ASIC_INT_PERIOD_MSB_REG)/ (1E-9 * clkFrequency[SYSTEM_C0]);
 }
 
@@ -878,6 +879,7 @@ int	setPeriodCont(int64_t val) {
 }
 
 int64_t	getPeriodCont() {
+	FILE_LOG(logDEBUG, ("Getting period [Continuous mode]\n"));
 	return get64BitReg(SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG)/ (1E-9 * FIXED_PLL_FREQUENCY);
 }
 
@@ -1849,10 +1851,13 @@ enum burstMode getBurstMode() {
 	switch (runmode) {
 		case ASIC_CONFIG_RUN_MODE_CONT_VAL:
 			burstMode = BURST_OFF;
+			break;
 		case ASIC_CONFIG_RUN_MODE_INT_BURST_VAL:
 			burstMode = BURST_INTERNAL;
+			break;
 		case ASIC_CONFIG_RUN_MODE_EXT_BURST_VAL:
 			burstMode = BURST_EXTERNAL;
+			break;
 		default:
 			FILE_LOG(logERROR, ("Unknown run mode read from FPGA %d\n", runmode));
 			return -1;
diff --git a/slsDetectorServers/gotthard2DetectorServer/slsDetectorServer_defs.h b/slsDetectorServers/gotthard2DetectorServer/slsDetectorServer_defs.h
index 06460e6cf..c39ad53de 100644
--- a/slsDetectorServers/gotthard2DetectorServer/slsDetectorServer_defs.h
+++ b/slsDetectorServers/gotthard2DetectorServer/slsDetectorServer_defs.h
@@ -34,7 +34,7 @@
 #define DEFAULT_NUM_FRAMES			(1)
 #define DEFAULT_NUM_CYCLES			(1)
 #define DEFAULT_EXPTIME				(0)	        // 0 ms (220ns in firmware)
-#define DEFAULT_PERIOD				(0)			// 1 ms
+#define DEFAULT_PERIOD				(0)			// 0 ms
 #define DEFAULT_DELAY_AFTER_TRIGGER (0)
 #define DEFAULT_HIGH_VOLTAGE		(0)
 #define DEFAULT_TIMING_MODE			(AUTO_TIMING)