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ctb server: pll reset to keep the phase after setting clock

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This commit is contained in:
maliakal_d 2019-03-28 15:22:13 +01:00
parent fc0306564c
commit 37b80bcc0d
1 changed files with 3 additions and 0 deletions
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3
slsDetectorServers/slsDetectorServer/ALTERA_PLL.h
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@ -225,6 +225,9 @@ int ALTERA_PLL_SetOuputFrequency (int clkIndex, int pllVCOFreqMhz, int value) {
// write frequency (post-scale output counter C)
ALTERA_PLL_SetPllReconfigReg(ALTERA_PLL_C_COUNTER_REG, val);
// reset required to keep the phase
ALTERA_PLL_ResetPLL ();
/*double temp = ((double)pllVCOFreqMhz / (double)(low_count + high_count));
if ((temp - (int)temp) > 0.0001) {
temp += 0.5;