From 37b80bcc0dc0d28392dbb61d1cf130bf14a1c593 Mon Sep 17 00:00:00 2001 From: Dhanya Thattil Date: Thu, 28 Mar 2019 15:22:13 +0100 Subject: [PATCH] ctb server: pll reset to keep the phase after setting clock --- slsDetectorServers/slsDetectorServer/ALTERA_PLL.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/slsDetectorServers/slsDetectorServer/ALTERA_PLL.h b/slsDetectorServers/slsDetectorServer/ALTERA_PLL.h index 9155cb876..008c39c79 100755 --- a/slsDetectorServers/slsDetectorServer/ALTERA_PLL.h +++ b/slsDetectorServers/slsDetectorServer/ALTERA_PLL.h @@ -225,6 +225,9 @@ int ALTERA_PLL_SetOuputFrequency (int clkIndex, int pllVCOFreqMhz, int value) { // write frequency (post-scale output counter C) ALTERA_PLL_SetPllReconfigReg(ALTERA_PLL_C_COUNTER_REG, val); + // reset required to keep the phase + ALTERA_PLL_ResetPLL (); + /*double temp = ((double)pllVCOFreqMhz / (double)(low_count + high_count)); if ((temp - (int)temp) > 0.0001) { temp += 0.5;