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Merge branch 'refactor' into shm

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maliakal_d 2019-03-13 14:22:26 +01:00
commit 2dcef909ca
12 changed files with 77 additions and 64 deletions
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12
slsDetectorServers/ctbDetectorServer/gitInfo.txt
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@ -1,9 +1,9 @@
Path: slsDetectorPackage/slsDetectorServers/ctbDetectorServer Path: slsDetectorPackage/slsDetectorServers/ctbDetectorServer
URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git URL: origin https://www.github.com/slsdetectorgroup/slsDetectorPackage
Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git Repository Root: origin https://www.github.com/slsdetectorgroup/slsDetectorPackage
Repsitory UUID: 1103f56256f3f8b5037343f9e9a2ef90139dc6d0 Repsitory UUID: 6765fd0dc89176b4eceaf5e2304ef808a316ba9b
Revision: 37 Revision: 38
Branch: refactor Branch: refactor
Last Changed Author: Dhanya_Thattil Last Changed Author: Dhanya_Thattil
Last Changed Rev: 4389 Last Changed Rev: 4394
Last Changed Date: 2019-03-08 14:05:26.000000002 +0100 ./RegisterDefs.h Last Changed Date: 2019-03-13 08:04:56.000000002 +0100 ./RegisterDefs.h

8
slsDetectorServers/ctbDetectorServer/gitInfoCtb.h
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@ -1,6 +1,6 @@
#define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git" #define GITURL "https://www.github.com/slsdetectorgroup/slsDetectorPackage"
#define GITREPUUID "1103f56256f3f8b5037343f9e9a2ef90139dc6d0" #define GITREPUUID "6765fd0dc89176b4eceaf5e2304ef808a316ba9b"
#define GITAUTH "Dhanya_Thattil" #define GITAUTH "Dhanya_Thattil"
#define GITREV 0x4389 #define GITREV 0x4394
#define GITDATE 0x20190308 #define GITDATE 0x20190313
#define GITBRANCH "refactor" #define GITBRANCH "refactor"

25
slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c
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@ -786,7 +786,7 @@ void setSpeed(enum speedVariable ind, int val) {
case ADC_PHASE: case ADC_PHASE:
case PHASE_SHIFT: case PHASE_SHIFT:
FILE_LOG(logINFOBLUE, ("Configuring ADC Phase\n")); FILE_LOG(logINFOBLUE, ("Configuring ADC Phase\n"));
configurePhase(RUN_CLK, val); configurePhase(ADC_CLK, val);
break; break;
case DBIT_PHASE: case DBIT_PHASE:
FILE_LOG(logINFOBLUE, ("Configuring Dbit Phase\n")); FILE_LOG(logINFOBLUE, ("Configuring Dbit Phase\n"));
@ -1639,6 +1639,12 @@ void configurePhase(enum CLKINDEX ind, int val) {
FILE_LOG(logERROR, ("\tPhase provided for C%d(%s) outside limits\n", ind, clock_names[ind])); FILE_LOG(logERROR, ("\tPhase provided for C%d(%s) outside limits\n", ind, clock_names[ind]));
return; return;
} }
int relativePhase = clkPhase[ind] - val;
// same phase
if (!relativePhase) {
return;
}
FILE_LOG(logINFO, ("Configuring Phase of C%d(%s) to %d\n", ind, clock_names[ind], val)); FILE_LOG(logINFO, ("Configuring Phase of C%d(%s) to %d\n", ind, clock_names[ind], val));
@ -1648,16 +1654,17 @@ void configurePhase(enum CLKINDEX ind, int val) {
// set mode register to polling mode // set mode register to polling mode
ALTERA_PLL_SetModePolling(); ALTERA_PLL_SetModePolling();
int phase = 0, inv = 0;
if (val > 0) { int phase = 0;
inv = 0; int maxShifts = ((ind == ADC_CLK) ? MAX_PHASE_SHIFTS_ADC_CLK : MAX_PHASE_SHIFTS_DBIT_CLK);
phase = val;
// delay clk
if (relativePhase > 0) {
phase = (maxShifts - relativePhase);
} else { } else {
inv = 1; phase = (-1) * relativePhase;
val = -1 * val;
phase = (~val);
} }
FILE_LOG(logINFO, ("\tphase out %d (0x%08x), inv:%d\n", phase, phase, inv)); FILE_LOG(logINFO, ("\tphase out %d (0x%08x)\n", phase, phase));
ALTERA_PLL_SetPhaseShift(phase, (int)ind, 0); ALTERA_PLL_SetPhaseShift(phase, (int)ind, 0);

3
slsDetectorServers/ctbDetectorServer/slsDetectorServer_defs.h
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@ -80,7 +80,8 @@ enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7, D8, D9,
/* Defines in the Firmware */ /* Defines in the Firmware */
#define MAX_PATTERN_LENGTH (0xFFFF) #define MAX_PATTERN_LENGTH (0xFFFF)
#define DIGITAL_IO_DELAY_MAXIMUM_PS ((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * OUTPUT_DELAY_0_OTPT_STTNG_STEPS) #define DIGITAL_IO_DELAY_MAXIMUM_PS ((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
#define MAX_PHASE_SHIFTS_ADC_CLK (320)
#define MAX_PHASE_SHIFTS_DBIT_CLK (32)
#define WAIT_TME_US_FR_ACQDONE_REG (100) // wait time in us after acquisition done to ensure there is no data in fifo #define WAIT_TME_US_FR_ACQDONE_REG (100) // wait time in us after acquisition done to ensure there is no data in fifo
#define WAIT_TIME_US_PLL (10 * 1000) #define WAIT_TIME_US_PLL (10 * 1000)

12
slsDetectorServers/jungfrauDetectorServer/gitInfo.txt
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@ -1,9 +1,9 @@
Path: slsDetectorPackage/slsDetectorServers/jungfrauDetectorServer Path: slsDetectorPackage/slsDetectorServers/jungfrauDetectorServer
URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git URL: origin https://www.github.com/slsdetectorgroup/slsDetectorPackage
Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git Repository Root: origin https://www.github.com/slsdetectorgroup/slsDetectorPackage
Repsitory UUID: 93192c6e84a34ad3416f99b95e58356b609f61c6 Repsitory UUID: 6765fd0dc89176b4eceaf5e2304ef808a316ba9b
Revision: 24 Revision: 26
Branch: refactor Branch: refactor
Last Changed Author: Dhanya_Thattil Last Changed Author: Dhanya_Thattil
Last Changed Rev: 4370 Last Changed Rev: 4394
Last Changed Date: 2019-03-01 15:23:53.000000002 +0100 ./RegisterDefs.h Last Changed Date: 2019-03-13 08:04:56.000000002 +0100 ./RegisterDefs.h

8
slsDetectorServers/jungfrauDetectorServer/gitInfoJungfrau.h
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@ -1,6 +1,6 @@
#define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git" #define GITURL "https://www.github.com/slsdetectorgroup/slsDetectorPackage"
#define GITREPUUID "93192c6e84a34ad3416f99b95e58356b609f61c6" #define GITREPUUID "6765fd0dc89176b4eceaf5e2304ef808a316ba9b"
#define GITAUTH "Dhanya_Thattil" #define GITAUTH "Dhanya_Thattil"
#define GITREV 0x4370 #define GITREV 0x4394
#define GITDATE 0x20190301 #define GITDATE 0x20190313
#define GITBRANCH "refactor" #define GITBRANCH "refactor"

24
slsDetectorServers/jungfrauDetectorServer/slsDetectorFunctionList.c
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@ -1255,29 +1255,25 @@ void configurePll() {
#ifdef VIRTUAL #ifdef VIRTUAL
return; return;
#endif #endif
int32_t phase=0, inv=0; int32_t phase=0;
// ensuring PLL is never configured with same phase // ensuring PLL is never configured with same phase
if (clkPhase[1] == 0) { if (clkPhase[1] == 0) {
return; return;
} }
FILE_LOG(logINFO, ("\tConfiguring PLL with phase in %d\n", clkPhase[1])); FILE_LOG(logINFO, ("\tConfiguring PLL with phase in %d\n", clkPhase[1]));
// delay ADC clk
if (clkPhase[1]>0) { if (clkPhase[1]>0) {
inv=0; phase = MAX_PHASE_SHIFTS - clkPhase[1];
phase=clkPhase[1];
} else {
inv=1;
phase=-1*clkPhase[1];
} }
// advance adc clk
else {
phase = (-1) * clkPhase[1];
}
FILE_LOG(logDEBUG1, ("\tphase out %d (0x%08x)\n", phase, phase)); FILE_LOG(logDEBUG1, ("\tphase out %d (0x%08x)\n", phase, phase));
ALTERA_PLL_SetPhaseShift(phase, 1, 0); // phase, 1: adc clk, 0:neg
if (inv) {
ALTERA_PLL_SetPhaseShift(phase, 1, 0);
} else {
ALTERA_PLL_SetPhaseShift(phase, 0, 0);
ALTERA_PLL_SetPhaseShift(phase, 2, 0);
}
usleep(10000); usleep(10000);
} }

1
slsDetectorServers/jungfrauDetectorServer/slsDetectorServer_defs.h
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@ -88,6 +88,7 @@ enum NETWORKINDEX { TXN_FRAME };
#define ADC_PHASE_HALF_SPEED (0x2D) //45 #define ADC_PHASE_HALF_SPEED (0x2D) //45
#define ADC_PHASE_QUARTER_SPEED (0x2D) //45 #define ADC_PHASE_QUARTER_SPEED (0x2D) //45
#define ADC_PORT_INVERT_VAL (0x453b2a9c) #define ADC_PORT_INVERT_VAL (0x453b2a9c)
#define MAX_PHASE_SHIFTS (160)
/* MSB & LSB DEFINES */ /* MSB & LSB DEFINES */
#define MSB_OF_64_BIT_REG_OFST (32) #define MSB_OF_64_BIT_REG_OFST (32)

12
slsDetectorServers/moenchDetectorServer/gitInfo.txt
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@ -1,9 +1,9 @@
Path: slsDetectorPackage/slsDetectorServers/moenchDetectorServer Path: slsDetectorPackage/slsDetectorServers/moenchDetectorServer
URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git URL: origin https://www.github.com/slsdetectorgroup/slsDetectorPackage
Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git Repository Root: origin https://www.github.com/slsdetectorgroup/slsDetectorPackage
Repsitory UUID: ae5938799fb1bf7a5cb64bdb329f9c0d9ab44a03 Repsitory UUID: 6765fd0dc89176b4eceaf5e2304ef808a316ba9b
Revision: 15 Revision: 16
Branch: refactor Branch: refactor
Last Changed Author: Dhanya_Thattil Last Changed Author: Dhanya_Thattil
Last Changed Rev: 4393 Last Changed Rev: 4394
Last Changed Date: 2019-03-08 14:05:26.000000002 +0100 ./RegisterDefs.h Last Changed Date: 2019-03-13 08:04:56.000000002 +0100 ./RegisterDefs.h

8
slsDetectorServers/moenchDetectorServer/gitInfoMoench.h
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@ -1,6 +1,6 @@
#define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git" #define GITURL "https://www.github.com/slsdetectorgroup/slsDetectorPackage"
#define GITREPUUID "ae5938799fb1bf7a5cb64bdb329f9c0d9ab44a03" #define GITREPUUID "6765fd0dc89176b4eceaf5e2304ef808a316ba9b"
#define GITAUTH "Dhanya_Thattil" #define GITAUTH "Dhanya_Thattil"
#define GITREV 0x4393 #define GITREV 0x4394
#define GITDATE 0x20190308 #define GITDATE 0x20190313
#define GITBRANCH "refactor" #define GITBRANCH "refactor"

25
slsDetectorServers/moenchDetectorServer/slsDetectorFunctionList.c
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@ -762,7 +762,7 @@ void setSpeed(enum speedVariable ind, int val) {
case ADC_PHASE: case ADC_PHASE:
case PHASE_SHIFT: case PHASE_SHIFT:
FILE_LOG(logINFOBLUE, ("Configuring ADC Phase\n")); FILE_LOG(logINFOBLUE, ("Configuring ADC Phase\n"));
configurePhase(RUN_CLK, val); configurePhase(ADC_CLK, val);
break; break;
case DBIT_PHASE: case DBIT_PHASE:
FILE_LOG(logINFOBLUE, ("Configuring Dbit Phase\n")); FILE_LOG(logINFOBLUE, ("Configuring Dbit Phase\n"));
@ -1274,6 +1274,12 @@ void configurePhase(enum CLKINDEX ind, int val) {
FILE_LOG(logERROR, ("\tPhase provided for C%d(%s) outside limits\n", ind, clock_names[ind])); FILE_LOG(logERROR, ("\tPhase provided for C%d(%s) outside limits\n", ind, clock_names[ind]));
return; return;
} }
int relativePhase = clkPhase[ind] - val;
// same phase
if (!relativePhase) {
return;
}
FILE_LOG(logINFO, ("Configuring Phase of C%d(%s) to %d\n", ind, clock_names[ind], val)); FILE_LOG(logINFO, ("Configuring Phase of C%d(%s) to %d\n", ind, clock_names[ind], val));
@ -1283,16 +1289,17 @@ void configurePhase(enum CLKINDEX ind, int val) {
// set mode register to polling mode // set mode register to polling mode
ALTERA_PLL_SetModePolling(); ALTERA_PLL_SetModePolling();
int phase = 0, inv = 0;
if (val > 0) { int phase = 0;
inv = 0; int maxShifts = ((ind == ADC_CLK) ? MAX_PHASE_SHIFTS_ADC_CLK : MAX_PHASE_SHIFTS_DBIT_CLK);
phase = val;
// delay clk
if (relativePhase > 0) {
phase = (maxShifts - relativePhase);
} else { } else {
inv = 1; phase = (-1) * relativePhase;
val = -1 * val;
phase = (~val);
} }
FILE_LOG(logINFO, ("\tphase out %d (0x%08x), inv:%d\n", phase, phase, inv)); FILE_LOG(logINFO, ("\tphase out %d (0x%08x)\n", phase, phase));
ALTERA_PLL_SetPhaseShift(phase, (int)ind, 0); ALTERA_PLL_SetPhaseShift(phase, (int)ind, 0);

3
slsDetectorServers/moenchDetectorServer/slsDetectorServer_defs.h
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@ -61,7 +61,8 @@ enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7};
/* Defines in the Firmware */ /* Defines in the Firmware */
#define MAX_PATTERN_LENGTH (0xFFFF) #define MAX_PATTERN_LENGTH (0xFFFF)
#define DIGITAL_IO_DELAY_MAXIMUM_PS ((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * OUTPUT_DELAY_0_OTPT_STTNG_STEPS) #define DIGITAL_IO_DELAY_MAXIMUM_PS ((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
#define MAX_PHASE_SHIFTS_ADC_CLK (320)
#define MAX_PHASE_SHIFTS_DBIT_CLK (32)
#define WAIT_TME_US_FR_ACQDONE_REG (100) // wait time in us after acquisition done to ensure there is no data in fifo #define WAIT_TME_US_FR_ACQDONE_REG (100) // wait time in us after acquisition done to ensure there is no data in fifo
#define WAIT_TIME_US_PLL (10 * 1000) #define WAIT_TIME_US_PLL (10 * 1000)