mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-04-23 23:10:02 +02:00
Merge branch 'refactor' into shm
This commit is contained in:
commit
2dcef909ca
@ -1,9 +1,9 @@
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Path: slsDetectorPackage/slsDetectorServers/ctbDetectorServer
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URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
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Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
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Repsitory UUID: 1103f56256f3f8b5037343f9e9a2ef90139dc6d0
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Revision: 37
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URL: origin https://www.github.com/slsdetectorgroup/slsDetectorPackage
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Repository Root: origin https://www.github.com/slsdetectorgroup/slsDetectorPackage
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Repsitory UUID: 6765fd0dc89176b4eceaf5e2304ef808a316ba9b
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Revision: 38
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Branch: refactor
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Last Changed Author: Dhanya_Thattil
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Last Changed Rev: 4389
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Last Changed Date: 2019-03-08 14:05:26.000000002 +0100 ./RegisterDefs.h
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Last Changed Rev: 4394
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Last Changed Date: 2019-03-13 08:04:56.000000002 +0100 ./RegisterDefs.h
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@ -1,6 +1,6 @@
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#define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git"
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#define GITREPUUID "1103f56256f3f8b5037343f9e9a2ef90139dc6d0"
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#define GITURL "https://www.github.com/slsdetectorgroup/slsDetectorPackage"
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#define GITREPUUID "6765fd0dc89176b4eceaf5e2304ef808a316ba9b"
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#define GITAUTH "Dhanya_Thattil"
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#define GITREV 0x4389
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#define GITDATE 0x20190308
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#define GITREV 0x4394
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#define GITDATE 0x20190313
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#define GITBRANCH "refactor"
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@ -786,7 +786,7 @@ void setSpeed(enum speedVariable ind, int val) {
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case ADC_PHASE:
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case PHASE_SHIFT:
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FILE_LOG(logINFOBLUE, ("Configuring ADC Phase\n"));
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configurePhase(RUN_CLK, val);
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configurePhase(ADC_CLK, val);
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break;
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case DBIT_PHASE:
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FILE_LOG(logINFOBLUE, ("Configuring Dbit Phase\n"));
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@ -1639,6 +1639,12 @@ void configurePhase(enum CLKINDEX ind, int val) {
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FILE_LOG(logERROR, ("\tPhase provided for C%d(%s) outside limits\n", ind, clock_names[ind]));
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return;
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}
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int relativePhase = clkPhase[ind] - val;
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// same phase
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if (!relativePhase) {
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return;
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}
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FILE_LOG(logINFO, ("Configuring Phase of C%d(%s) to %d\n", ind, clock_names[ind], val));
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@ -1648,16 +1654,17 @@ void configurePhase(enum CLKINDEX ind, int val) {
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// set mode register to polling mode
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ALTERA_PLL_SetModePolling();
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int phase = 0, inv = 0;
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if (val > 0) {
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inv = 0;
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phase = val;
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int phase = 0;
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int maxShifts = ((ind == ADC_CLK) ? MAX_PHASE_SHIFTS_ADC_CLK : MAX_PHASE_SHIFTS_DBIT_CLK);
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// delay clk
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if (relativePhase > 0) {
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phase = (maxShifts - relativePhase);
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} else {
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inv = 1;
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val = -1 * val;
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phase = (~val);
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phase = (-1) * relativePhase;
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}
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FILE_LOG(logINFO, ("\tphase out %d (0x%08x), inv:%d\n", phase, phase, inv));
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FILE_LOG(logINFO, ("\tphase out %d (0x%08x)\n", phase, phase));
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ALTERA_PLL_SetPhaseShift(phase, (int)ind, 0);
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@ -80,7 +80,8 @@ enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7, D8, D9,
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/* Defines in the Firmware */
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#define MAX_PATTERN_LENGTH (0xFFFF)
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#define DIGITAL_IO_DELAY_MAXIMUM_PS ((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
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#define MAX_PHASE_SHIFTS_ADC_CLK (320)
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#define MAX_PHASE_SHIFTS_DBIT_CLK (32)
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#define WAIT_TME_US_FR_ACQDONE_REG (100) // wait time in us after acquisition done to ensure there is no data in fifo
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#define WAIT_TIME_US_PLL (10 * 1000)
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@ -1,9 +1,9 @@
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Path: slsDetectorPackage/slsDetectorServers/jungfrauDetectorServer
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URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
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Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
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Repsitory UUID: 93192c6e84a34ad3416f99b95e58356b609f61c6
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Revision: 24
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URL: origin https://www.github.com/slsdetectorgroup/slsDetectorPackage
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Repository Root: origin https://www.github.com/slsdetectorgroup/slsDetectorPackage
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Repsitory UUID: 6765fd0dc89176b4eceaf5e2304ef808a316ba9b
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Revision: 26
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Branch: refactor
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Last Changed Author: Dhanya_Thattil
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Last Changed Rev: 4370
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Last Changed Date: 2019-03-01 15:23:53.000000002 +0100 ./RegisterDefs.h
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Last Changed Rev: 4394
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Last Changed Date: 2019-03-13 08:04:56.000000002 +0100 ./RegisterDefs.h
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@ -1,6 +1,6 @@
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#define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git"
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#define GITREPUUID "93192c6e84a34ad3416f99b95e58356b609f61c6"
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#define GITURL "https://www.github.com/slsdetectorgroup/slsDetectorPackage"
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#define GITREPUUID "6765fd0dc89176b4eceaf5e2304ef808a316ba9b"
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#define GITAUTH "Dhanya_Thattil"
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#define GITREV 0x4370
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#define GITDATE 0x20190301
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#define GITREV 0x4394
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#define GITDATE 0x20190313
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#define GITBRANCH "refactor"
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@ -1255,29 +1255,25 @@ void configurePll() {
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#ifdef VIRTUAL
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return;
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#endif
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int32_t phase=0, inv=0;
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int32_t phase=0;
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// ensuring PLL is never configured with same phase
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if (clkPhase[1] == 0) {
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return;
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}
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FILE_LOG(logINFO, ("\tConfiguring PLL with phase in %d\n", clkPhase[1]));
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// delay ADC clk
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if (clkPhase[1]>0) {
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inv=0;
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phase=clkPhase[1];
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} else {
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inv=1;
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phase=-1*clkPhase[1];
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phase = MAX_PHASE_SHIFTS - clkPhase[1];
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}
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// advance adc clk
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else {
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phase = (-1) * clkPhase[1];
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}
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FILE_LOG(logDEBUG1, ("\tphase out %d (0x%08x)\n", phase, phase));
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if (inv) {
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ALTERA_PLL_SetPhaseShift(phase, 1, 0);
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} else {
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ALTERA_PLL_SetPhaseShift(phase, 0, 0);
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ALTERA_PLL_SetPhaseShift(phase, 2, 0);
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}
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ALTERA_PLL_SetPhaseShift(phase, 1, 0); // phase, 1: adc clk, 0:neg
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usleep(10000);
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}
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@ -88,6 +88,7 @@ enum NETWORKINDEX { TXN_FRAME };
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#define ADC_PHASE_HALF_SPEED (0x2D) //45
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#define ADC_PHASE_QUARTER_SPEED (0x2D) //45
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#define ADC_PORT_INVERT_VAL (0x453b2a9c)
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#define MAX_PHASE_SHIFTS (160)
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/* MSB & LSB DEFINES */
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#define MSB_OF_64_BIT_REG_OFST (32)
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@ -1,9 +1,9 @@
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Path: slsDetectorPackage/slsDetectorServers/moenchDetectorServer
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URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
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Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
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Repsitory UUID: ae5938799fb1bf7a5cb64bdb329f9c0d9ab44a03
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Revision: 15
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URL: origin https://www.github.com/slsdetectorgroup/slsDetectorPackage
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Repository Root: origin https://www.github.com/slsdetectorgroup/slsDetectorPackage
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Repsitory UUID: 6765fd0dc89176b4eceaf5e2304ef808a316ba9b
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Revision: 16
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Branch: refactor
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Last Changed Author: Dhanya_Thattil
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Last Changed Rev: 4393
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Last Changed Date: 2019-03-08 14:05:26.000000002 +0100 ./RegisterDefs.h
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Last Changed Rev: 4394
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Last Changed Date: 2019-03-13 08:04:56.000000002 +0100 ./RegisterDefs.h
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@ -1,6 +1,6 @@
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#define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git"
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#define GITREPUUID "ae5938799fb1bf7a5cb64bdb329f9c0d9ab44a03"
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#define GITURL "https://www.github.com/slsdetectorgroup/slsDetectorPackage"
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#define GITREPUUID "6765fd0dc89176b4eceaf5e2304ef808a316ba9b"
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#define GITAUTH "Dhanya_Thattil"
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#define GITREV 0x4393
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#define GITDATE 0x20190308
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#define GITREV 0x4394
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#define GITDATE 0x20190313
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#define GITBRANCH "refactor"
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@ -762,7 +762,7 @@ void setSpeed(enum speedVariable ind, int val) {
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case ADC_PHASE:
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case PHASE_SHIFT:
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FILE_LOG(logINFOBLUE, ("Configuring ADC Phase\n"));
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configurePhase(RUN_CLK, val);
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configurePhase(ADC_CLK, val);
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break;
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case DBIT_PHASE:
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FILE_LOG(logINFOBLUE, ("Configuring Dbit Phase\n"));
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@ -1274,6 +1274,12 @@ void configurePhase(enum CLKINDEX ind, int val) {
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FILE_LOG(logERROR, ("\tPhase provided for C%d(%s) outside limits\n", ind, clock_names[ind]));
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return;
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}
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int relativePhase = clkPhase[ind] - val;
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// same phase
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if (!relativePhase) {
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return;
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}
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FILE_LOG(logINFO, ("Configuring Phase of C%d(%s) to %d\n", ind, clock_names[ind], val));
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@ -1283,16 +1289,17 @@ void configurePhase(enum CLKINDEX ind, int val) {
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// set mode register to polling mode
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ALTERA_PLL_SetModePolling();
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int phase = 0, inv = 0;
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if (val > 0) {
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inv = 0;
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phase = val;
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int phase = 0;
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int maxShifts = ((ind == ADC_CLK) ? MAX_PHASE_SHIFTS_ADC_CLK : MAX_PHASE_SHIFTS_DBIT_CLK);
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// delay clk
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if (relativePhase > 0) {
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phase = (maxShifts - relativePhase);
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} else {
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inv = 1;
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val = -1 * val;
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phase = (~val);
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phase = (-1) * relativePhase;
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}
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FILE_LOG(logINFO, ("\tphase out %d (0x%08x), inv:%d\n", phase, phase, inv));
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FILE_LOG(logINFO, ("\tphase out %d (0x%08x)\n", phase, phase));
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ALTERA_PLL_SetPhaseShift(phase, (int)ind, 0);
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@ -61,7 +61,8 @@ enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7};
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/* Defines in the Firmware */
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#define MAX_PATTERN_LENGTH (0xFFFF)
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#define DIGITAL_IO_DELAY_MAXIMUM_PS ((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
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#define MAX_PHASE_SHIFTS_ADC_CLK (320)
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#define MAX_PHASE_SHIFTS_DBIT_CLK (32)
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#define WAIT_TME_US_FR_ACQDONE_REG (100) // wait time in us after acquisition done to ensure there is no data in fifo
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#define WAIT_TIME_US_PLL (10 * 1000)
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