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mythen3, gotthard2: bug fix- changing wrong pll phases when changing frequency
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@ -1929,7 +1929,7 @@ int setClockDivider(enum CLKINDEX ind, int val) {
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clkDivider[ind]));
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// phase is reset by pll (when setting output frequency)
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if (ind >= READOUT_C0) {
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if (ind < SYSTEM_C0) {
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clkPhase[READOUT_C0] = 0;
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clkPhase[READOUT_C1] = 0;
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} else {
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