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mythen3, gotthard2: bug fix- changing wrong pll phases when changing frequency

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This commit is contained in:
maliakal_d
2020-07-13 15:47:43 +02:00
parent bef35eb3d6
commit 293fda0c7a
5 changed files with 5 additions and 5 deletions
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slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServer_developer
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4
slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c
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@ -1710,7 +1710,7 @@ int setClockDivider(enum CLKINDEX ind, int val) {
}
// phase is reset by pll (when setting output frequency)
if (ind >= READOUT_C0) {
if (ind < SYSTEM_C0) {
clkPhase[READOUT_C0] = 0;
clkPhase[READOUT_C1] = 0;
} else {
@ -2500,4 +2500,4 @@ int getTotalNumberOfChannels() {
}
int getNumberOfChips() { return NCHIP; }
int getNumberOfDACs() { return NDAC; }
int getNumberOfChannelsPerChip() { return NCHAN; }
int getNumberOfChannelsPerChip() { return NCHAN; }

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slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer
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2
slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c
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@ -1929,7 +1929,7 @@ int setClockDivider(enum CLKINDEX ind, int val) {
clkDivider[ind]));
// phase is reset by pll (when setting output frequency)
if (ind >= READOUT_C0) {
if (ind < SYSTEM_C0) {
clkPhase[READOUT_C0] = 0;
clkPhase[READOUT_C1] = 0;
} else {