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https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-23 01:58:00 +02:00
g2 speed also requires dbit pipeline to be set
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slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServer_developer
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slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServer_developer
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@ -2083,24 +2083,40 @@ int setReadoutSpeed(int val) {
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case G2_108MHZ:
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LOG(logINFOBLUE, ("Setting readout speed to 108 MHz\n"));
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if (setClockDivider(READOUT_C0, SPEED_108_CLKDIV_0) == FAIL) {
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LOG(logERROR, ("Could not set readout speed to 108 MHz. Failed to set readout clk 0 to %d\n", SPEED_108_CLKDIV_0));
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return FAIL;
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}
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if (setClockDivider(READOUT_C1, SPEED_108_CLKDIV_1) == FAIL) {
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LOG(logERROR, ("Could not set readout speed to 108 MHz. Failed to set readout clk 1 to %d\n", SPEED_108_CLKDIV_1));
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return FAIL;
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}
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if (setPhase(READOUT_C1, SPEED_108_CLKPHASE_DEG_1, 1) == FAIL) {
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LOG(logERROR, ("Could not set readout speed to 108 MHz. Failed to set clk phase 1 %d deg\n", SPEED_108_CLKPHASE_DEG_1));
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return FAIL;
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}
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setDBITPipeline(SPEED_144_DBIT_PIPELINE);
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if (getDBITPipeline() != SPEED_144_DBIT_PIPELINE) {
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LOG(logERROR, ("Could not set readout speed to 108 MHz. Failed to set dbitpipeline to %d \n", SPEED_144_DBIT_PIPELINE));
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return FAIL;
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}
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break;
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case G2_144MHZ:
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LOG(logINFOBLUE, ("Setting readout speed to 144 MHz\n"));
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if (setClockDivider(READOUT_C0, SPEED_144_CLKDIV_0) == FAIL) {
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LOG(logERROR, ("Could not set readout speed to 144 MHz. Failed to set readout clk 0 to %d\n", SPEED_144_CLKDIV_0));
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return FAIL;
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}
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if (setClockDivider(READOUT_C1, SPEED_144_CLKDIV_1) == FAIL) {
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LOG(logERROR, ("Could not set readout speed to 144 MHz. Failed to set readout clk 1 to %d\n", SPEED_144_CLKDIV_1));
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return FAIL;
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}
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if (setPhase(READOUT_C1, SPEED_144_CLKPHASE_DEG_1, 1) == FAIL) {
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LOG(logERROR, ("Could not set readout speed to 144 MHz. Failed to set clk phase 1 %d deg\n", SPEED_144_CLKPHASE_DEG_1));
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return FAIL;
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}
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setDBITPipeline(SPEED_144_DBIT_PIPELINE);
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if (getDBITPipeline() != SPEED_144_DBIT_PIPELINE) {
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LOG(logERROR, ("Could not set readout speed to 144 MHz. Failed to set dbitpipeline to %d \n", SPEED_144_DBIT_PIPELINE));
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return FAIL;
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}
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break;
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@ -67,9 +67,11 @@
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#define SPEED_144_CLKDIV_0 (6)
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#define SPEED_144_CLKDIV_1 (6)
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#define SPEED_144_CLKPHASE_DEG_1 (122) // 125 not possible
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#define SPEED_144_DBIT_PIPELINE (1)
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#define SPEED_108_CLKDIV_0 (8)
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#define SPEED_108_CLKDIV_1 (8)
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#define SPEED_108_CLKPHASE_DEG_1 (268) // 270 not possible
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#define SPEED_108_DBIT_PIPELINE (1)
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/* Firmware Definitions */
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#define FIXED_PLL_FREQUENCY (20000000) // 20MHz
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