g2 speed also requires dbit pipeline to be set

This commit is contained in:
maliakal_d 2021-11-24 16:59:20 +01:00
parent 2c57d5f72d
commit 1ed10acc01
5 changed files with 29 additions and 3 deletions

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@ -19,8 +19,8 @@ This document describes the differences between v6.0.1 and v6.0.0.
1. New or Changed Features
==========================
API
---
Client
------
1. Kernel version
Commandline: kernelversion, API: getKernelVersion
@ -51,6 +51,14 @@ This document describes the differences between v6.0.1 and v6.0.0.
it will delete the empty file. Ofcourse, command line "--update" will
overwrite any file detection and start server in update mode.
Detector Server
---------------
1. [Gotthard2] speed
Ensuring dbitpipeline is default when changing speed. This has an effect
only if dbitpipeline was changed in between.
2. Resolved Issues

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@ -2083,24 +2083,40 @@ int setReadoutSpeed(int val) {
case G2_108MHZ:
LOG(logINFOBLUE, ("Setting readout speed to 108 MHz\n"));
if (setClockDivider(READOUT_C0, SPEED_108_CLKDIV_0) == FAIL) {
LOG(logERROR, ("Could not set readout speed to 108 MHz. Failed to set readout clk 0 to %d\n", SPEED_108_CLKDIV_0));
return FAIL;
}
if (setClockDivider(READOUT_C1, SPEED_108_CLKDIV_1) == FAIL) {
LOG(logERROR, ("Could not set readout speed to 108 MHz. Failed to set readout clk 1 to %d\n", SPEED_108_CLKDIV_1));
return FAIL;
}
if (setPhase(READOUT_C1, SPEED_108_CLKPHASE_DEG_1, 1) == FAIL) {
LOG(logERROR, ("Could not set readout speed to 108 MHz. Failed to set clk phase 1 %d deg\n", SPEED_108_CLKPHASE_DEG_1));
return FAIL;
}
setDBITPipeline(SPEED_144_DBIT_PIPELINE);
if (getDBITPipeline() != SPEED_144_DBIT_PIPELINE) {
LOG(logERROR, ("Could not set readout speed to 108 MHz. Failed to set dbitpipeline to %d \n", SPEED_144_DBIT_PIPELINE));
return FAIL;
}
break;
case G2_144MHZ:
LOG(logINFOBLUE, ("Setting readout speed to 144 MHz\n"));
if (setClockDivider(READOUT_C0, SPEED_144_CLKDIV_0) == FAIL) {
LOG(logERROR, ("Could not set readout speed to 144 MHz. Failed to set readout clk 0 to %d\n", SPEED_144_CLKDIV_0));
return FAIL;
}
if (setClockDivider(READOUT_C1, SPEED_144_CLKDIV_1) == FAIL) {
LOG(logERROR, ("Could not set readout speed to 144 MHz. Failed to set readout clk 1 to %d\n", SPEED_144_CLKDIV_1));
return FAIL;
}
if (setPhase(READOUT_C1, SPEED_144_CLKPHASE_DEG_1, 1) == FAIL) {
LOG(logERROR, ("Could not set readout speed to 144 MHz. Failed to set clk phase 1 %d deg\n", SPEED_144_CLKPHASE_DEG_1));
return FAIL;
}
setDBITPipeline(SPEED_144_DBIT_PIPELINE);
if (getDBITPipeline() != SPEED_144_DBIT_PIPELINE) {
LOG(logERROR, ("Could not set readout speed to 144 MHz. Failed to set dbitpipeline to %d \n", SPEED_144_DBIT_PIPELINE));
return FAIL;
}
break;

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@ -67,9 +67,11 @@
#define SPEED_144_CLKDIV_0 (6)
#define SPEED_144_CLKDIV_1 (6)
#define SPEED_144_CLKPHASE_DEG_1 (122) // 125 not possible
#define SPEED_144_DBIT_PIPELINE (1)
#define SPEED_108_CLKDIV_0 (8)
#define SPEED_108_CLKDIV_1 (8)
#define SPEED_108_CLKPHASE_DEG_1 (268) // 270 not possible
#define SPEED_108_DBIT_PIPELINE (1)
/* Firmware Definitions */
#define FIXED_PLL_FREQUENCY (20000000) // 20MHz

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@ -8,8 +8,8 @@
#define APIGUI 0x211021
#define APICTB 0x211124
#define APIGOTTHARD 0x211124
#define APIGOTTHARD2 0x211124
#define APIJUNGFRAU 0x211124
#define APIMYTHEN3 0x211124
#define APIMOENCH 0x211124
#define APIEIGER 0x211124
#define APIGOTTHARD2 0x211124