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g2 speed also requires dbit pipeline to be set
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12
RELEASE.txt
12
RELEASE.txt
@ -19,8 +19,8 @@ This document describes the differences between v6.0.1 and v6.0.0.
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1. New or Changed Features
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==========================
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API
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---
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Client
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------
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1. Kernel version
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Commandline: kernelversion, API: getKernelVersion
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@ -51,6 +51,14 @@ This document describes the differences between v6.0.1 and v6.0.0.
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it will delete the empty file. Ofcourse, command line "--update" will
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overwrite any file detection and start server in update mode.
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Detector Server
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---------------
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1. [Gotthard2] speed
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Ensuring dbitpipeline is default when changing speed. This has an effect
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only if dbitpipeline was changed in between.
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2. Resolved Issues
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BIN
slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServer_developer
Executable file
BIN
slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServer_developer
Executable file
Binary file not shown.
@ -2083,24 +2083,40 @@ int setReadoutSpeed(int val) {
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case G2_108MHZ:
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LOG(logINFOBLUE, ("Setting readout speed to 108 MHz\n"));
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if (setClockDivider(READOUT_C0, SPEED_108_CLKDIV_0) == FAIL) {
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LOG(logERROR, ("Could not set readout speed to 108 MHz. Failed to set readout clk 0 to %d\n", SPEED_108_CLKDIV_0));
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return FAIL;
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}
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if (setClockDivider(READOUT_C1, SPEED_108_CLKDIV_1) == FAIL) {
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LOG(logERROR, ("Could not set readout speed to 108 MHz. Failed to set readout clk 1 to %d\n", SPEED_108_CLKDIV_1));
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return FAIL;
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}
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if (setPhase(READOUT_C1, SPEED_108_CLKPHASE_DEG_1, 1) == FAIL) {
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LOG(logERROR, ("Could not set readout speed to 108 MHz. Failed to set clk phase 1 %d deg\n", SPEED_108_CLKPHASE_DEG_1));
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return FAIL;
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}
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setDBITPipeline(SPEED_144_DBIT_PIPELINE);
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if (getDBITPipeline() != SPEED_144_DBIT_PIPELINE) {
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LOG(logERROR, ("Could not set readout speed to 108 MHz. Failed to set dbitpipeline to %d \n", SPEED_144_DBIT_PIPELINE));
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return FAIL;
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}
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break;
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case G2_144MHZ:
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LOG(logINFOBLUE, ("Setting readout speed to 144 MHz\n"));
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if (setClockDivider(READOUT_C0, SPEED_144_CLKDIV_0) == FAIL) {
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LOG(logERROR, ("Could not set readout speed to 144 MHz. Failed to set readout clk 0 to %d\n", SPEED_144_CLKDIV_0));
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return FAIL;
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}
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if (setClockDivider(READOUT_C1, SPEED_144_CLKDIV_1) == FAIL) {
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LOG(logERROR, ("Could not set readout speed to 144 MHz. Failed to set readout clk 1 to %d\n", SPEED_144_CLKDIV_1));
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return FAIL;
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}
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if (setPhase(READOUT_C1, SPEED_144_CLKPHASE_DEG_1, 1) == FAIL) {
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LOG(logERROR, ("Could not set readout speed to 144 MHz. Failed to set clk phase 1 %d deg\n", SPEED_144_CLKPHASE_DEG_1));
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return FAIL;
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}
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setDBITPipeline(SPEED_144_DBIT_PIPELINE);
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if (getDBITPipeline() != SPEED_144_DBIT_PIPELINE) {
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LOG(logERROR, ("Could not set readout speed to 144 MHz. Failed to set dbitpipeline to %d \n", SPEED_144_DBIT_PIPELINE));
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return FAIL;
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}
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break;
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@ -67,9 +67,11 @@
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#define SPEED_144_CLKDIV_0 (6)
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#define SPEED_144_CLKDIV_1 (6)
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#define SPEED_144_CLKPHASE_DEG_1 (122) // 125 not possible
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#define SPEED_144_DBIT_PIPELINE (1)
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#define SPEED_108_CLKDIV_0 (8)
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#define SPEED_108_CLKDIV_1 (8)
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#define SPEED_108_CLKPHASE_DEG_1 (268) // 270 not possible
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#define SPEED_108_DBIT_PIPELINE (1)
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/* Firmware Definitions */
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#define FIXED_PLL_FREQUENCY (20000000) // 20MHz
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@ -8,8 +8,8 @@
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#define APIGUI 0x211021
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#define APICTB 0x211124
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#define APIGOTTHARD 0x211124
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#define APIGOTTHARD2 0x211124
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#define APIJUNGFRAU 0x211124
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#define APIMYTHEN3 0x211124
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#define APIMOENCH 0x211124
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#define APIEIGER 0x211124
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#define APIGOTTHARD2 0x211124
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