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jungfrau server: pll moved out to remove redundancy

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This commit is contained in:
maliakal_d
2019-01-11 14:48:58 +01:00
parent de2ebad2ed
commit 1bbb352743
15 changed files with 269 additions and 376 deletions
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1
slsDetectorServers/jungfrauDetectorServer/ALTERA_PLL.h Symbolic link
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@@ -0,0 +1 @@
../slsDetectorServer/ALTERA_PLL.h

18
slsDetectorServers/jungfrauDetectorServer/RegisterDefs.h
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@@ -239,16 +239,16 @@
#define PLL_PARAM_REG (0x50 << MEM_MAP_SHIFT)
/* Reconfiguratble PLL Control Regiser */
#define PLL_CONTROL_REG (0x51 << MEM_MAP_SHIFT)
#define PLL_CNTRL_REG (0x51 << MEM_MAP_SHIFT)
#define PLL_CTRL_RECONFIG_RST_OFST (0) //parameter reset
#define PLL_CTRL_RECONFIG_RST_MSK (0x00000001 << PLL_CTRL_RECONFIG_RST_OFST) //parameter reset
#define PLL_CTRL_WR_PARAMETER_OFST (2)
#define PLL_CTRL_WR_PARAMETER_MSK (0x00000001 << PLL_CTRL_WR_PARAMETER_OFST)
#define PLL_CTRL_RST_OFST (3)
#define PLL_CTRL_RST_MSK (0x00000001 << PLL_CTRL_RST_OFST)
#define PLL_CTRL_ADDR_OFST (16)
#define PLL_CTRL_ADDR_MSK (0x0000003F << PLL_CTRL_ADDR_OFST)
#define PLL_CNTRL_RCNFG_PRMTR_RST_OFST (0) //parameter reset
#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK (0x00000001 << PLL_CNTRL_RCNFG_PRMTR_RST_OFST) //parameter reset
#define PLL_CNTRL_WR_PRMTR_OFST (2)
#define PLL_CNTRL_WR_PRMTR_MSK (0x00000001 << PLL_CNTRL_WR_PRMTR_OFST)
#define PLL_CNTRL_PLL_RST_OFST (3)
#define PLL_CNTRL_PLL_RST_MSK (0x00000001 << PLL_CNTRL_PLL_RST_OFST)
#define PLL_CNTRL_ADDR_OFST (16)
#define PLL_CNTRL_ADDR_MSK (0x0000003F << PLL_CNTRL_ADDR_OFST)
/* Sample Register (Obsolete) */
#define SAMPLE_REG (0x59 << MEM_MAP_SHIFT)

BIN
slsDetectorServers/jungfrauDetectorServer/bin/jungfrauDetectorServer_refactor
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Binary file not shown.

8
slsDetectorServers/jungfrauDetectorServer/gitInfo.txt
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@@ -1,9 +1,9 @@
Path: slsDetectorPackage/slsDetectorServers/jungfrauDetectorServer
URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
Repsitory UUID: b5b5ce5c3782a201b449141448ebe99c69515c18
Revision: 21
Repsitory UUID: de2ebad2ed07a85f70b40490b4e07d46b3ac1ff6
Revision: 22
Branch: refactor
Last Changed Author: Dhanya_Thattil
Last Changed Rev: 4214
Last Changed Date: 2019-01-10 11:46:27.000000002 +0100 ./RegisterDefs.h
Last Changed Rev: 4228
Last Changed Date: 2019-01-11 11:59:57.000000002 +0100 ./RegisterDefs.h

6
slsDetectorServers/jungfrauDetectorServer/gitInfoJungfrau.h
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@@ -1,6 +1,6 @@
#define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git"
#define GITREPUUID "b5b5ce5c3782a201b449141448ebe99c69515c18"
#define GITREPUUID "de2ebad2ed07a85f70b40490b4e07d46b3ac1ff6"
#define GITAUTH "Dhanya_Thattil"
#define GITREV 0x4214
#define GITDATE 0x20190110
#define GITREV 0x4228
#define GITDATE 0x20190111
#define GITBRANCH "refactor"

55
slsDetectorServers/jungfrauDetectorServer/slsDetectorFunctionList.c
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@@ -3,10 +3,11 @@
#include "versionAPI.h"
#include "logger.h"
#ifndef VIRTUAL
#include "AD9257.h" // commonServerFunctions.h, blackfin.h, ansi.h
#include "LTC2620.h" // dacs
#include "MAX1932.h" // hv
#include "ALTERA_PLL.h" // pll
#ifndef VIRTUAL
#include "programfpga.h"
#else
#include "blackfin.h"
@@ -392,7 +393,7 @@ void initStopServer() {
void setupDetector() {
FILE_LOG(logINFO, ("This Server is for 1 Jungfrau module (500k)\n"));
resetPLL();
ALTERA_PLL_ResetPLL();
resetCore();
resetPeripheral();
cleanFifos();
@@ -413,6 +414,9 @@ void setupDetector() {
LTC2620_Configure();
setDefaultDacs();
// altera pll
ALTERA_PLL_SetDefines(PLL_CNTRL_REG, PLL_PARAM_REG, PLL_CNTRL_RCNFG_PRMTR_RST_MSK, PLL_CNTRL_WR_PRMTR_MSK, PLL_CNTRL_PLL_RST_MSK, PLL_CNTRL_ADDR_MSK, PLL_CNTRL_ADDR_OFST);
bus_w(DAQ_REG, 0x0); /* Only once at server startup */
FILE_LOG(logINFOBLUE, ("Setting Default parameters\n"));
@@ -1223,41 +1227,6 @@ int getPhase() {
}
void resetPLL() {
#ifdef VIRTUAL
return;
#endif
FILE_LOG(logINFO, ("Resetting PLL\n"));
// reset PLL Reconfiguration and PLL
bus_w(PLL_CONTROL_REG, bus_r(PLL_CONTROL_REG) | PLL_CTRL_RECONFIG_RST_MSK | PLL_CTRL_RST_MSK);
usleep(100);
bus_w(PLL_CONTROL_REG, bus_r(PLL_CONTROL_REG) & ~PLL_CTRL_RECONFIG_RST_MSK & ~PLL_CTRL_RST_MSK);
}
u_int32_t setPllReconfigReg(u_int32_t reg, u_int32_t val) {
#ifdef VIRTUAL
return val;
#endif
FILE_LOG(logINFO, ("Setting PLL Reconfig Reg\n"));
// set parameter
bus_w(PLL_PARAM_REG, val);
// set address
bus_w(PLL_CONTROL_REG, (reg << PLL_CTRL_ADDR_OFST) & PLL_CTRL_ADDR_MSK);
usleep(10*1000);
//write parameter
bus_w(PLL_CONTROL_REG, bus_r(PLL_CONTROL_REG) | PLL_CTRL_WR_PARAMETER_MSK);
bus_w(PLL_CONTROL_REG, bus_r(PLL_CONTROL_REG) & ~PLL_CTRL_WR_PARAMETER_MSK);
usleep(10*1000);
return val;
}
void configurePll() {
#ifdef VIRTUAL
return;
@@ -1280,17 +1249,11 @@ void configurePll() {
FILE_LOG(logDEBUG1, ("\tphase out %d (0x%08x)\n", phase, phase));
if (inv) {
val = ((phase << PLL_SHIFT_NUM_SHIFTS_OFST) & PLL_SHIFT_NUM_SHIFTS_MSK) + PLL_SHIFT_CNT_SLCT_C1_VAL + PLL_SHIFT_UP_DOWN_NEG_VAL;
FILE_LOG(logDEBUG1, ("\tphase word 0x%08x\n", val));
setPllReconfigReg(PLL_PHASE_SHIFT_REG, val);
ALTERA_PLL_SetPhaseShift(phase, 1, 0);
} else {
val = ((phase << PLL_SHIFT_NUM_SHIFTS_OFST) & PLL_SHIFT_NUM_SHIFTS_MSK) + PLL_SHIFT_CNT_SLCT_C0_VAL + PLL_SHIFT_UP_DOWN_NEG_VAL;
FILE_LOG(logDEBUG1, ("\tphase word 0x%08x\n", val));
setPllReconfigReg(PLL_PHASE_SHIFT_REG, val);
ALTERA_PLL_SetPhaseShift(phase, 0, 0);
FILE_LOG(logDEBUG1, ("\tphase word 0x%08x\n", val));
val = ((phase << PLL_SHIFT_NUM_SHIFTS_OFST) & PLL_SHIFT_NUM_SHIFTS_MSK) + PLL_SHIFT_CNT_SLCT_C2_VAL;
setPllReconfigReg(PLL_PHASE_SHIFT_REG, val);
ALTERA_PLL_SetPhaseShift(phase, 2, 0);
}
usleep(10000);
}

44
slsDetectorServers/jungfrauDetectorServer/slsDetectorServer_defs.h
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@@ -92,47 +92,3 @@ enum NETWORKINDEX { TXN_FRAME };
#define LSB_OF_64_BIT_REG_OFST (0)
#define BIT_32_MSK (0xFFFFFFFF)
/** PLL Reconfiguration Registers */
//https://www.altera.com/documentation/mcn1424769382940.html
#define PLL_MODE_REG (0x00)
#define PLL_STATUS_REG (0x01)
#define PLL_START_REG (0x02)
#define PLL_N_COUNTER_REG (0x03)
#define PLL_M_COUNTER_REG (0x04)
#define PLL_C_COUNTER_REG (0x05)
#define PLL_PHASE_SHIFT_REG (0x06)
#define PLL_SHIFT_NUM_SHIFTS_OFST (0)
#define PLL_SHIFT_NUM_SHIFTS_MSK (0x0000FFFF << PLL_SHIFT_NUM_SHIFTS_OFST)
#define PLL_SHIFT_CNT_SELECT_OFST (16)
#define PLL_SHIFT_CNT_SELECT_MSK (0x0000001F << PLL_SHIFT_CNT_SELECT_OFST)
#define PLL_SHIFT_CNT_SLCT_C0_VAL ((0x0 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C1_VAL ((0x1 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C2_VAL ((0x2 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C3_VAL ((0x3 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C4_VAL ((0x4 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C5_VAL ((0x5 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C6_VAL ((0x6 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C7_VAL ((0x7 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C8_VAL ((0x8 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C9_VAL ((0x9 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C10_VAL ((0x10 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C11_VAL ((0x11 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C12_VAL ((0x12 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C13_VAL ((0x13 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C14_VAL ((0x14 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C15_VAL ((0x15 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C16_VAL ((0x16 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C17_VAL ((0x17 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_UP_DOWN_OFST (21)
#define PLL_SHIFT_UP_DOWN_MSK (0x00000001 << PLL_SHIFT_UP_DOWN_OFST)
#define PLL_SHIFT_UP_DOWN_NEG_VAL ((0x0 << PLL_SHIFT_UP_DOWN_OFST) & PLL_SHIFT_UP_DOWN_MSK)
#define PLL_SHIFT_UP_DOWN_POS_VAL ((0x1 << PLL_SHIFT_UP_DOWN_OFST) & PLL_SHIFT_UP_DOWN_MSK)
#define PLL_K_COUNTER_REG (0x07)
#define PLL_BANDWIDTH_REG (0x08)
#define PLL_CHARGEPUMP_REG (0x09)
#define PLL_VCO_DIV_REG (0x1c)
#define PLL_MIF_REG (0x1f)