diff --git a/slsDetectorServers/ctbDetectorServer/ALTERA_PLL.h b/slsDetectorServers/ctbDetectorServer/ALTERA_PLL.h
new file mode 120000
index 000000000..e665f009d
--- /dev/null
+++ b/slsDetectorServers/ctbDetectorServer/ALTERA_PLL.h
@@ -0,0 +1 @@
+../slsDetectorServer/ALTERA_PLL.h
\ No newline at end of file
diff --git a/slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c b/slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c
index 0f78a2534..b855dbce4 100644
--- a/slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c
+++ b/slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c
@@ -3,12 +3,14 @@
 #include "versionAPI.h"
 #include "logger.h"
 
-#ifndef VIRTUAL
+
 #include "AD9257.h"		// commonServerFunctions.h, blackfin.h, ansi.h
 #include "AD7689.h"     // slow adcs
 #include "LTC2620.h"    // dacs
 #include "MAX1932.h"    // hv
 #include "INA226.h"     // i2c
+#include "ALTERA_PLL.h" // pll
+#ifndef VIRTUAL
 #include "programfpga.h"
 #else
 #include "blackfin.h"
@@ -473,7 +475,7 @@ void setupDetector() {
     now_ptr = 0;
 
 
-    resetPLL();
+    ALTERA_PLL_ResetPLLAndReconfiguration();
     resetCore();
     resetPeripheral();
     cleanFifos();
@@ -518,6 +520,9 @@ void setupDetector() {
 	    }
 	}
 
+	// altera pll
+	ALTERA_PLL_SetDefines(PLL_CNTRL_REG, PLL_PARAM_REG, PLL_CNTRL_RCNFG_PRMTR_RST_MSK, PLL_CNTRL_WR_PRMTR_MSK, PLL_CNTRL_PLL_RST_MSK, PLL_CNTRL_ADDR_MSK, PLL_CNTRL_ADDR_OFST);
+
     bus_w(ADC_PORT_INVERT_REG, ADC_PORT_INVERT_VAL);//FIXME:  got from moench config file
 
 	FILE_LOG(logINFOBLUE, ("Setting Default parameters\n"));
@@ -1561,35 +1566,6 @@ int sendUDP(int enable) {
     return ((bus_r(addr) & CONFIG_GB10_SND_UDP_MSK) >> CONFIG_GB10_SND_UDP_OFST);
 }
 
-void resetPLL() {
-#ifdef VIRTUAL
-    return;
-#endif
-    FILE_LOG(logINFO, ("Resetting PLL\n"));
-	// reset PLL Reconfiguration and PLL
-	bus_w(PLL_CNTRL_REG, bus_r(PLL_CNTRL_REG) | PLL_CNTRL_RCNFG_PRMTR_RST_MSK | PLL_CNTRL_PLL_RST_MSK);
-	usleep(WAIT_TIME_US_PLL);
-	bus_w(PLL_CNTRL_REG, bus_r(PLL_CNTRL_REG) & ~PLL_CNTRL_RCNFG_PRMTR_RST_MSK & ~PLL_CNTRL_PLL_RST_MSK);
-}
-
-void setPllReconfigReg(uint32_t reg, uint32_t val) {
-#ifdef VIRTUAL
-    return val;
-#endif
-    FILE_LOG(logINFO, ("Setting PLL Reconfig Reg\n"));
-	// set parameter
-	bus_w(PLL_PARAM_REG, val);
-
-	// set address
-	bus_w(PLL_CNTRL_REG, (reg << PLL_CNTRL_ADDR_OFST) & PLL_CNTRL_ADDR_MSK);
-	usleep(WAIT_TIME_US_PLL);
-
-	//write parameter
-	bus_w(PLL_CNTRL_REG, bus_r(PLL_CNTRL_REG) | PLL_CNTRL_WR_PRMTR_MSK);
-	bus_w(PLL_CNTRL_REG, bus_r(PLL_CNTRL_REG) & ~PLL_CNTRL_WR_PRMTR_MSK);
-	usleep(WAIT_TIME_US_PLL);
-}
-
 // ind can only be ADC_CLK or DBIT_CLK
 void configurePhase(CLKINDEX ind, int val) {
     if (st > 65535 || st < -65535) {
@@ -1600,12 +1576,10 @@ void configurePhase(CLKINDEX ind, int val) {
     FILE_LOG(logINFO, ("Configuring Phase of C%d to %d\n", ind, val));
 
     // reset only pll
-    bus_w(PLL_CNTRL_REG, bus_r(PLL_CNTRL_REG) | PLL_CNTRL_PLL_RST_MSK);
-    usleep(WAIT_TIME_US_PLL);
-    bus_w(PLL_CNTRL_REG, bus_r(PLL_CNTRL_REG) & ~PLL_CNTRL_PLL_RST_MSK);
+    ALTERA_PLL_ResetPLL();
 
     // set mode register to polling mode
-    setPllReconfigReg(PLL_MODE_REG, PLL_MODE_PLLNG_MD_VAL);
+    ALTERA_PLL_SetModePolling();
 
     int phase = 0, inv = 0;
     if (val > 0) {
@@ -1618,13 +1592,7 @@ void configurePhase(CLKINDEX ind, int val) {
     }
     FILE_LOG(logINFO, ("\tphase out %d (0x%08x), inv:%d\n", phase, phase, inv));
 
-    uint32_t value = (((phase << PLL_SHIFT_NUM_SHIFTS_OFST) & PLL_SHIFT_NUM_SHIFTS_MSK) |
-             (((int)ind << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK));
-    FILE_LOG(logDEBUG1, ("\tC%d phase word:0x%08x\n", ind, value));
-
-    // write phase shift
-    setPllReconfigReg(PLL_PHASE_SHIFT_REG, value);
-    usleep(WAIT_TIME_US_PLL);
+    ALTERA_PLL_SetPhaseShift(phase, (int)ind, 0);
 
     clkPhase[ind] = val;
 }
@@ -1645,35 +1613,8 @@ void configureFrequency(CLKINDEX ind, int val) {
         return getPhase(ind);
     }
 
-    // calculate output frequency
-    uint32_t total_div =  PLL_VCO_FREQ_MHZ / val;
-
-    // assume 50% duty cycle
-    uint32_t low_count = total_div / 2;
-    uint32_t high_count = low_count;
-    uint32_t odd_division = 0;
-
-    // odd division
-    if (total_div > (2 * low_count)) {
-        ++high_count;
-        odd_division = 1;
-    }
-    FILE_LOG(logINFO, ("\tC%d: Low:%d, High:%d, Odd:%d\n", ind, low_count, high_count, odd_division));
-
-    uint32_t val = (((low_count << PLL_C_COUNTER_LW_CNT_OFST) & PLL_C_COUNTER_LW_CNT_MSK) |
-            ((high_count << PLL_C_COUNTER_HGH_CNT_OFST) & PLL_C_COUNTER_HGH_CNT_MSK) |
-        ((odd_division << PLL_C_COUNTER_ODD_DVSN_OFST) & PLL_C_COUNTER_ODD_DVSN_MSK) |
-        (((int)ind << PLL_C_COUNTER_SLCT_OFST) & PLL_C_COUNTER_SLCT_MSK));
-    FILE_LOG(logDEBUG1, ("\tC%d word:0x%08x\n", ind, val));
-
-    // write frequency (post-scale output counter C)
-    setPllReconfigReg(PLL_C_COUNTER_REG, val);
-    usleep(WAIT_TIME_US_PLL);
-
-    // reset only PLL
-    bus_w(PLL_CNTRL_REG, bus_r(PLL_CNTRL_REG) | PLL_CNTRL_PLL_RST_MSK);
-    usleep(WAIT_TIME_US_PLL);
-    bus_w(PLL_CNTRL_REG, bus_r(PLL_CNTRL_REG) & ~PLL_CNTRL_PLL_RST_MSK);
+    // Calculate and set output frequency
+    ALTERA_PLL_SetOuputFrequency (ind, PLL_VCO_FREQ_MHZ);
 
     clkDivider[ind] = PLL_VCO_FREQ_MHZ / (low_count + high_count);
     FILE_LOG(logINFO, ("\tC%d: Frequency set to %d MHz\n", ind, clkDivider[ind]));
diff --git a/slsDetectorServers/ctbDetectorServer/slsDetectorServer_defs.h b/slsDetectorServers/ctbDetectorServer/slsDetectorServer_defs.h
index 772795859..77a0364d5 100644
--- a/slsDetectorServers/ctbDetectorServer/slsDetectorServer_defs.h
+++ b/slsDetectorServers/ctbDetectorServer/slsDetectorServer_defs.h
@@ -87,67 +87,3 @@ enum DACINDEX               {D0, D1, D2, D3, D4, D5, D6, D7, D8, D9,
 #define MAXIMUM_ADC_CLK             (40)
 #define PLL_VCO_FREQ_MHZ            (400)
 
-/** PLL Reconfiguration Registers */
-//https://www.altera.com/documentation/mcn1424769382940.html
-#define PLL_MODE_REG 				    (0x00)
-
-#define PLL_MODE_WT_RQUST_VAL           (0)
-#define PLL_MODE_PLLNG_MD_VAL           (1)
-
-#define PLL_STATUS_REG 				    (0x01)
-#define PLL_START_REG 				    (0x02)
-#define PLL_N_COUNTER_REG 			    (0x03)
-#define PLL_M_COUNTER_REG 			    (0x04)
-#define PLL_C_COUNTER_REG 			    (0x05)
-
-#define PLL_C_COUNTER_LW_CNT_OFST       (0)
-#define PLL_C_COUNTER_LW_CNT_MSK        (0x000000FF << PLL_C_COUNTER_LW_CNT_OFST)
-#define PLL_C_COUNTER_HGH_CNT_OFST      (8)
-#define PLL_C_COUNTER_HGH_CNT_MSK       (0x000000FF << PLL_C_COUNTER_HGH_CNT_OFST)
-/* total_div = lw_cnt + hgh_cnt */
-#define PLL_C_COUNTER_BYPSS_ENBL_OFST   (16)
-#define PLL_C_COUNTER_BYPSS_ENBL_MSK    (0x00000001 << PLL_C_COUNTER_BYPSS_ENBL_OFST)
-/* if bypss_enbl = 0, fout = f(vco)/total_div; else fout = f(vco) (c counter is bypassed) */
-#define PLL_C_COUNTER_ODD_DVSN_OFST     (17)
-#define PLL_C_COUNTER_ODD_DVSN_MSK      (0x00000001 << PLL_C_COUNTER_ODD_DVSN_OFST)
-/** if odd_dvsn = 0 (even), duty cycle = hgh_cnt/ total_div; else duty cycle = (hgh_cnt - 0.5) / total_div */
-#define PLL_C_COUNTER_SLCT_OFST         (18)
-#define PLL_C_COUNTER_SLCT_MSK          (0x0000001F << PLL_C_COUNTER_SLCT_OFST)
-
-#define PLL_PHASE_SHIFT_REG			    (0x06)
-
-#define PLL_SHIFT_NUM_SHIFTS_OFST	    (0)
-#define PLL_SHIFT_NUM_SHIFTS_MSK	    (0x0000FFFF << PLL_SHIFT_NUM_SHIFTS_OFST)
-
-#define PLL_SHIFT_CNT_SELECT_OFST	    (16)
-#define PLL_SHIFT_CNT_SELECT_MSK	    (0x0000001F << PLL_SHIFT_CNT_SELECT_OFST)
-#define PLL_SHIFT_CNT_SLCT_C0_VAL	    ((0x0 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C1_VAL	    ((0x1 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C2_VAL	    ((0x2 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C3_VAL	    ((0x3 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C4_VAL	    ((0x4 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C5_VAL	    ((0x5 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C6_VAL	    ((0x6 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C7_VAL	    ((0x7 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C8_VAL	    ((0x8 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C9_VAL	    ((0x9 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C10_VAL	    ((0x10 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C11_VAL	    ((0x11 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C12_VAL	    ((0x12 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C13_VAL	    ((0x13 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C14_VAL	    ((0x14 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C15_VAL	    ((0x15 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C16_VAL	    ((0x16 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C17_VAL	    ((0x17 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-
-#define PLL_SHIFT_UP_DOWN_OFST		    (21)
-#define PLL_SHIFT_UP_DOWN_MSK		    (0x00000001 << PLL_SHIFT_UP_DOWN_OFST)
-#define PLL_SHIFT_UP_DOWN_NEG_VAL	    ((0x0 << PLL_SHIFT_UP_DOWN_OFST) & PLL_SHIFT_UP_DOWN_MSK)
-#define PLL_SHIFT_UP_DOWN_POS_VAL	    ((0x1 << PLL_SHIFT_UP_DOWN_OFST) & PLL_SHIFT_UP_DOWN_MSK)
-
-#define PLL_K_COUNTER_REG 			    (0x07)
-#define PLL_BANDWIDTH_REG 			    (0x08)
-#define PLL_CHARGEPUMP_REG 			    (0x09)
-#define PLL_VCO_DIV_REG 			    (0x1c)
-#define PLL_MIF_REG 				    (0x1f)
-
diff --git a/slsDetectorServers/jungfrauDetectorServer/ALTERA_PLL.h b/slsDetectorServers/jungfrauDetectorServer/ALTERA_PLL.h
new file mode 120000
index 000000000..e665f009d
--- /dev/null
+++ b/slsDetectorServers/jungfrauDetectorServer/ALTERA_PLL.h
@@ -0,0 +1 @@
+../slsDetectorServer/ALTERA_PLL.h
\ No newline at end of file
diff --git a/slsDetectorServers/jungfrauDetectorServer/RegisterDefs.h b/slsDetectorServers/jungfrauDetectorServer/RegisterDefs.h
index 562f065f8..1862e68ca 100644
--- a/slsDetectorServers/jungfrauDetectorServer/RegisterDefs.h
+++ b/slsDetectorServers/jungfrauDetectorServer/RegisterDefs.h
@@ -239,16 +239,16 @@
 #define PLL_PARAM_REG					(0x50 << MEM_MAP_SHIFT)
 
 /* Reconfiguratble PLL Control Regiser */
-#define PLL_CONTROL_REG					(0x51 << MEM_MAP_SHIFT)
+#define PLL_CNTRL_REG					(0x51 << MEM_MAP_SHIFT)
 
-#define PLL_CTRL_RECONFIG_RST_OFST		(0)											//parameter reset
-#define PLL_CTRL_RECONFIG_RST_MSK		(0x00000001 << PLL_CTRL_RECONFIG_RST_OFST)	//parameter reset
-#define PLL_CTRL_WR_PARAMETER_OFST		(2)
-#define PLL_CTRL_WR_PARAMETER_MSK		(0x00000001 << PLL_CTRL_WR_PARAMETER_OFST)
-#define PLL_CTRL_RST_OFST				(3)
-#define PLL_CTRL_RST_MSK				(0x00000001 << PLL_CTRL_RST_OFST)
-#define PLL_CTRL_ADDR_OFST				(16)
-#define PLL_CTRL_ADDR_MSK				(0x0000003F << PLL_CTRL_ADDR_OFST)
+#define PLL_CNTRL_RCNFG_PRMTR_RST_OFST	(0)											//parameter reset
+#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK	(0x00000001 << PLL_CNTRL_RCNFG_PRMTR_RST_OFST)	//parameter reset
+#define PLL_CNTRL_WR_PRMTR_OFST		    (2)
+#define PLL_CNTRL_WR_PRMTR_MSK		    (0x00000001 << PLL_CNTRL_WR_PRMTR_OFST)
+#define PLL_CNTRL_PLL_RST_OFST			(3)
+#define PLL_CNTRL_PLL_RST_MSK			(0x00000001 << PLL_CNTRL_PLL_RST_OFST)
+#define PLL_CNTRL_ADDR_OFST				(16)
+#define PLL_CNTRL_ADDR_MSK				(0x0000003F << PLL_CNTRL_ADDR_OFST)
 
 /* Sample Register (Obsolete) */
 #define SAMPLE_REG 						(0x59 << MEM_MAP_SHIFT)
diff --git a/slsDetectorServers/jungfrauDetectorServer/bin/jungfrauDetectorServer_refactor b/slsDetectorServers/jungfrauDetectorServer/bin/jungfrauDetectorServer_refactor
index bc9469f9d..b5d37dcd8 100755
Binary files a/slsDetectorServers/jungfrauDetectorServer/bin/jungfrauDetectorServer_refactor and b/slsDetectorServers/jungfrauDetectorServer/bin/jungfrauDetectorServer_refactor differ
diff --git a/slsDetectorServers/jungfrauDetectorServer/gitInfo.txt b/slsDetectorServers/jungfrauDetectorServer/gitInfo.txt
index 620a09911..380e64312 100644
--- a/slsDetectorServers/jungfrauDetectorServer/gitInfo.txt
+++ b/slsDetectorServers/jungfrauDetectorServer/gitInfo.txt
@@ -1,9 +1,9 @@
 Path: slsDetectorPackage/slsDetectorServers/jungfrauDetectorServer 
 URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git 
 Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git 
-Repsitory UUID: b5b5ce5c3782a201b449141448ebe99c69515c18 
-Revision: 21 
+Repsitory UUID: de2ebad2ed07a85f70b40490b4e07d46b3ac1ff6 
+Revision: 22 
 Branch: refactor 
 Last Changed Author: Dhanya_Thattil 
-Last Changed Rev: 4214 
-Last Changed Date: 2019-01-10 11:46:27.000000002 +0100 ./RegisterDefs.h
+Last Changed Rev: 4228 
+Last Changed Date: 2019-01-11 11:59:57.000000002 +0100 ./RegisterDefs.h
diff --git a/slsDetectorServers/jungfrauDetectorServer/gitInfoJungfrau.h b/slsDetectorServers/jungfrauDetectorServer/gitInfoJungfrau.h
index a11ead5e1..1bcb6652d 100644
--- a/slsDetectorServers/jungfrauDetectorServer/gitInfoJungfrau.h
+++ b/slsDetectorServers/jungfrauDetectorServer/gitInfoJungfrau.h
@@ -1,6 +1,6 @@
 #define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git"
-#define GITREPUUID "b5b5ce5c3782a201b449141448ebe99c69515c18"
+#define GITREPUUID "de2ebad2ed07a85f70b40490b4e07d46b3ac1ff6"
 #define GITAUTH "Dhanya_Thattil"
-#define GITREV 0x4214
-#define GITDATE 0x20190110
+#define GITREV 0x4228
+#define GITDATE 0x20190111
 #define GITBRANCH "refactor"
diff --git a/slsDetectorServers/jungfrauDetectorServer/slsDetectorFunctionList.c b/slsDetectorServers/jungfrauDetectorServer/slsDetectorFunctionList.c
index bddf781ac..f01d22752 100644
--- a/slsDetectorServers/jungfrauDetectorServer/slsDetectorFunctionList.c
+++ b/slsDetectorServers/jungfrauDetectorServer/slsDetectorFunctionList.c
@@ -3,10 +3,11 @@
 #include "versionAPI.h"
 #include "logger.h"
 
-#ifndef VIRTUAL
 #include "AD9257.h"		// commonServerFunctions.h, blackfin.h, ansi.h
 #include "LTC2620.h"    // dacs
 #include "MAX1932.h"    // hv
+#include "ALTERA_PLL.h" // pll
+#ifndef VIRTUAL
 #include "programfpga.h"
 #else
 #include "blackfin.h"
@@ -392,7 +393,7 @@ void initStopServer() {
 void setupDetector() {
     FILE_LOG(logINFO, ("This Server is for 1 Jungfrau module (500k)\n"));
 
-	resetPLL();
+    ALTERA_PLL_ResetPLL();
 	resetCore();
 	resetPeripheral();
 	cleanFifos();
@@ -413,6 +414,9 @@ void setupDetector() {
     LTC2620_Configure();
 	setDefaultDacs();
 
+    // altera pll
+    ALTERA_PLL_SetDefines(PLL_CNTRL_REG, PLL_PARAM_REG, PLL_CNTRL_RCNFG_PRMTR_RST_MSK, PLL_CNTRL_WR_PRMTR_MSK, PLL_CNTRL_PLL_RST_MSK, PLL_CNTRL_ADDR_MSK, PLL_CNTRL_ADDR_OFST);
+
 	bus_w(DAQ_REG, 0x0);         /* Only once at server startup */
 
 	FILE_LOG(logINFOBLUE, ("Setting Default parameters\n"));
@@ -1223,41 +1227,6 @@ int getPhase() {
 }
 
 
-void resetPLL() {
-#ifdef VIRTUAL
-    return;
-#endif
-    FILE_LOG(logINFO, ("Resetting PLL\n"));
-	// reset PLL Reconfiguration and PLL
-	bus_w(PLL_CONTROL_REG, bus_r(PLL_CONTROL_REG) | PLL_CTRL_RECONFIG_RST_MSK | PLL_CTRL_RST_MSK);
-	usleep(100);
-	bus_w(PLL_CONTROL_REG, bus_r(PLL_CONTROL_REG) & ~PLL_CTRL_RECONFIG_RST_MSK & ~PLL_CTRL_RST_MSK);
-}
-
-
-u_int32_t setPllReconfigReg(u_int32_t reg, u_int32_t val) {
-#ifdef VIRTUAL
-    return val;
-#endif
-    FILE_LOG(logINFO, ("Setting PLL Reconfig Reg\n"));
-	// set parameter
-	bus_w(PLL_PARAM_REG, val);
-
-	// set address
-	bus_w(PLL_CONTROL_REG, (reg << PLL_CTRL_ADDR_OFST) & PLL_CTRL_ADDR_MSK);
-	usleep(10*1000);
-
-	//write parameter
-	bus_w(PLL_CONTROL_REG, bus_r(PLL_CONTROL_REG) | PLL_CTRL_WR_PARAMETER_MSK);
-	bus_w(PLL_CONTROL_REG, bus_r(PLL_CONTROL_REG) & ~PLL_CTRL_WR_PARAMETER_MSK);
-	usleep(10*1000);
-
-	return val;
-}
-
-
-
-
 void configurePll() {
 #ifdef VIRTUAL
     return;
@@ -1280,17 +1249,11 @@ void configurePll() {
 	FILE_LOG(logDEBUG1, ("\tphase out %d (0x%08x)\n", phase, phase));
 
 	if (inv) {
-		val = ((phase << PLL_SHIFT_NUM_SHIFTS_OFST) & PLL_SHIFT_NUM_SHIFTS_MSK) + PLL_SHIFT_CNT_SLCT_C1_VAL + PLL_SHIFT_UP_DOWN_NEG_VAL;
-		FILE_LOG(logDEBUG1, ("\tphase word 0x%08x\n", val));
-		setPllReconfigReg(PLL_PHASE_SHIFT_REG, val);
+	    ALTERA_PLL_SetPhaseShift(phase, 1, 0);
 	} else {
-		val = ((phase << PLL_SHIFT_NUM_SHIFTS_OFST) & PLL_SHIFT_NUM_SHIFTS_MSK) + PLL_SHIFT_CNT_SLCT_C0_VAL + PLL_SHIFT_UP_DOWN_NEG_VAL;
-		FILE_LOG(logDEBUG1, ("\tphase word 0x%08x\n", val));
-		setPllReconfigReg(PLL_PHASE_SHIFT_REG, val);
+        ALTERA_PLL_SetPhaseShift(phase, 0, 0);
 
-		FILE_LOG(logDEBUG1, ("\tphase word 0x%08x\n", val));
-		val = ((phase << PLL_SHIFT_NUM_SHIFTS_OFST) & PLL_SHIFT_NUM_SHIFTS_MSK) + PLL_SHIFT_CNT_SLCT_C2_VAL;
-		setPllReconfigReg(PLL_PHASE_SHIFT_REG, val);
+        ALTERA_PLL_SetPhaseShift(phase, 2, 0);
 	}
 	usleep(10000);
 }
diff --git a/slsDetectorServers/jungfrauDetectorServer/slsDetectorServer_defs.h b/slsDetectorServers/jungfrauDetectorServer/slsDetectorServer_defs.h
index 067239d7f..9d829a0fa 100644
--- a/slsDetectorServers/jungfrauDetectorServer/slsDetectorServer_defs.h
+++ b/slsDetectorServers/jungfrauDetectorServer/slsDetectorServer_defs.h
@@ -92,47 +92,3 @@ enum NETWORKINDEX           { TXN_FRAME };
 #define LSB_OF_64_BIT_REG_OFST		(0)
 #define BIT_32_MSK					(0xFFFFFFFF)
 
-/** PLL Reconfiguration Registers */
-//https://www.altera.com/documentation/mcn1424769382940.html
-#define PLL_MODE_REG 				(0x00)
-#define PLL_STATUS_REG 				(0x01)
-#define PLL_START_REG 				(0x02)
-#define PLL_N_COUNTER_REG 			(0x03)
-#define PLL_M_COUNTER_REG 			(0x04)
-#define PLL_C_COUNTER_REG 			(0x05)
-#define PLL_PHASE_SHIFT_REG			(0x06)
-
-#define PLL_SHIFT_NUM_SHIFTS_OFST	(0)
-#define PLL_SHIFT_NUM_SHIFTS_MSK	(0x0000FFFF << PLL_SHIFT_NUM_SHIFTS_OFST)
-
-#define PLL_SHIFT_CNT_SELECT_OFST	(16)
-#define PLL_SHIFT_CNT_SELECT_MSK	(0x0000001F << PLL_SHIFT_CNT_SELECT_OFST)
-#define PLL_SHIFT_CNT_SLCT_C0_VAL	((0x0 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C1_VAL	((0x1 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C2_VAL	((0x2 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C3_VAL	((0x3 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C4_VAL	((0x4 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C5_VAL	((0x5 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C6_VAL	((0x6 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C7_VAL	((0x7 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C8_VAL	((0x8 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C9_VAL	((0x9 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C10_VAL	((0x10 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C11_VAL	((0x11 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C12_VAL	((0x12 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C13_VAL	((0x13 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C14_VAL	((0x14 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C15_VAL	((0x15 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C16_VAL	((0x16 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C17_VAL	((0x17 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-
-#define PLL_SHIFT_UP_DOWN_OFST		(21)
-#define PLL_SHIFT_UP_DOWN_MSK		(0x00000001 << PLL_SHIFT_UP_DOWN_OFST)
-#define PLL_SHIFT_UP_DOWN_NEG_VAL	((0x0 << PLL_SHIFT_UP_DOWN_OFST) & PLL_SHIFT_UP_DOWN_MSK)
-#define PLL_SHIFT_UP_DOWN_POS_VAL	((0x1 << PLL_SHIFT_UP_DOWN_OFST) & PLL_SHIFT_UP_DOWN_MSK)
-
-#define PLL_K_COUNTER_REG 			(0x07)
-#define PLL_BANDWIDTH_REG 			(0x08)
-#define PLL_CHARGEPUMP_REG 			(0x09)
-#define PLL_VCO_DIV_REG 			(0x1c)
-#define PLL_MIF_REG 				(0x1f)
diff --git a/slsDetectorServers/moenchDetectorServer/ALTERA_PLL.h b/slsDetectorServers/moenchDetectorServer/ALTERA_PLL.h
new file mode 120000
index 000000000..e665f009d
--- /dev/null
+++ b/slsDetectorServers/moenchDetectorServer/ALTERA_PLL.h
@@ -0,0 +1 @@
+../slsDetectorServer/ALTERA_PLL.h
\ No newline at end of file
diff --git a/slsDetectorServers/moenchDetectorServer/slsDetectorFunctionList.c b/slsDetectorServers/moenchDetectorServer/slsDetectorFunctionList.c
index 676a800e4..dd206f9c6 100644
--- a/slsDetectorServers/moenchDetectorServer/slsDetectorFunctionList.c
+++ b/slsDetectorServers/moenchDetectorServer/slsDetectorFunctionList.c
@@ -3,10 +3,11 @@
 #include "versionAPI.h"
 #include "logger.h"
 
-#ifndef VIRTUAL
 #include "AD9257.h"		// commonServerFunctions.h, blackfin.h, ansi.h
 #include "LTC2620.h"    // dacs
 #include "MAX1932.h"    // hv
+#include "ALTERA_PLL.h" // pll
+#ifndef VIRTUAL
 #include "programfpga.h"
 #else
 #include "blackfin.h"
@@ -471,7 +472,7 @@ void setupDetector() {
     now_ptr = 0;
 
 
-	resetPLL();
+    ALTERA_PLL_ResetPLLAndReconfiguration();
 	resetCore();
 	resetPeripheral();
 	cleanFifos();
@@ -500,6 +501,8 @@ void setupDetector() {
 	    }
 	}
 
+    // altera pll
+    ALTERA_PLL_SetDefines(PLL_CNTRL_REG, PLL_PARAM_REG, PLL_CNTRL_RCNFG_PRMTR_RST_MSK, PLL_CNTRL_WR_PRMTR_MSK, PLL_CNTRL_PLL_RST_MSK, PLL_CNTRL_ADDR_MSK, PLL_CNTRL_ADDR_OFST);
 
     bus_w(ADC_PORT_INVERT_REG, ADC_PORT_INVERT_VAL);//FIXME:  got from moench config file
 
@@ -1288,34 +1291,6 @@ int sendUDP(int enable) {
     return ((bus_r(addr) & CONFIG_GB10_SND_UDP_MSK) >> CONFIG_GB10_SND_UDP_OFST);
 }
 
-void resetPLL() {
-#ifdef VIRTUAL
-    return;
-#endif
-    FILE_LOG(logINFO, ("Resetting PLL\n"));
-	// reset PLL Reconfiguration and PLL
-	bus_w(PLL_CNTRL_REG, bus_r(PLL_CNTRL_REG) | PLL_CNTRL_RCNFG_PRMTR_RST_MSK | PLL_CNTRL_PLL_RST_MSK);
-	usleep(WAIT_TIME_US_PLL);
-	bus_w(PLL_CNTRL_REG, bus_r(PLL_CNTRL_REG) & ~PLL_CNTRL_RCNFG_PRMTR_RST_MSK & ~PLL_CNTRL_PLL_RST_MSK);
-}
-
-void setPllReconfigReg(uint32_t reg, uint32_t val) {
-#ifdef VIRTUAL
-    return val;
-#endif
-    FILE_LOG(logINFO, ("Setting PLL Reconfig Reg\n"));
-	// set parameter
-	bus_w(PLL_PARAM_REG, val);
-
-	// set address
-	bus_w(PLL_CNTRL_REG, (reg << PLL_CNTRL_ADDR_OFST) & PLL_CNTRL_ADDR_MSK);
-	usleep(WAIT_TIME_US_PLL);
-
-	//write parameter
-	bus_w(PLL_CNTRL_REG, bus_r(PLL_CNTRL_REG) | PLL_CNTRL_WR_PRMTR_MSK);
-	bus_w(PLL_CNTRL_REG, bus_r(PLL_CNTRL_REG) & ~PLL_CNTRL_WR_PRMTR_MSK);
-	usleep(WAIT_TIME_US_PLL);
-}
 
 // ind can only be ADC_CLK or DBIT_CLK
 void configurePhase(CLKINDEX ind, int val) {
@@ -1327,12 +1302,10 @@ void configurePhase(CLKINDEX ind, int val) {
     FILE_LOG(logINFO, ("Configuring Phase of C%d to %d\n", ind, val));
 
     // reset only pll
-    bus_w(PLL_CNTRL_REG, bus_r(PLL_CNTRL_REG) | PLL_CNTRL_PLL_RST_MSK);
-    usleep(WAIT_TIME_US_PLL);
-    bus_w(PLL_CNTRL_REG, bus_r(PLL_CNTRL_REG) & ~PLL_CNTRL_PLL_RST_MSK);
+    ALTERA_PLL_ResetPLL();
 
     // set mode register to polling mode
-    setPllReconfigReg(PLL_MODE_REG, PLL_MODE_PLLNG_MD_VAL);
+    ALTERA_PLL_SetModePolling();
 
     int phase = 0, inv = 0;
     if (val > 0) {
@@ -1345,13 +1318,7 @@ void configurePhase(CLKINDEX ind, int val) {
     }
     FILE_LOG(logINFO, ("\tphase out %d (0x%08x), inv:%d\n", phase, phase, inv));
 
-    uint32_t value = (((phase << PLL_SHIFT_NUM_SHIFTS_OFST) & PLL_SHIFT_NUM_SHIFTS_MSK) |
-             (((int)ind << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK));
-    FILE_LOG(logDEBUG1, ("\tC%d phase word:0x%08x\n", ind, value));
-
-    // write phase shift
-    setPllReconfigReg(PLL_PHASE_SHIFT_REG, value);
-    usleep(WAIT_TIME_US_PLL);
+    ALTERA_PLL_SetPhaseShift(phase, (int)ind, 0);
 
     clkPhase[ind] = val;
 }
@@ -1372,35 +1339,8 @@ void configureFrequency(CLKINDEX ind, int val) {
         return getPhase(ind);
     }
 
-    // calculate output frequency
-    uint32_t total_div =  PLL_VCO_FREQ_MHZ / val;
-
-    // assume 50% duty cycle
-    uint32_t low_count = total_div / 2;
-    uint32_t high_count = low_count;
-    uint32_t odd_division = 0;
-
-    // odd division
-    if (total_div > (2 * low_count)) {
-        ++high_count;
-        odd_division = 1;
-    }
-    FILE_LOG(logINFO, ("\tC%d: Low:%d, High:%d, Odd:%d\n", ind, low_count, high_count, odd_division));
-
-    uint32_t val = (((low_count << PLL_C_COUNTER_LW_CNT_OFST) & PLL_C_COUNTER_LW_CNT_MSK) |
-            ((high_count << PLL_C_COUNTER_HGH_CNT_OFST) & PLL_C_COUNTER_HGH_CNT_MSK) |
-        ((odd_division << PLL_C_COUNTER_ODD_DVSN_OFST) & PLL_C_COUNTER_ODD_DVSN_MSK) |
-        (((int)ind << PLL_C_COUNTER_SLCT_OFST) & PLL_C_COUNTER_SLCT_MSK));
-    FILE_LOG(logDEBUG1, ("\tC%d word:0x%08x\n", ind, val));
-
-    // write frequency (post-scale output counter C)
-    setPllReconfigReg(PLL_C_COUNTER_REG, val);
-    usleep(WAIT_TIME_US_PLL);
-
-    // reset only PLL
-    bus_w(PLL_CNTRL_REG, bus_r(PLL_CNTRL_REG) | PLL_CNTRL_PLL_RST_MSK);
-    usleep(WAIT_TIME_US_PLL);
-    bus_w(PLL_CNTRL_REG, bus_r(PLL_CNTRL_REG) & ~PLL_CNTRL_PLL_RST_MSK);
+    // Calculate and set output frequency
+    ALTERA_PLL_SetOuputFrequency (ind, PLL_VCO_FREQ_MHZ, val);
 
     clkDivider[ind] = PLL_VCO_FREQ_MHZ / (low_count + high_count);
     FILE_LOG(logINFO, ("\tC%d: Frequency set to %d MHz\n", ind, clkDivider[ind]));
diff --git a/slsDetectorServers/moenchDetectorServer/slsDetectorServer_defs.h b/slsDetectorServers/moenchDetectorServer/slsDetectorServer_defs.h
index a7cd843d2..6b19324cd 100644
--- a/slsDetectorServers/moenchDetectorServer/slsDetectorServer_defs.h
+++ b/slsDetectorServers/moenchDetectorServer/slsDetectorServer_defs.h
@@ -74,67 +74,3 @@ enum DACINDEX               {D0, D1, D2, D3, D4, D5, D6, D7, D8, D9,
 #define MAXIMUM_ADC_CLK             (40)
 #define PLL_VCO_FREQ_MHZ            (400)
 
-/** PLL Reconfiguration Registers */
-//https://www.altera.com/documentation/mcn1424769382940.html
-#define PLL_MODE_REG 				    (0x00)
-
-#define PLL_MODE_WT_RQUST_VAL           (0)
-#define PLL_MODE_PLLNG_MD_VAL           (1)
-
-#define PLL_STATUS_REG 				    (0x01)
-#define PLL_START_REG 				    (0x02)
-#define PLL_N_COUNTER_REG 			    (0x03)
-#define PLL_M_COUNTER_REG 			    (0x04)
-#define PLL_C_COUNTER_REG 			    (0x05)
-
-#define PLL_C_COUNTER_LW_CNT_OFST       (0)
-#define PLL_C_COUNTER_LW_CNT_MSK        (0x000000FF << PLL_C_COUNTER_LW_CNT_OFST)
-#define PLL_C_COUNTER_HGH_CNT_OFST      (8)
-#define PLL_C_COUNTER_HGH_CNT_MSK       (0x000000FF << PLL_C_COUNTER_HGH_CNT_OFST)
-/* total_div = lw_cnt + hgh_cnt */
-#define PLL_C_COUNTER_BYPSS_ENBL_OFST   (16)
-#define PLL_C_COUNTER_BYPSS_ENBL_MSK    (0x00000001 << PLL_C_COUNTER_BYPSS_ENBL_OFST)
-/* if bypss_enbl = 0, fout = f(vco)/total_div; else fout = f(vco) (c counter is bypassed) */
-#define PLL_C_COUNTER_ODD_DVSN_OFST     (17)
-#define PLL_C_COUNTER_ODD_DVSN_MSK      (0x00000001 << PLL_C_COUNTER_ODD_DVSN_OFST)
-/** if odd_dvsn = 0 (even), duty cycle = hgh_cnt/ total_div; else duty cycle = (hgh_cnt - 0.5) / total_div */
-#define PLL_C_COUNTER_SLCT_OFST         (18)
-#define PLL_C_COUNTER_SLCT_MSK          (0x0000001F << PLL_C_COUNTER_SLCT_OFST)
-
-#define PLL_PHASE_SHIFT_REG			    (0x06)
-
-#define PLL_SHIFT_NUM_SHIFTS_OFST	    (0)
-#define PLL_SHIFT_NUM_SHIFTS_MSK	    (0x0000FFFF << PLL_SHIFT_NUM_SHIFTS_OFST)
-
-#define PLL_SHIFT_CNT_SELECT_OFST	    (16)
-#define PLL_SHIFT_CNT_SELECT_MSK	    (0x0000001F << PLL_SHIFT_CNT_SELECT_OFST)
-#define PLL_SHIFT_CNT_SLCT_C0_VAL	    ((0x0 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C1_VAL	    ((0x1 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C2_VAL	    ((0x2 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C3_VAL	    ((0x3 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C4_VAL	    ((0x4 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C5_VAL	    ((0x5 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C6_VAL	    ((0x6 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C7_VAL	    ((0x7 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C8_VAL	    ((0x8 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C9_VAL	    ((0x9 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C10_VAL	    ((0x10 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C11_VAL	    ((0x11 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C12_VAL	    ((0x12 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C13_VAL	    ((0x13 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C14_VAL	    ((0x14 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C15_VAL	    ((0x15 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C16_VAL	    ((0x16 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-#define PLL_SHIFT_CNT_SLCT_C17_VAL	    ((0x17 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
-
-#define PLL_SHIFT_UP_DOWN_OFST		    (21)
-#define PLL_SHIFT_UP_DOWN_MSK		    (0x00000001 << PLL_SHIFT_UP_DOWN_OFST)
-#define PLL_SHIFT_UP_DOWN_NEG_VAL	    ((0x0 << PLL_SHIFT_UP_DOWN_OFST) & PLL_SHIFT_UP_DOWN_MSK)
-#define PLL_SHIFT_UP_DOWN_POS_VAL	    ((0x1 << PLL_SHIFT_UP_DOWN_OFST) & PLL_SHIFT_UP_DOWN_MSK)
-
-#define PLL_K_COUNTER_REG 			    (0x07)
-#define PLL_BANDWIDTH_REG 			    (0x08)
-#define PLL_CHARGEPUMP_REG 			    (0x09)
-#define PLL_VCO_DIV_REG 			    (0x1c)
-#define PLL_MIF_REG 				    (0x1f)
-
diff --git a/slsDetectorServers/slsDetectorServer/ALTERA_PLL.h b/slsDetectorServers/slsDetectorServer/ALTERA_PLL.h
new file mode 100755
index 000000000..20ec6d3ec
--- /dev/null
+++ b/slsDetectorServers/slsDetectorServer/ALTERA_PLL.h
@@ -0,0 +1,218 @@
+#pragma once
+
+#include <unistd.h>     // usleep
+
+/* Altera PLL DEFINES */
+
+/** PLL Reconfiguration Registers */
+//https://www.altera.com/documentation/mcn1424769382940.html
+#define ALTERA_PLL_MODE_REG                     (0x00)
+
+#define ALTERA_PLL_MODE_WT_RQUST_VAL            (0)
+#define ALTERA_PLL_MODE_PLLNG_MD_VAL            (1)
+
+#define ALTERA_PLL_STATUS_REG                   (0x01)
+#define ALTERA_PLL_START_REG                    (0x02)
+#define ALTERA_PLL_N_COUNTER_REG                (0x03)
+#define ALTERA_PLL_M_COUNTER_REG                (0x04)
+#define ALTERA_PLL_C_COUNTER_REG                (0x05)
+
+#define ALTERA_PLL_C_COUNTER_LW_CNT_OFST        (0)
+#define ALTERA_PLL_C_COUNTER_LW_CNT_MSK         (0x000000FF << ALTERA_PLL_C_COUNTER_LW_CNT_OFST)
+#define ALTERA_PLL_C_COUNTER_HGH_CNT_OFST       (8)
+#define ALTERA_PLL_C_COUNTER_HGH_CNT_MSK        (0x000000FF << ALTERA_PLL_C_COUNTER_HGH_CNT_OFST)
+/* total_div = lw_cnt + hgh_cnt */
+#define ALTERA_PLL_C_COUNTER_BYPSS_ENBL_OFST    (16)
+#define ALTERA_PLL_C_COUNTER_BYPSS_ENBL_MSK     (0x00000001 << ALTERA_PLL_C_COUNTER_BYPSS_ENBL_OFST)
+/* if bypss_enbl = 0, fout = f(vco)/total_div; else fout = f(vco) (c counter is bypassed) */
+#define ALTERA_PLL_C_COUNTER_ODD_DVSN_OFST      (17)
+#define ALTERA_PLL_C_COUNTER_ODD_DVSN_MSK       (0x00000001 << ALTERA_PLL_C_COUNTER_ODD_DVSN_OFST)
+/** if odd_dvsn = 0 (even), duty cycle = hgh_cnt/ total_div; else duty cycle = (hgh_cnt - 0.5) / total_div */
+#define ALTERA_PLL_C_COUNTER_SLCT_OFST          (18)
+#define ALTERA_PLL_C_COUNTER_SLCT_MSK           (0x0000001F << ALTERA_PLL_C_COUNTER_SLCT_OFST)
+
+#define ALTERA_PLL_PHASE_SHIFT_REG              (0x06)
+
+#define ALTERA_PLL_SHIFT_NUM_SHIFTS_OFST        (0)
+#define ALTERA_PLL_SHIFT_NUM_SHIFTS_MSK         (0x0000FFFF << ALTERA_PLL_SHIFT_NUM_SHIFTS_OFST)
+
+#define ALTERA_PLL_SHIFT_CNT_SELECT_OFST        (16)
+#define ALTERA_PLL_SHIFT_CNT_SELECT_MSK         (0x0000001F << ALTERA_PLL_SHIFT_CNT_SELECT_OFST)
+#define ALTERA_PLL_SHIFT_CNT_SLCT_C0_VAL        ((0x0 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
+#define ALTERA_PLL_SHIFT_CNT_SLCT_C1_VAL        ((0x1 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
+#define ALTERA_PLL_SHIFT_CNT_SLCT_C2_VAL        ((0x2 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
+#define ALTERA_PLL_SHIFT_CNT_SLCT_C3_VAL        ((0x3 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
+#define ALTERA_PLL_SHIFT_CNT_SLCT_C4_VAL        ((0x4 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
+#define ALTERA_PLL_SHIFT_CNT_SLCT_C5_VAL        ((0x5 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
+#define ALTERA_PLL_SHIFT_CNT_SLCT_C6_VAL        ((0x6 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
+#define ALTERA_PLL_SHIFT_CNT_SLCT_C7_VAL        ((0x7 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
+#define ALTERA_PLL_SHIFT_CNT_SLCT_C8_VAL        ((0x8 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
+#define ALTERA_PLL_SHIFT_CNT_SLCT_C9_VAL        ((0x9 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
+#define ALTERA_PLL_SHIFT_CNT_SLCT_C10_VAL       ((0x10 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
+#define ALTERA_PLL_SHIFT_CNT_SLCT_C11_VAL       ((0x11 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
+#define ALTERA_PLL_SHIFT_CNT_SLCT_C12_VAL       ((0x12 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
+#define ALTERA_PLL_SHIFT_CNT_SLCT_C13_VAL       ((0x13 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
+#define ALTERA_PLL_SHIFT_CNT_SLCT_C14_VAL       ((0x14 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
+#define ALTERA_PLL_SHIFT_CNT_SLCT_C15_VAL       ((0x15 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
+#define ALTERA_PLL_SHIFT_CNT_SLCT_C16_VAL       ((0x16 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
+#define ALTERA_PLL_SHIFT_CNT_SLCT_C17_VAL       ((0x17 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
+
+#define ALTERA_PLL_SHIFT_UP_DOWN_OFST           (21)
+#define ALTERA_PLL_SHIFT_UP_DOWN_MSK            (0x00000001 << ALTERA_PLL_SHIFT_UP_DOWN_OFST)
+#define ALTERA_PLL_SHIFT_UP_DOWN_NEG_VAL        ((0x0 << ALTERA_PLL_SHIFT_UP_DOWN_OFST) & ALTERA_PLL_SHIFT_UP_DOWN_MSK)
+#define ALTERA_PLL_SHIFT_UP_DOWN_POS_VAL        ((0x1 << ALTERA_PLL_SHIFT_UP_DOWN_OFST) & ALTERA_PLL_SHIFT_UP_DOWN_MSK)
+
+#define ALTERA_PLL_K_COUNTER_REG                (0x07)
+#define ALTERA_PLL_BANDWIDTH_REG                (0x08)
+#define ALTERA_PLL_CHARGEPUMP_REG               (0x09)
+#define ALTERA_PLL_VCO_DIV_REG                  (0x1c)
+#define ALTERA_PLL_MIF_REG                      (0x1f)
+
+
+#define ALTERA_PLL_WAIT_TIME_US                 (10 * 1000)
+
+
+uint32_t ALTERA_PLL_Cntrl_Reg = 0x0;
+uint32_t ALTERA_PLL_Param_Reg = 0x0;
+uint32_t ALTERA_PLL_Cntrl_RcnfgPrmtrRstMask = 0x0;
+uint32_t ALTERA_PLL_Cntrl_WrPrmtrMask = 0x0;
+uint32_t ALTERA_PLL_Cntrl_PLLRstMask = 0x0;
+uint32_t ALTERA_PLL_Cntrl_AddrMask = 0x0;
+int ALTERA_PLL_Cntrl_AddrOfst = 0;
+
+
+/**
+ * Set Defines
+ * @param creg control register
+ * @param preg parameter register
+ * @param rprmsk reconfig parameter reset mask
+ * @param wpmsk write parameter mask
+ * @param prmsk pll reset mask
+ * @param amsk address mask
+ * @param aofst address offset
+ */
+void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk, uint32_t wpmsk, uint32_t prmsk, uint32_t amsk, int aofst) {
+    ALTERA_PLL_Cntrl_Reg = creg;
+    ALTERA_PLL_Param_Reg = preg;
+    ALTERA_PLL_Cntrl_RcnfgPrmtrRstMask = rprmsk;
+    ALTERA_PLL_Cntrl_WrPrmtrMask = wpmsk;
+    ALTERA_PLL_Cntrl_PLLRstMask = prmsk;
+    ALTERA_PLL_Cntrl_AddrMask = amsk;
+    ALTERA_PLL_Cntrl_AddrOfst = aofst;
+}
+
+/**
+ * Reset only PLL
+ */
+void ALTERA_PLL_ResetPLL () {
+    FILE_LOG(logINFO, ("Resetting only PLL\n"));
+
+    bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) | ALTERA_PLL_Cntrl_PLLRstMask);
+    usleep(ALTERA_PLL_WAIT_TIME_US);
+    bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) & ~ALTERA_PLL_Cntrl_PLLRstMask);
+
+}
+
+/**
+ * Reset PLL Reconfiguration and PLL
+ */
+void ALTERA_PLL_ResetPLLAndReconfiguration () {
+    FILE_LOG(logINFO, ("Resetting PLL and Reconfiguration\n"));
+
+    bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) | ALTERA_PLL_Cntrl_RcnfgPrmtrRstMask | ALTERA_PLL_Cntrl_PLLRstMask);
+    usleep(ALTERA_PLL_WAIT_TIME_US);
+    bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) & ~ALTERA_PLL_Cntrl_RcnfgPrmtrRstMask & ~ALTERA_PLL_Cntrl_PLLRstMask);
+}
+
+
+/**
+ * Set PLL Reconfig register
+ * @param reg register
+ * @param val value
+ */
+void ALTERA_PLL_SetPllReconfigReg(uint32_t reg, uint32_t val) {
+    FILE_LOG(logINFO, ("Setting PLL Reconfig Reg\n"));
+
+    // set parameter
+    bus_w(ALTERA_PLL_Param_Reg, val);
+
+    // set address
+    bus_w(ALTERA_PLL_Cntrl_Reg, (reg << ALTERA_PLL_Cntrl_AddrOfst) & ALTERA_PLL_Cntrl_AddrMask);
+    usleep(ALTERA_PLL_WAIT_TIME_US);
+
+    //write parameter
+    bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) | ALTERA_PLL_Cntrl_WrPrmtrMask);
+    bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) & ~ALTERA_PLL_Cntrl_WrPrmtrMask);
+    usleep(ALTERA_PLL_WAIT_TIME_US);
+}
+
+/**
+ * Write Phase Shift
+ * @param phase phase shift
+ * @param clkIndex clock index
+ * @param pos 1 if up down direction of shift is positive, else 0
+ */
+void ALTERA_PLL_SetPhaseShift(int32_t phase, int clkIndex, int pos) {
+    FILE_LOG(logINFO, ("\tWriting PLL Phase Shift\n"));
+    uint32_t value = (((phase << ALTERA_PLL_SHIFT_NUM_SHIFTS_OFST) & ALTERA_PLL_SHIFT_NUM_SHIFTS_MSK) |
+             ((clkIndex << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK) |
+             (pos ? ALTERA_PLL_SHIFT_UP_DOWN_POS_VAL : ALTERA_PLL_SHIFT_UP_DOWN_NEG_VAL));
+
+    FILE_LOG(logDEBUG1, ("\tC%d phase word:0x%08x\n", clkIndex, value));
+
+    // write phase shift
+    ALTERA_PLL_SetPllReconfigReg(ALTERA_PLL_PHASE_SHIFT_REG, value);
+    usleep(ALTERA_PLL_WAIT_TIME_US);
+}
+
+/**
+ * Set PLL mode register to polling mode
+ */
+void ALTERA_PLL_SetModePolling() {
+    FILE_LOG(logINFO, ("\tSetting Polling Mode\n"));
+    ALTERA_PLL_SetPllReconfigReg(ALTERA_PLL_MODE_REG, ALTERA_PLL_MODE_PLLNG_MD_VAL);
+    usleep(ALTERA_PLL_WAIT_TIME_US);
+}
+
+/**
+ * Calculate and write output frequency
+ * @param clkIndex clock index
+ * @param pllVCOFreqMhz PLL VCO Frequency in Mhz
+ * @param value frequency to set to
+ */
+void ALTERA_PLL_SetOuputFrequency (int clkIndex, int pllVCOFreqMhz, int value) {
+    FILE_LOG(logINFO, ("\tC%d: Setting output frequency\n"));
+
+    // calculate output frequency
+    uint32_t total_div =  pllVCOFreqMhz / value;
+
+    // assume 50% duty cycle
+    uint32_t low_count = total_div / 2;
+    uint32_t high_count = low_count;
+    uint32_t odd_division = 0;
+
+    // odd division
+    if (total_div > (2 * low_count)) {
+        ++high_count;
+        odd_division = 1;
+    }
+    FILE_LOG(logINFO, ("\tC%d: Low:%d, High:%d, Odd:%d\n", clkIndex, low_count, high_count, odd_division));
+
+    // command to set output frequency
+    uint32_t val = (((low_count << ALTERA_PLL_C_COUNTER_LW_CNT_OFST) & ALTERA_PLL_C_COUNTER_LW_CNT_MSK) |
+            ((high_count << ALTERA_PLL_C_COUNTER_HGH_CNT_OFST) & ALTERA_PLL_C_COUNTER_HGH_CNT_MSK) |
+            ((odd_division << ALTERA_PLL_C_COUNTER_ODD_DVSN_OFST) & ALTERA_PLL_C_COUNTER_ODD_DVSN_MSK) |
+            ((clkIndex << ALTERA_PLL_C_COUNTER_SLCT_OFST) & ALTERA_PLL_C_COUNTER_SLCT_MSK));
+    FILE_LOG(logDEBUG1, ("\tC%d word:0x%08x\n", clkIndex, val));
+
+    // write frequency (post-scale output counter C)
+    ALTERA_PLL_SetPllReconfigReg(ALTERA_PLL_C_COUNTER_REG, val);
+    usleep(ALTERA_PLL_WAIT_TIME_US);
+
+    // reset only PLL
+    bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) | ALTERA_PLL_Cntrl_PLLRstMask);
+    usleep(ALTERA_PLL_WAIT_TIME_US);
+    bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) & ~ALTERA_PLL_Cntrl_PLLRstMask);
+}
+
+
diff --git a/slsSupportLib/include/versionAPI.h b/slsSupportLib/include/versionAPI.h
index d46621ea6..db4a4581f 100644
--- a/slsSupportLib/include/versionAPI.h
+++ b/slsSupportLib/include/versionAPI.h
@@ -1,7 +1,7 @@
 /** API versions */
 #define APIRECEIVER 0x180927
 #define APIEIGER 0x181031
-#define APIJUNGFRAU 0x181102
+#define APIJUNGFRAU 0x190111
 #define APIGOTTHARD 0x190108
 #define APICTB 0x180101
 #define APIMOENCH 0x181108