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updated mythen3 to configure phase, freq, delay left, period left, actual time, measurement time, framesfrom start and othe register mappings

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maliakal_d
2019-11-06 18:58:22 +01:00
parent 0f9fd5cd73
commit 1797d39216
16 changed files with 493 additions and 147 deletions
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60
slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h
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@@ -23,42 +23,46 @@
#define DEFAULT_PERIOD (2*1000*1000) //ns
#define DEFAULT_DELAY_AFTER_TRIGGER (0)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_RUN_CLK (125)
#define DEFAULT_TICK_CLK (20) // will be fixed later. Not configurable
#define DEFAULT_SAMPLING_CLK (80)
#define DEFAULT_READOUT_C0 (125000000) // rdo_clk, 125 MHz
#define DEFAULT_READOUT_C1 (250000000) // rdo_x2_clk, 250 MHz
#define DEFAULT_SYSTEM_C0 (125000000) // run_clk, 125 MHz
#define DEFAULT_SYSTEM_C1 (80000000) // chip_clk, 80 MHz
#define DEFAULT_SYSTEM_C2 (20000000) // sync_clk, 20 MHz
#define DEFAULT_SYSTEM_C3 (125000000) // str_clk, 125 MHz
/* Firmware Definitions */
#define IP_HEADER_SIZE (20)
#define READOUT_PLL_VCO_FREQ_HZ (750000000) // 750MHz
#define SYSTEM_PLL_VCO_FREQ_HZ (750000000) // 750MHz
#define MAX_PATTERN_LENGTH (0x2000) // maximum number of words (64bit)
#define WAIT_TIME_US_STP_ACQ (100)
/** Other Definitions */
#define BIT16_MASK (0xFFFF)
#define DAC_NAMES "vcassh", "vth2", "vshaper", "vshaperneg", "vipre_out", "vth3", "vth1", "vicin", "vcas", "vpreamp", "vph", "vipre", "viinsh", "vpl", "vtrim", "vdcsh"
/* Enums */
enum CLKINDEX {RUN_CLK, TICK_CLK, SAMPLING_CLK, NUM_CLOCKS};
enum DACINDEX {M_CASSH, M_VTH2, M_VRFSH, M_VRFSHNPOL, M_VIPRE_OUT, M_VTH3, M_VTH1, M_VICIN, M_CAS, M_VRF, M_VPH, M_VIPRE, M_VIINSH, M_VPL, M_VTRIM, M_VDCSH};
#define DEFAULT_DAC_VALS {1200, /* casSh */ \
2800, /* Vth2 */ \
1280, /* VrfSh */ \
2800, /* VrfShNpol */ \
1220, /* vIpreOut */ \
2800, /* Vth3 */ \
2800, /* Vth1 */ \
1708, /* vIcin */ \
1800, /* cas */ \
1100, /* Vrf */ \
1712, /* VPH */ \
2624, /* vIpre */ \
1708, /* vIinSh */ \
1100, /* VPL */ \
2800, /* vTrim */ \
800 /* VdcSh */ \
};
/* Defines in the Firmware */
#define MAX_PATTERN_LENGTH (0x2000) // maximum number of words (64bit)
#define WAIT_TIME_US_STP_ACQ (100)
enum DACINDEX {M_CASSH, M_VTH2, M_VRFSH, M_VRFSHNPOL, M_VIPRE_OUT, M_VTH3, M_VTH1, M_VICIN, M_CAS, M_VRF, M_VPH, M_VIPRE, M_VIINSH, M_VPL, M_VTRIM, M_VDCSH};
#define DAC_NAMES "vcassh", "vth2", "vshaper", "vshaperneg", "vipre_out", "vth3", "vth1", "vicin", "vcas", "vpreamp", "vph", "vipre", "viinsh", "vpl", "vtrim", "vdcsh"
#define DEFAULT_DAC_VALS {1200, /* casSh */ \
2800, /* Vth2 */ \
1280, /* VrfSh */ \
2800, /* VrfShNpol */ \
1220, /* vIpreOut */ \
2800, /* Vth3 */ \
2800, /* Vth1 */ \
1708, /* vIcin */ \
1800, /* cas */ \
1100, /* Vrf */ \
1712, /* VPH */ \
2624, /* vIpre */ \
1708, /* vIinSh */ \
1100, /* VPL */ \
2800, /* vTrim */ \
800 /* VdcSh */ \
};
enum CLKINDEX {READOUT_C0, READOUT_C1, SYSTEM_C0, SYSTEM_C1, SYSTEM_C2, SYSTEM_C3, NUM_CLOCKS};
#define CLK_NAMES "READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2", "SYSTEM_C3"
enum PLLINDEX {READOUT_PLL, SYSTEM_PLL};
/* Struct Definitions */
typedef struct udp_header_struct {