diff --git a/slsDetectorServers/gotthard2DetectorServer/RegisterDefs.h b/slsDetectorServers/gotthard2DetectorServer/RegisterDefs.h index f22731f77..5314c6a87 100644 --- a/slsDetectorServers/gotthard2DetectorServer/RegisterDefs.h +++ b/slsDetectorServers/gotthard2DetectorServer/RegisterDefs.h @@ -1,43 +1,62 @@ #pragma once -/* Definitions for FPGA*/ + #define REG_OFFSET (4) -/* cspbase 0x1804 0000 */ -#define BASE_READOUT_PLL (0x000) -#define BASE_SYSTEM_PLL (0x800) + +/* Base addresses 0x1804 0000 ---------------------------------------------*/ +/* Reconfiguration core for readout pll */ +#define BASE_READOUT_PLL (0x0000) // 0x1804_0000 - 0x1804_07FF +/* Reconfiguration core for system pll */ +#define BASE_SYSTEM_PLL (0x0800) // 0x1804_0800 - 0x1804_0FFF + +/* Base addresses 0x1806 0000 ---------------------------------------------*/ +/* General purpose control and status registers */ +#define BASE_CONTROL (0x0000) +/* Acquisition? TODO */ +#define BASE_ACQUISITION (0x0200) +/* UDP datagram generator */ +#define BASE_UDP_RAM (0x01000) // 0x1806_1000 - 0x1806_1FFF + + + + +/* Readout PLL registers --------------------------------------------------*/ #define READOUT_PLL_RESET_REG (0x1 * REG_OFFSET + BASE_READOUT_PLL) //TODO #define READOUT_PLL_RESET_OFST (0) #define READOUT_PLL_RESET_MSK (0x00000001 << READOUT_PLL_RESET_OFST) -#define SYSTEM_PLL_RESET_REG (0x1 * REG_OFFSET + BASE_SYSTEM_PLL) //TODO - -#define SYSTEM_PLL_RESET_OFST (0) -#define SYSTEM_PLL_RESET_MSK (0x00000001 << SYSTEM_PLL_RESET_OFST) - #define READOUT_PLL_WAIT_REG (0x2 * REG_OFFSET + BASE_READOUT_PLL) //TODO #define READOUT_PLL_WAIT_OFST (0) #define READOUT_PLL_WAIT_MSK (0x00000001 << READOUT_PLL_WAIT_OFST) + +/* System PLL registers --------------------------------------------------*/ + +#define SYSTEM_PLL_RESET_REG (0x1 * REG_OFFSET + BASE_SYSTEM_PLL) //TODO + +#define SYSTEM_PLL_RESET_OFST (0) +#define SYSTEM_PLL_RESET_MSK (0x00000001 << SYSTEM_PLL_RESET_OFST) + #define SYSTEM_PLL_WAIT_REG (0x2 * REG_OFFSET + BASE_SYSTEM_PLL) //TODO #define SYSTEM_PLL_WAIT_OFST (0) #define SYSTEM_PLL_WAIT_MSK (0x00000001 << SYSTEM_PLL_WAIT_OFST) -/* cspbase 0x1806 0000 */ -#define BASE_CONTROL (0x000) -#define BASE_ACQUISITION (0x200) //???TODO -#define BASE_UDP_RAM (0x1000) +/* Control registers --------------------------------------------------*/ /* Module Control Board Serial Number register */ -#define MCB_SERIAL_NO_REG (0x000 * REG_OFFSET + BASE_CONTROL) +#define MCB_SERIAL_NO_REG (0x00 * REG_OFFSET + BASE_CONTROL) + +#define MCB_SERIAL_NO_VRSN_OFST (16) +#define MCB_SERIAL_NO_VRSN_MSK (0x0000001F << MCB_SERIAL_NO_VRSN_OFST) /* FPGA Version register */ -#define FPGA_VERSION_REG (0x001 * REG_OFFSET + BASE_CONTROL) +#define FPGA_VERSION_REG (0x01 * REG_OFFSET + BASE_CONTROL) #define FPGA_COMPILATION_DATE_OFST (0) #define FPGA_COMPILATION_DATE_MSK (0x00FFFFFF << FPGA_COMPILATION_DATE_OFST) @@ -45,7 +64,7 @@ #define DETECTOR_TYPE_MSK (0x000000FF << DETECTOR_TYPE_OFST) /* API Version register */ -#define API_VERSION_REG (0x002 * REG_OFFSET + BASE_CONTROL) +#define API_VERSION_REG (0x02 * REG_OFFSET + BASE_CONTROL) #define API_VERSION_OFST (0) #define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST) @@ -53,11 +72,11 @@ #define API_VERSION_DETECTOR_TYPE_MSK (0x000000FF << API_VERSION_DETECTOR_TYPE_OFST) //Not used in software /* Fix pattern register */ -#define FIX_PATT_REG (0x003 * REG_OFFSET + BASE_CONTROL) +#define FIX_PATT_REG (0x03 * REG_OFFSET + BASE_CONTROL) #define FIX_PATT_VAL (0xACDC2019) /* Status register */ -#define STATUS_REG (0x004 * REG_OFFSET + BASE_CONTROL) +#define STATUS_REG (0x04 * REG_OFFSET + BASE_CONTROL) #ifdef VIRTUAL #define RUN_BUSY_OFST (0) @@ -65,16 +84,40 @@ #endif /* Look at me read only register */ -#define LOOK_AT_ME_REG (0x005 * REG_OFFSET + BASE_CONTROL) +#define LOOK_AT_ME_REG (0x05 * REG_OFFSET + BASE_CONTROL) + +/* System status register */ +#define SYSTEM_STATUS_REG (0x06 * REG_OFFSET + BASE_CONTROL) + +/* Config RW regiseter */ +#define CONFIG_REG (0x20 * REG_OFFSET + BASE_CONTROL) + +/* Control RW register */ +#define CONTROL_REG (0x21 * REG_OFFSET + BASE_CONTROL) + +#define CONTROL_STRT_ACQSTN_OFST (0) +#define CONTROL_STRT_ACQSTN_MSK (0x00000001 << CONTROL_STRT_ACQSTN_OFST) +#define CONTROL_STP_ACQSTN_OFST (1) +#define CONTROL_STP_ACQSTN_MSK (0x00000001 << CONTROL_STP_ACQSTN_OFST) +#define CONTROL_CRE_RST_OFST (10) +#define CONTROL_CRE_RST_MSK (0x00000001 << CONTROL_CRE_RST_OFST) +#define CONTROL_PRPHRL_RST_OFST (11) // Only GBE10? +#define CONTROL_PRPHRL_RST_MSK (0x00000001 << CONTROL_PRPHRL_RST_OFST) +#define CONTROL_CLR_ACQSTN_FIFO_OFST (15) +#define CONTROL_CLR_ACQSTN_FIFO_MSK (0x00000001 << CONTROL_CLR_ACQSTN_FIFO_OFST) + +/* Pattern IO Control 64 bit register */ +#define PATTERN_IO_CTRL_LSB_REG (0x22 * REG_OFFSET + BASE_CONTROL) +#define PATTERN_IO_CTRL_MSB_REG (0x23 * REG_OFFSET + BASE_CONTROL) /** DTA Offset Register */ -#define DTA_OFFSET_REG (0x104 * REG_OFFSET + BASE_CONTROL) +#define DTA_OFFSET_REG (0x24 * REG_OFFSET + BASE_CONTROL) -/* BASE_ACQUISITION FPGA registers TODO --------------------------------------------------*/ - +/* Acquisition registers --------------------------------------------------*/ +//TODO /* Triggers left 64bit Register */ #define GET_CYCLES_LSB_REG (0x10 + BASE_ACQUISITION) #define GET_CYCLES_MSB_REG (0x14 + BASE_ACQUISITION) diff --git a/slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServer_developer b/slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServer_developer index eb17f2c0f..9c580018e 100755 Binary files a/slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServer_developer and b/slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServer_developer differ diff --git a/slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c b/slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c index 783aad5d3..5f900d3a9 100644 --- a/slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c +++ b/slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c @@ -6,7 +6,7 @@ #include "DAC6571.h" #include "LTC2620_Driver.h" #include "common.h" -#include "ALTERA_PLL_CYCLONE10.h" // pll +#include "ALTERA_PLL_CYCLONE10.h" #ifdef VIRTUAL #include "communication_funcs_UDP.h" #endif @@ -18,8 +18,6 @@ #include #endif -enum {READOUT_PLL, SYSTEM_PLL}; - // Global variable from slsDetectorServer_funcs extern int debugflag; @@ -363,6 +361,8 @@ void setupDetector() { // Default values setHighVoltage(DEFAULT_HIGH_VOLTAGE); setDefaultDacs(); + + // Initialization of acquistion parameters setNumFrames(DEFAULT_NUM_FRAMES); setNumTriggers(DEFAULT_NUM_CYCLES); setExpTime(DEFAULT_EXPTIME); @@ -376,10 +376,7 @@ int setDefaultDacs() { int i = 0; const int defaultvals[NDAC] = DEFAULT_DAC_VALS; for(i = 0; i < NDAC; ++i) { - // if not already default, set it to default - //if (dacValues[i] != defaultvals[i]) { - setDAC((enum DACINDEX)i,defaultvals[i],0); - //} + setDAC((enum DACINDEX)i,defaultvals[i],0); } } return ret; @@ -509,9 +506,6 @@ int getMaxDacSteps() { return LTC2620_D_GetMaxNumSteps(); } - - - int setHighVoltage(int val){ if (val > HV_SOFT_MAX_VOLTAGE) { val = HV_SOFT_MAX_VOLTAGE; diff --git a/slsDetectorServers/gotthard2DetectorServer/slsDetectorServer_defs.h b/slsDetectorServers/gotthard2DetectorServer/slsDetectorServer_defs.h index efdb32ed2..dcfff7bd8 100644 --- a/slsDetectorServers/gotthard2DetectorServer/slsDetectorServer_defs.h +++ b/slsDetectorServers/gotthard2DetectorServer/slsDetectorServer_defs.h @@ -10,7 +10,6 @@ #define NCHIP (10) #define NDAC (16) #define DYNAMIC_RANGE (16) - #define HV_SOFT_MAX_VOLTAGE (200) #define HV_HARD_MAX_VOLTAGE (530) #define HV_DRIVER_FILE_NAME ("/etc/devlinks/hvdac") @@ -29,7 +28,6 @@ #define DEFAULT_SYSTEM_C1 (72222224) // chip_clk, 72 MHz #define DEFAULT_SYSTEM_C2 (18055556) // sync_clk, 18 MHz #define DEFAULT_SYSTEM_C3 (144444448) // str_clk, 144 MHz -#define DEFAULT_TX_UDP_PORT (0x7e9a) /* Firmware Definitions */ #define IP_HEADER_SIZE (20) @@ -78,6 +76,7 @@ enum DACINDEX {G2_VREF_H_ADC, /* 0 */ \ }; enum CLKINDEX {READOUT_C0, READOUT_C1, SYSTEM_C0, SYSTEM_C1, SYSTEM_C2, SYSTEM_C3, NUM_CLOCKS}; #define CLK_NAMES "READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2", "SYSTEM_C3" +enum PLLINDEX {READOUT_PLL, SYSTEM_PLL}; /* Struct Definitions */ typedef struct udp_header_struct { diff --git a/slsDetectorServers/mythen3DetectorServer/CMakeLists.txt b/slsDetectorServers/mythen3DetectorServer/CMakeLists.txt index 883f21614..687e9de86 100644 --- a/slsDetectorServers/mythen3DetectorServer/CMakeLists.txt +++ b/slsDetectorServers/mythen3DetectorServer/CMakeLists.txt @@ -8,6 +8,7 @@ add_executable(mythen3DetectorServer_virtual ../slsDetectorServer/src/DAC6571.c ../slsDetectorServer/src/common.c ../slsDetectorServer/src/LTC2620_Driver.c + ../slsDetectorServer/src/ALTERA_PLL_CYCLONE10.c ) include_directories( diff --git a/slsDetectorServers/mythen3DetectorServer/Makefile b/slsDetectorServers/mythen3DetectorServer/Makefile index 70c908db0..c3f79b8d6 100755 --- a/slsDetectorServers/mythen3DetectorServer/Makefile +++ b/slsDetectorServers/mythen3DetectorServer/Makefile @@ -12,7 +12,7 @@ DESTDIR ?= bin INSTMODE = 0777 SRCS = slsDetectorFunctionList.c -SRCS += $(main_src)slsDetectorServer.c $(main_src)slsDetectorServer_funcs.c $(main_src)communication_funcs.c $(main_src)nios.c $(main_src)DAC6571.c $(main_src)common.c $(main_src)LTC2620_Driver.c +SRCS += $(main_src)slsDetectorServer.c $(main_src)slsDetectorServer_funcs.c $(main_src)communication_funcs.c $(main_src)nios.c $(main_src)DAC6571.c $(main_src)common.c $(main_src)LTC2620_Driver.c $(main_src)ALTERA_PLL_CYCLONE10.c OBJS = $(SRCS:.c=.o) diff --git a/slsDetectorServers/mythen3DetectorServer/RegisterDefs.h b/slsDetectorServers/mythen3DetectorServer/RegisterDefs.h index 43e42df35..854de5380 100644 --- a/slsDetectorServers/mythen3DetectorServer/RegisterDefs.h +++ b/slsDetectorServers/mythen3DetectorServer/RegisterDefs.h @@ -1,11 +1,60 @@ #pragma once -/* Base addresses */ + #define REG_OFFSET (4) -#define BASE_CONTROL (0x0000) -#define BASE_PATTERN_CONTROL (0x00200) -#define BASE_UDP_RAM (0x01000) -#define BASE_PATTERN_RAM (0x10000) + +/* Base addresses 0x1804 0000 ---------------------------------------------*/ +/* Reconfiguration core for readout pll */ +#define BASE_READOUT_PLL (0x0000) // 0x1804_0000 - 0x1804_07FF +/* Reconfiguration core for system pll */ +#define BASE_SYSTEM_PLL (0x0800) // 0x1804_0800 - 0x1804_0FFF + +/* Base addresses 0x1806 0000 ---------------------------------------------*/ +/* General purpose control and status registers */ +#define BASE_CONTROL (0x0000) // 0x1806_0000 - 0x1806_00FF https://git.psi.ch/sls_detectors_firmware/mythen_III_mcb/blob/master/code/hdl/ctrl/ctrl.vhd + +/* ASIC Control */ +#define BASE_ASIC (0x0100) // 0x1806_0100 - 0x1806_010F +/* ASIC Digital Interface. Data recovery core */ +#define BASE_ADIF (0x0110) // 0x1806_0110 - 0x1806_011F https://git.psi.ch/sls_detectors_firmware/vhdl_library/blob/2e81ccbdbc5cb81813ba190fbdba43e8d6884eb9/adif/adif_ctrl.vhd + +/* Formatting of data core */ +#define BASE_FMT (0x0120) // 0x1806_0120 - 0x1806_012F +/* Pattern control and status registers */ +#define BASE_PATTERN_CONTROL (0x00200) // 0x1806_0200 - 0x1806_02FF https://git.psi.ch/sls_detectors_firmware/vhdl_library/blob/2e81ccbdbc5cb81813ba190fbdba43e8d6884eb9/pattern_flow/pattern_flow_ctrl.vhd + +/* UDP datagram generator */ +#define BASE_UDP_RAM (0x01000) // 0x1806_1000 - 0x1806_1FFF +/* Pattern RAM. Pattern table */ +#define BASE_PATTERN_RAM (0x10000) // 0x1807_0000 - 0x1807_FFFF + + + + +/* Readout PLL registers --------------------------------------------------*/ + +#define READOUT_PLL_RESET_REG (0x1 * REG_OFFSET + BASE_READOUT_PLL) //TODO + +#define READOUT_PLL_RESET_OFST (0) +#define READOUT_PLL_RESET_MSK (0x00000001 << READOUT_PLL_RESET_OFST) + +#define READOUT_PLL_WAIT_REG (0x2 * REG_OFFSET + BASE_READOUT_PLL) //TODO + +#define READOUT_PLL_WAIT_OFST (0) +#define READOUT_PLL_WAIT_MSK (0x00000001 << READOUT_PLL_WAIT_OFST) + + +/* System PLL registers --------------------------------------------------*/ + +#define SYSTEM_PLL_RESET_REG (0x1 * REG_OFFSET + BASE_SYSTEM_PLL) //TODO + +#define SYSTEM_PLL_RESET_OFST (0) +#define SYSTEM_PLL_RESET_MSK (0x00000001 << SYSTEM_PLL_RESET_OFST) + +#define SYSTEM_PLL_WAIT_REG (0x2 * REG_OFFSET + BASE_SYSTEM_PLL) //TODO + +#define SYSTEM_PLL_WAIT_OFST (0) +#define SYSTEM_PLL_WAIT_MSK (0x00000001 << SYSTEM_PLL_WAIT_OFST) /* Control registers --------------------------------------------------*/ @@ -13,6 +62,9 @@ /* Module Control Board Serial Number Register */ #define MCB_SERIAL_NO_REG (0x00 * REG_OFFSET + BASE_CONTROL) +#define MCB_SERIAL_NO_VRSN_OFST (16) +#define MCB_SERIAL_NO_VRSN_MSK (0x0000001F << MCB_SERIAL_NO_VRSN_OFST) + /* FPGA Version register */ #define FPGA_VERSION_REG (0x01 * REG_OFFSET + BASE_CONTROL) @@ -47,6 +99,7 @@ #define SYSTEM_STATUS_REG (0x06 * REG_OFFSET + BASE_CONTROL) //Not used in software + /* Config RW regiseter */ #define CONFIG_REG (0x20 * REG_OFFSET + BASE_CONTROL) @@ -57,17 +110,13 @@ #define CONTROL_STRT_ACQSTN_MSK (0x00000001 << CONTROL_STRT_ACQSTN_OFST) #define CONTROL_STP_ACQSTN_OFST (1) #define CONTROL_STP_ACQSTN_MSK (0x00000001 << CONTROL_STP_ACQSTN_OFST) -#define CONTROL_RN_BSY_OFST (2) // assumed for MY3 +#define CONTROL_RN_BSY_OFST (2) // assumed for MY3 TODO #define CONTROL_RN_BSY_MSK (0x00000001 << CONTROL_RN_BSY_OFST) -#define CONTROL_STRT_EXPSR_OFST (6) -#define CONTROL_STRT_EXPSR_MSK (0x00000001 << CONTROL_STRT_EXPSR_OFST) #define CONTROL_CRE_RST_OFST (10) #define CONTROL_CRE_RST_MSK (0x00000001 << CONTROL_CRE_RST_OFST) #define CONTROL_PRPHRL_RST_OFST (11) // Only GBE10? #define CONTROL_PRPHRL_RST_MSK (0x00000001 << CONTROL_PRPHRL_RST_OFST) -// #define CONTROL_MMRY_RST_OFST (12) -// #define CONTROL_MMRY_RST_MSK (0x00000001 << CONTROL_MMRY_RST_OFST) -#define CONTROL_CLR_ACQSTN_FIFO_OFST (14) +#define CONTROL_CLR_ACQSTN_FIFO_OFST (15) #define CONTROL_CLR_ACQSTN_FIFO_MSK (0x00000001 << CONTROL_CLR_ACQSTN_FIFO_OFST) #define CONTROL_PWR_CHIP_OFST (31) #define CONTROL_PWR_CHIP_MSK (0x00000001 << CONTROL_PWR_CHIP_OFST) diff --git a/slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer b/slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer index 100d84674..82e842cba 100755 Binary files a/slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer and b/slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer differ diff --git a/slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c b/slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c index e3d05db0a..3ffba8a18 100644 --- a/slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c +++ b/slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c @@ -6,7 +6,7 @@ #include "LTC2620_Driver.h" #include "common.h" #include "RegisterDefs.h" - +#include "ALTERA_PLL_CYCLONE10.h" #ifdef VIRTUAL #include "communication_funcs_UDP.h" #endif @@ -18,10 +18,10 @@ #include #endif -extern udpStruct udpDetails; // Global variable from slsDetectorServer_funcs extern int debugflag; +extern udpStruct udpDetails; int firmware_compatibility = OK; int firmware_check_done = 0; @@ -33,8 +33,8 @@ int virtual_status = 0; int virtual_stop = 0; #endif -int32_t clkPhase[NUM_CLOCKS] = {0, 0, 0}; -uint32_t clkFrequency[NUM_CLOCKS] = {125, 20, 80}; +int32_t clkPhase[NUM_CLOCKS] = {0, 0, 0, 0, 0, 0}; +uint32_t clkFrequency[NUM_CLOCKS] = {0, 0, 0, 0, 0, 0}; int highvoltage = 0; int dacValues[NDAC] = {0}; @@ -333,18 +333,41 @@ void initStopServer() { void setupDetector() { FILE_LOG(logINFO, ("This Server is for 1 Mythen3 module \n")); - clkFrequency[RUN_CLK] = DEFAULT_RUN_CLK; - clkFrequency[TICK_CLK] = DEFAULT_TICK_CLK; - clkFrequency[SAMPLING_CLK] = DEFAULT_SAMPLING_CLK; + clkFrequency[READOUT_C0] = DEFAULT_READOUT_C0; + clkFrequency[READOUT_C1] = DEFAULT_READOUT_C1; + clkFrequency[SYSTEM_C0] = DEFAULT_SYSTEM_C0; + clkFrequency[SYSTEM_C1] = DEFAULT_SYSTEM_C1; + clkFrequency[SYSTEM_C2] = DEFAULT_SYSTEM_C2; + clkFrequency[SYSTEM_C3] = DEFAULT_SYSTEM_C3; highvoltage = 0; + { + int i; + for (i = 0; i < NUM_CLOCKS; ++i) { + clkPhase[i] = 0; + } + for (i = 0; i < NDAC; ++i) { + dacValues[i] = 0; + } + } #ifndef VIRTUAL + // pll defines + ALTERA_PLL_C10_SetDefines(REG_OFFSET, BASE_READOUT_PLL, BASE_SYSTEM_PLL, READOUT_PLL_RESET_REG, SYSTEM_PLL_RESET_REG, READOUT_PLL_RESET_MSK, SYSTEM_PLL_RESET_MSK, READOUT_PLL_WAIT_REG, SYSTEM_PLL_WAIT_REG, READOUT_PLL_WAIT_MSK, SYSTEM_PLL_WAIT_MSK, READOUT_PLL_VCO_FREQ_HZ, SYSTEM_PLL_VCO_FREQ_HZ); + ALTERA_PLL_C10_ResetPLL(READOUT_PLL); + ALTERA_PLL_C10_ResetPLL(SYSTEM_PLL); // hv DAC6571_SetDefines(HV_HARD_MAX_VOLTAGE, HV_DRIVER_FILE_NAME); //dac LTC2620_D_SetDefines(DAC_MAX_MV, DAC_DRIVER_FILE_NAME, NDAC); #endif + + //TODO? + //resetCore(); + //resetPeripheral(); + //cleanFifos(); + + // defaults setHighVoltage(DEFAULT_HIGH_VOLTAGE); setDefaultDacs(); @@ -369,10 +392,37 @@ int setDefaultDacs() { return ret; } +/* firmware functions (resets) */ + +void cleanFifos() { +#ifdef VIRTUAL + return; +#endif + FILE_LOG(logINFO, ("Clearing Acquisition Fifos\n")); + bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_CLR_ACQSTN_FIFO_MSK); +} + +void resetCore() { +#ifdef VIRTUAL + return; +#endif + FILE_LOG(logINFO, ("Resetting Core\n")); + bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_CRE_RST_MSK); + usleep(1000 * 1000); +} + +void resetPeripheral() { +#ifdef VIRTUAL + return; +#endif + FILE_LOG(logINFO, ("Resetting Peripheral\n")); + bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_PRPHRL_RST_MSK); +} + /* set parameters - dr, roi */ int setDynamicRange(int dr){ - return -1; + return 16; //TODO } @@ -406,12 +456,12 @@ int setExpTime(int64_t val) { return FAIL; } FILE_LOG(logINFO, ("Setting exptime %lld ns\n", (long long int)val)); - val *= (1E-3 * clkFrequency[RUN_CLK]); + val *= (1E-9 * clkFrequency[SYSTEM_C0]); setPatternWaitTime(0, val); // validate for tolerance int64_t retval = getExpTime(); - val /= (1E-3 * clkFrequency[RUN_CLK]); + val /= (1E-9 * clkFrequency[SYSTEM_C0]); if (val != retval) { return FAIL; } @@ -419,7 +469,7 @@ int setExpTime(int64_t val) { } int64_t getExpTime() { - return setPatternWaitTime(0, -1) / (1E-3 * clkFrequency[RUN_CLK]); + return setPatternWaitTime(0, -1) / (1E-9 * clkFrequency[SYSTEM_C0]); } int setPeriod(int64_t val) { @@ -428,12 +478,12 @@ int setPeriod(int64_t val) { return FAIL; } FILE_LOG(logINFO, ("Setting period %lld ns\n", (long long int)val)); - val *= (1E-3 * clkFrequency[TICK_CLK]); + val *= (1E-9 * clkFrequency[SYSTEM_C2]); set64BitReg(val, SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG); // validate for tolerance int64_t retval = getPeriod(); - val /= (1E-3 * clkFrequency[TICK_CLK]); + val /= (1E-9 * clkFrequency[SYSTEM_C2]); if (val != retval) { return FAIL; } @@ -441,7 +491,7 @@ int setPeriod(int64_t val) { } int64_t getPeriod() { - return get64BitReg(SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG)/ (1E-3 * clkFrequency[TICK_CLK]); + return get64BitReg(SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG)/ (1E-9 * clkFrequency[SYSTEM_C2]); } int setDelayAfterTrigger(int64_t val) { @@ -450,12 +500,12 @@ int setDelayAfterTrigger(int64_t val) { return FAIL; } FILE_LOG(logINFO, ("Setting delay after trigger %lld ns\n", (long long int)val)); - val *= (1E-3 * clkFrequency[TICK_CLK]); - set64BitReg(val, SET_DELAY_LSB_REG, SET_DELAY_MSB_REG); + val *= (1E-9 * clkFrequency[SYSTEM_C2]); + set64BitReg(val, SET_TRIGGER_DELAY_LSB_REG, SET_TRIGGER_DELAY_MSB_REG); // validate for tolerance int64_t retval = getDelayAfterTrigger(); - val /= (1E-3 * clkFrequency[TICK_CLK]); + val /= (1E-9 * clkFrequency[SYSTEM_C2]); if (val != retval) { return FAIL; } @@ -463,7 +513,7 @@ int setDelayAfterTrigger(int64_t val) { } int64_t getDelayAfterTrigger() { - return get64BitReg(SET_DELAY_LSB_REG, SET_DELAY_MSB_REG) / (1E-3 * clkFrequency[TICK_CLK]); + return get64BitReg(SET_TRIGGER_DELAY_LSB_REG, SET_TRIGGER_DELAY_MSB_REG) / (1E-9 * clkFrequency[SYSTEM_C2]); } @@ -475,6 +525,25 @@ int64_t getNumTriggersLeft() { return get64BitReg(GET_CYCLES_LSB_REG, GET_CYCLES_MSB_REG); } +int64_t getDelayAfterTriggerLeft() { + return get64BitReg(GET_DELAY_LSB_REG, GET_DELAY_MSB_REG) / (1E-9 * clkFrequency[SYSTEM_C2]); +} + +int64_t getPeriodLeft() { + return get64BitReg(GET_PERIOD_LSB_REG, GET_PERIOD_MSB_REG) / (1E-9 * clkFrequency[SYSTEM_C2]); +} + +int64_t getFramesFromStart() { + return get64BitReg(FRAMES_FROM_START_LSB_REG, FRAMES_FROM_START_MSB_REG); +} + +int64_t getActualTime() { + return get64BitReg(TIME_FROM_START_LSB_REG, TIME_FROM_START_MSB_REG) / (1E-9 * clkFrequency[SYSTEM_C3]);//TODO which clock +} + +int64_t getMeasurementTime() { + return get64BitReg(START_FRAME_TIME_LSB_REG, START_FRAME_TIME_MSB_REG) / (1E-9 * clkFrequency[SYSTEM_C3]);//TODO which clock +} @@ -623,7 +692,7 @@ int configureMAC() { calcChecksum(udp); //TODO? - //cleanFifos(); + cleanFifos(); //resetCore(); //alignDeserializer(); return OK; @@ -894,6 +963,192 @@ int powerChip (int on){ } +int setPhase(enum CLKINDEX ind, int val, int degrees) { + if (ind < 0 || ind >= NUM_CLOCKS) { + FILE_LOG(logERROR, ("Unknown clock index %d to set phase\n", ind)); + return FAIL; + } + char* clock_names[] = {CLK_NAMES}; + FILE_LOG(logINFO, ("Setting %s clock (%d) phase to %d %s\n", clock_names[ind], ind, val, degrees == 0 ? "" : "degrees")); + int maxShift = getMaxPhase(ind); + // validation + if (degrees && (val < 0 || val > 359)) { + FILE_LOG(logERROR, ("\tPhase outside limits (0 - 359°C)\n")); + return FAIL; + } + if (!degrees && (val < 0 || val > maxShift - 1)) { + FILE_LOG(logERROR, ("\tPhase outside limits (0 - %d phase shifts)\n", maxShift - 1)); + return FAIL; + } + + int valShift = val; + // convert to phase shift + if (degrees) { + ConvertToDifferentRange(0, 359, 0, maxShift - 1, val, &valShift); + } + FILE_LOG(logDEBUG1, ("\tphase shift: %d (degrees/shift: %d)\n", valShift, val)); + + int relativePhase = valShift - clkPhase[ind]; + FILE_LOG(logDEBUG1, ("\trelative phase shift: %d (Current phase: %d)\n", relativePhase, clkPhase[ind])); + + // same phase + if (!relativePhase) { + FILE_LOG(logINFO, ("\tNothing to do in Phase Shift\n")); + return OK; + } + FILE_LOG(logINFOBLUE, ("Configuring Phase\n")); + + int phase = 0; + if (relativePhase > 0) { + phase = (maxShift - relativePhase); + } else { + phase = (-1) * relativePhase; + } + FILE_LOG(logDEBUG1, ("\t[Single Direction] Phase:%d (0x%x). Max Phase shifts:%d\n", phase, phase, maxShift)); + + int pllIndex = ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL; + int clkIndex = ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind; + int ret = ALTERA_PLL_C10_SetPhaseShift(pllIndex, clkIndex, phase, 0); + + clkPhase[ind] = valShift; + return ret; +} + +int getPhase(enum CLKINDEX ind, int degrees) { + if (ind < 0 || ind >= NUM_CLOCKS) { + FILE_LOG(logERROR, ("Unknown clock index %d to get phase\n", ind)); + return -1; + } + if (!degrees) + return clkPhase[ind]; + // convert back to degrees + int val = 0; + ConvertToDifferentRange(0, getMaxPhase(ind) - 1, 0, 359, clkPhase[ind], &val); + return val; +} + +int getMaxPhase(enum CLKINDEX ind) { + if (ind < 0 || ind >= NUM_CLOCKS) { + FILE_LOG(logERROR, ("Unknown clock index %d to get max phase\n", ind)); + return -1; + } + int vcofreq = getVCOFrequency(ind); + int maxshiftstep = ALTERA_PLL_C10_GetMaxPhaseShiftStepsofVCO(); + int ret = ((double)vcofreq / (double)clkFrequency[ind]) * maxshiftstep; + + char* clock_names[] = {CLK_NAMES}; + FILE_LOG(logDEBUG1, ("\tMax Phase Shift (%s): %d (Clock: %d Hz, VCO:%d Hz)\n", + clock_names[ind], ret, clkFrequency[ind], vcofreq)); + + return ret; +} + +int validatePhaseinDegrees(enum CLKINDEX ind, int val, int retval) { + if (ind < 0 || ind >= NUM_CLOCKS) { + FILE_LOG(logERROR, ("Unknown clock index %d to validate phase in degrees\n", ind)); + return FAIL; + } + if (val == -1) { + return OK; + } + FILE_LOG(logDEBUG1, ("validating phase in degrees for clk %d\n", (int)ind)); + int maxShift = getMaxPhase(ind); + // convert degrees to shift + int valShift = 0; + ConvertToDifferentRange(0, 359, 0, maxShift - 1, val, &valShift); + // convert back to degrees + ConvertToDifferentRange(0, maxShift - 1, 0, 359, valShift, &val); + + if (val == retval) + return OK; + return FAIL; +} + + + +int getFrequency(enum CLKINDEX ind) { + if (ind < 0 || ind >= NUM_CLOCKS) { + FILE_LOG(logERROR, ("Unknown clock index %d to get frequency\n", ind)); + return -1; + } + return clkFrequency[ind]; +} + +int getVCOFrequency(enum CLKINDEX ind) { + if (ind < 0 || ind >= NUM_CLOCKS) { + FILE_LOG(logERROR, ("Unknown clock index %d to get vco frequency\n", ind)); + return -1; + } + int pllIndex = ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL; + return ALTERA_PLL_C10_GetVCOFrequency(pllIndex); +} + +int getMaxClockDivider() { + return ALTERA_PLL_C10_GetMaxClockDivider(); +} + +int setClockDivider(enum CLKINDEX ind, int val) { + if (ind < 0 || ind >= NUM_CLOCKS) { + FILE_LOG(logERROR, ("Unknown clock index %d to set clock divider\n", ind)); + return FAIL; + } + if (val < 2 || val > getMaxClockDivider()) { + return FAIL; + } + char* clock_names[] = {CLK_NAMES}; + int vcofreq = getVCOFrequency(ind); + int currentdiv = vcofreq / clkFrequency[ind]; + int newfreq = vcofreq / val; + + FILE_LOG(logINFO, ("\tSetting %s clock (%d) divider from %d (%d Hz) to %d (%d Hz). \n\t(Vcofreq: %d Hz)\n", clock_names[ind], ind, currentdiv, clkFrequency[ind], val, newfreq, vcofreq)); + + // Remembering old phases in degrees + int oldPhases[NUM_CLOCKS]; + { + int i = 0; + for (i = 0; i < NUM_CLOCKS; ++i) { + oldPhases [i] = getPhase(i, 1); + FILE_LOG(logDEBUG1, ("\tRemembering %s clock (%d) phase: %d degrees\n", clock_names[ind], ind, oldPhases[i])); + } + } + + // Calculate and set output frequency + int pllIndex = ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL; + int clkIndex = ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind; + int ret = ALTERA_PLL_C10_SetOuputFrequency (pllIndex, clkIndex, newfreq); + clkFrequency[ind] = newfreq; + FILE_LOG(logINFO, ("\t%s clock (%d) divider set to %d (%d Hz)\n", clock_names[ind], ind, val, clkFrequency[ind])); + + // phase is reset by pll (when setting output frequency) + if (ind >= READOUT_C0) { + clkPhase[READOUT_C0] = 0; + clkPhase[READOUT_C1] = 0; + } else { + clkPhase[SYSTEM_C0] = 0; + clkPhase[SYSTEM_C1] = 0; + clkPhase[SYSTEM_C2] = 0; + clkPhase[SYSTEM_C3] = 0; + } + + // set the phase in degreesif custom set + { + int i = 0; + for (i = 0; i < NUM_CLOCKS; ++i) { + FILE_LOG(logINFO, ("\tPhase reset by PLL\n\tCorrecting %s clock (%d) phase to %d degrees\n", clock_names[i], i, oldPhases[i])); + setPhase(i, oldPhases[i], 1); + } + } + return ret; +} + +int getClockDivider(enum CLKINDEX ind) { + if (ind < 0 || ind >= NUM_CLOCKS) { + FILE_LOG(logERROR, ("Unknown clock index %d to get clock divider\n", ind)); + return -1; + } + return (getVCOFrequency(ind) / clkFrequency[ind]); +} + /* aquisition */ int setDetectorPosition(int pos[]) { @@ -924,11 +1179,10 @@ int startStateMachine(){ return OK; #endif FILE_LOG(logINFOBLUE, ("Starting State Machine\n")); - // cleanFifos(); + cleanFifos(); //start state machine - bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_STRT_ACQSTN_MSK | CONTROL_STRT_EXPSR_MSK); - bus_w(CONTROL_REG, bus_r(CONTROL_REG) & ~CONTROL_STRT_ACQSTN_MSK & ~CONTROL_STRT_EXPSR_MSK); + bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_STRT_ACQSTN_MSK); FILE_LOG(logINFO, ("Status Register: %08x\n",bus_r(STATUS_REG))); return OK; @@ -990,9 +1244,6 @@ int stopStateMachine(){ #endif //stop state machine bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_STP_ACQSTN_MSK); - usleep(WAIT_TIME_US_STP_ACQ); - bus_w(CONTROL_REG, bus_r(CONTROL_REG) & ~CONTROL_STP_ACQSTN_MSK); - FILE_LOG(logINFO, ("Status Register: %08x\n",bus_r(STATUS_REG))); return OK; } diff --git a/slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h b/slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h index 916e8c6ff..5e5bbe40f 100644 --- a/slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h +++ b/slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h @@ -23,42 +23,46 @@ #define DEFAULT_PERIOD (2*1000*1000) //ns #define DEFAULT_DELAY_AFTER_TRIGGER (0) #define DEFAULT_HIGH_VOLTAGE (0) -#define DEFAULT_RUN_CLK (125) -#define DEFAULT_TICK_CLK (20) // will be fixed later. Not configurable -#define DEFAULT_SAMPLING_CLK (80) +#define DEFAULT_READOUT_C0 (125000000) // rdo_clk, 125 MHz +#define DEFAULT_READOUT_C1 (250000000) // rdo_x2_clk, 250 MHz +#define DEFAULT_SYSTEM_C0 (125000000) // run_clk, 125 MHz +#define DEFAULT_SYSTEM_C1 (80000000) // chip_clk, 80 MHz +#define DEFAULT_SYSTEM_C2 (20000000) // sync_clk, 20 MHz +#define DEFAULT_SYSTEM_C3 (125000000) // str_clk, 125 MHz /* Firmware Definitions */ #define IP_HEADER_SIZE (20) +#define READOUT_PLL_VCO_FREQ_HZ (750000000) // 750MHz +#define SYSTEM_PLL_VCO_FREQ_HZ (750000000) // 750MHz +#define MAX_PATTERN_LENGTH (0x2000) // maximum number of words (64bit) +#define WAIT_TIME_US_STP_ACQ (100) /** Other Definitions */ #define BIT16_MASK (0xFFFF) -#define DAC_NAMES "vcassh", "vth2", "vshaper", "vshaperneg", "vipre_out", "vth3", "vth1", "vicin", "vcas", "vpreamp", "vph", "vipre", "viinsh", "vpl", "vtrim", "vdcsh" /* Enums */ -enum CLKINDEX {RUN_CLK, TICK_CLK, SAMPLING_CLK, NUM_CLOCKS}; -enum DACINDEX {M_CASSH, M_VTH2, M_VRFSH, M_VRFSHNPOL, M_VIPRE_OUT, M_VTH3, M_VTH1, M_VICIN, M_CAS, M_VRF, M_VPH, M_VIPRE, M_VIINSH, M_VPL, M_VTRIM, M_VDCSH}; -#define DEFAULT_DAC_VALS {1200, /* casSh */ \ - 2800, /* Vth2 */ \ - 1280, /* VrfSh */ \ - 2800, /* VrfShNpol */ \ - 1220, /* vIpreOut */ \ - 2800, /* Vth3 */ \ - 2800, /* Vth1 */ \ - 1708, /* vIcin */ \ - 1800, /* cas */ \ - 1100, /* Vrf */ \ - 1712, /* VPH */ \ - 2624, /* vIpre */ \ - 1708, /* vIinSh */ \ - 1100, /* VPL */ \ - 2800, /* vTrim */ \ - 800 /* VdcSh */ \ - }; - - -/* Defines in the Firmware */ -#define MAX_PATTERN_LENGTH (0x2000) // maximum number of words (64bit) -#define WAIT_TIME_US_STP_ACQ (100) +enum DACINDEX {M_CASSH, M_VTH2, M_VRFSH, M_VRFSHNPOL, M_VIPRE_OUT, M_VTH3, M_VTH1, M_VICIN, M_CAS, M_VRF, M_VPH, M_VIPRE, M_VIINSH, M_VPL, M_VTRIM, M_VDCSH}; +#define DAC_NAMES "vcassh", "vth2", "vshaper", "vshaperneg", "vipre_out", "vth3", "vth1", "vicin", "vcas", "vpreamp", "vph", "vipre", "viinsh", "vpl", "vtrim", "vdcsh" +#define DEFAULT_DAC_VALS {1200, /* casSh */ \ + 2800, /* Vth2 */ \ + 1280, /* VrfSh */ \ + 2800, /* VrfShNpol */ \ + 1220, /* vIpreOut */ \ + 2800, /* Vth3 */ \ + 2800, /* Vth1 */ \ + 1708, /* vIcin */ \ + 1800, /* cas */ \ + 1100, /* Vrf */ \ + 1712, /* VPH */ \ + 2624, /* vIpre */ \ + 1708, /* vIinSh */ \ + 1100, /* VPL */ \ + 2800, /* vTrim */ \ + 800 /* VdcSh */ \ + }; +enum CLKINDEX {READOUT_C0, READOUT_C1, SYSTEM_C0, SYSTEM_C1, SYSTEM_C2, SYSTEM_C3, NUM_CLOCKS}; +#define CLK_NAMES "READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2", "SYSTEM_C3" +enum PLLINDEX {READOUT_PLL, SYSTEM_PLL}; /* Struct Definitions */ typedef struct udp_header_struct { diff --git a/slsDetectorServers/slsDetectorServer/include/slsDetectorFunctionList.h b/slsDetectorServers/slsDetectorServer/include/slsDetectorFunctionList.h index 5dad01efd..580fc067f 100755 --- a/slsDetectorServers/slsDetectorServer/include/slsDetectorFunctionList.h +++ b/slsDetectorServers/slsDetectorServer/include/slsDetectorFunctionList.h @@ -103,7 +103,7 @@ extern u_int32_t readRegister(u_int32_t offset); // black // firmware functions (resets) -#ifdef JUNGFRAUD +#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D) void cleanFifos(); void resetCore(); void resetPeripheral(); @@ -118,14 +118,6 @@ void setROIADC(int adc); void setGbitReadout(); int readConfigFile(); void setMasterSlaveConfiguration(); -#elif CHIPTESTBOARDD -void cleanFifos(); -void resetCore(); -void resetPeripheral(); -#elif MOENCHD -void cleanFifos(); -void resetCore(); -void resetPeripheral(); #endif // parameters - dr, roi @@ -208,14 +200,14 @@ int64_t getDelayAfterTrigger(); int64_t getNumFramesLeft(); int64_t getNumTriggersLeft(); #endif -#if defined(JUNGFRAUD) || defined(GOTTHARDD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) +#if defined(JUNGFRAUD) || defined(GOTTHARDD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D) int64_t getDelayAfterTriggerLeft(); int64_t getPeriodLeft(); #endif #ifdef GOTTHARDD int64_t getExpTimeLeft(); #endif -#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) +#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D) int64_t getFramesFromStart(); int64_t getActualTime(); int64_t getMeasurementTime(); @@ -425,7 +417,16 @@ int setPatternWaitAddress(int level, int addr); uint64_t setPatternWaitTime(int level, uint64_t t); void setPatternLoop(int level, int *startAddr, int *stopAddr, int *nLoop); int powerChip (int on); - +int setPhase(enum CLKINDEX ind, int val, int degrees); +int getPhase(enum CLKINDEX ind, int degrees); +int getMaxPhase(enum CLKINDEX ind); +int validatePhaseinDegrees(enum CLKINDEX ind, int val, int retval); +//void setFrequency(enum CLKINDEX ind, int val); +int getFrequency(enum CLKINDEX ind); +int getVCOFrequency(enum CLKINDEX ind); +int getMaxClockDivider(); +int setClockDivider(enum CLKINDEX ind, int val); +int getClockDivider(enum CLKINDEX ind); #elif GOTTHARD2D int setPhase(enum CLKINDEX ind, int val, int degrees); diff --git a/slsDetectorServers/slsDetectorServer/src/nios.c b/slsDetectorServers/slsDetectorServer/src/nios.c index a9efa5584..a375c9052 100755 --- a/slsDetectorServers/slsDetectorServer/src/nios.c +++ b/slsDetectorServers/slsDetectorServer/src/nios.c @@ -10,7 +10,7 @@ /* global variables */ u_int32_t* csp0base = 0; #define CSP0 0x18060000 -#define MEM_SIZE 0x100000 +#define MEM_SIZE 0x100000 //TODO (1804 0000 - 1804 07FF = 800 * 4 = 2000), (1806 0000 = 10000* 4 = 40000) u_int32_t* csp1base = 0; #define CSP1 0x18040000 diff --git a/slsDetectorServers/slsDetectorServer/src/slsDetectorServer_funcs.c b/slsDetectorServers/slsDetectorServer/src/slsDetectorServer_funcs.c index 3b5f4d3ac..0be28f545 100755 --- a/slsDetectorServers/slsDetectorServer/src/slsDetectorServer_funcs.c +++ b/slsDetectorServers/slsDetectorServer/src/slsDetectorServer_funcs.c @@ -2393,7 +2393,7 @@ int get_period_left(int file_des) { memset(mess, 0, sizeof(mess)); int64_t retval = -1; -#if !defined(JUNGFRAUD) && !defined(GOTTHARDD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) +#if !defined(JUNGFRAUD) && !defined(GOTTHARDD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D) functionNotImplemented(); #else // get only @@ -2408,7 +2408,7 @@ int get_delay_after_trigger_left(int file_des) { memset(mess, 0, sizeof(mess)); int64_t retval = -1; -#if !defined(JUNGFRAUD) && !defined(GOTTHARDD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) +#if !defined(JUNGFRAUD) && !defined(GOTTHARDD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D) functionNotImplemented(); #else // get only @@ -2453,7 +2453,7 @@ int get_frames_from_start(int file_des) { memset(mess, 0, sizeof(mess)); int64_t retval = -1; -#if !defined(JUNGFRAUD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) +#if !defined(JUNGFRAUD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D) functionNotImplemented(); #else // get only @@ -2468,7 +2468,7 @@ int get_actual_time(int file_des) { memset(mess, 0, sizeof(mess)); int64_t retval = -1; -#if !defined(JUNGFRAUD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) +#if !defined(JUNGFRAUD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D) functionNotImplemented(); #else // get only @@ -2483,7 +2483,7 @@ int get_measurement_time(int file_des) { memset(mess, 0, sizeof(mess)); int64_t retval = -1; -#if !defined(JUNGFRAUD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) +#if !defined(JUNGFRAUD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D) functionNotImplemented(); #else // get only @@ -3188,7 +3188,7 @@ int write_adc_register(int file_des) { uint32_t val = args[1]; FILE_LOG(logDEBUG1, ("Writing 0x%x to ADC Register 0x%x\n", val, addr)); -#if defined(EIGERD) || defined(GOTTHARD2D) +#if defined(EIGERD) || defined(GOTTHARD2D) || defined(MYTHEN3D) functionNotImplemented(); #else #ifndef VIRTUAL @@ -3722,7 +3722,7 @@ int reset_fpga(int file_des) { memset(mess, 0, sizeof(mess)); FILE_LOG(logDEBUG1, ("Reset FPGA\n")); -#if defined(EIGERD) || defined(GOTTHARDD) || defined(GOTTHARD2D) +#if defined(EIGERD) || defined(GOTTHARDD) || defined(GOTTHARD2D) || defined(MYTHEN3D) functionNotImplemented(); #else // only set @@ -5567,7 +5567,7 @@ int get_clock_frequency(int file_des) { return printSocketReadError(); FILE_LOG(logDEBUG1, ("Getting clock (%d) frequency\n", arg)); -#if !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(GOTTHARD2D) +#if !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(GOTTHARD2D) && !defined(MYTHEN3D) functionNotImplemented(); #else // get only @@ -5588,7 +5588,7 @@ int get_clock_frequency(int file_des) { break; #endif default: -#ifdef GOTTHARD2D +#if defined(GOTTHARD2D) || defined(MYTHEN3D) if (c < NUM_CLOCKS) { c = (enum CLKINDEX)arg; break; @@ -5600,7 +5600,7 @@ int get_clock_frequency(int file_des) { if (ret == OK) { retval = getFrequency(c); char* clock_names[] = {CLK_NAMES}; - FILE_LOG(logDEBUG1, ("retval %s clock (%d) frequency: %d %s\n", clock_names[c], (int)c, retval, myDetectorType == GOTTHARD2 ? "Hz" : "MHz")); + FILE_LOG(logDEBUG1, ("retval %s clock (%d) frequency: %d %s\n", clock_names[c], (int)c, retval, myDetectorType == GOTTHARD2 || myDetectorType == MYTHEN3 ? "Hz" : "MHz")); } #endif return Server_SendResult(file_des, INT32, UPDATE, &retval, sizeof(retval)); @@ -5618,7 +5618,7 @@ int set_clock_phase(int file_des) { return printSocketReadError(); FILE_LOG(logDEBUG1, ("Setting clock (%d) phase: %u %s\n", args[0], args[1], (args[2] == 0 ? "" : "degrees"))); -#if !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(JUNGFRAUD)&& !defined(GOTTHARDD) && !defined(GOTTHARD2D) +#if !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(JUNGFRAUD)&& !defined(GOTTHARDD) && !defined(GOTTHARD2D) && !defined(MYTHEN3D) functionNotImplemented(); #else // only set @@ -5639,7 +5639,7 @@ int set_clock_phase(int file_des) { break; #endif default: -#ifdef GOTTHARD2D +#if defined(GOTTHARD2D) || defined(MYTHEN3D) if (c < NUM_CLOCKS) { c = (enum CLKINDEX)ind; break; @@ -5654,7 +5654,7 @@ int set_clock_phase(int file_des) { sprintf(modeName, "%s clock (%d) phase %s", clock_names[c], (int)c, (inDegrees == 0 ? "" : "(degrees)")); // gotthard1d doesnt take degrees and cannot get phase -#ifdef GOTTHARDD +#ifndef GOTTHARDD if (inDegrees != 0) { ret = FAIL; strcpy(mess, "Cannot set phase in degrees for this detector.\n"); @@ -5714,7 +5714,7 @@ int get_clock_phase(int file_des) { return printSocketReadError(); FILE_LOG(logDEBUG1, ("Getting clock (%d) phase %s \n", args[0], (args[1] == 0 ? "" : "in degrees"))); -#if !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(JUNGFRAUD) && !defined(GOTTHARD2D) +#if !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(JUNGFRAUD) && !defined(GOTTHARD2D) && !defined(MYTHEN3D) functionNotImplemented(); #else // get only @@ -5733,7 +5733,7 @@ int get_clock_phase(int file_des) { break; #endif default: -#ifdef GOTTHARD2D +#if defined(GOTTHARD2D) || defined(MYTHEN3D) if (c < NUM_CLOCKS) { c = (enum CLKINDEX)ind; break; @@ -5762,7 +5762,7 @@ int get_max_clock_phase_shift(int file_des) { return printSocketReadError(); FILE_LOG(logDEBUG1, ("Getting clock (%d) max phase shift\n", arg)); -#if !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(JUNGFRAUD) && !defined(GOTTHARD2D) +#if !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(JUNGFRAUD) && !defined(GOTTHARD2D) && !defined(MYTHEN3D) functionNotImplemented(); #else // get only @@ -5779,7 +5779,7 @@ int get_max_clock_phase_shift(int file_des) { break; #endif default: -#ifdef GOTTHARD2D +#if defined(GOTTHARD2D) || defined(MYTHEN3D) if (c < NUM_CLOCKS) { c = (enum CLKINDEX)arg; break; @@ -5807,7 +5807,7 @@ int set_clock_divider(int file_des) { return printSocketReadError(); FILE_LOG(logDEBUG1, ("Setting clock (%d) divider: %u\n", args[0], args[1])); -#if !defined(EIGERD) && !defined(JUNGFRAUD) && !defined(GOTTHARD2D) +#if !defined(EIGERD) && !defined(JUNGFRAUD) && !defined(GOTTHARD2D) && !defined(MYTHEN3D) functionNotImplemented(); #else // only set @@ -5824,7 +5824,7 @@ int set_clock_divider(int file_des) { #endif default: // any clock index -#ifdef GOTTHARD2D +#if defined(GOTTHARD2D) || defined(MYTHEN3D) if (c < NUM_CLOCKS) { c = (enum CLKINDEX)ind; break; @@ -5843,7 +5843,7 @@ int set_clock_divider(int file_des) { FILE_LOG(logERROR,(mess)); } else #endif -#ifdef GOTTHARD2D +#if defined(GOTTHARD2D) || defined(MYTHEN3D) if (val < 2 || val > getMaxClockDivider()) { char* clock_names[] = {CLK_NAMES}; ret = FAIL; @@ -5861,7 +5861,7 @@ int set_clock_divider(int file_des) { if (ret != FAIL) { char modeName[50] = "speed"; -#ifdef GOTTHARD2D +#if defined(GOTTHARD2D) || defined(MYTHEN3D) char* clock_names[] = {CLK_NAMES}; sprintf(modeName, "%s clock (%d) divider", clock_names[c], (int)c); #endif @@ -5895,7 +5895,7 @@ int get_clock_divider(int file_des) { return printSocketReadError(); FILE_LOG(logDEBUG1, ("Getting clock (%d) divider\n", arg)); -#if !defined(EIGERD) && !defined(JUNGFRAUD) && !defined(GOTTHARD2D) +#if !defined(EIGERD) && !defined(JUNGFRAUD) && !defined(GOTTHARD2D) && !defined(MYTHEN3D) functionNotImplemented(); #else // get only @@ -5907,7 +5907,7 @@ int get_clock_divider(int file_des) { break; #endif default: -#ifdef GOTTHARD2D +#if defined(GOTTHARD2D) || defined(MYTHEN3D) if (c < NUM_CLOCKS) { c = (enum CLKINDEX)arg; break; diff --git a/slsDetectorSoftware/src/CmdProxy.cpp b/slsDetectorSoftware/src/CmdProxy.cpp index a2c9e586c..62ddd3786 100644 --- a/slsDetectorSoftware/src/CmdProxy.cpp +++ b/slsDetectorSoftware/src/CmdProxy.cpp @@ -404,9 +404,10 @@ std::string CmdProxy::ClockFrequency(int action) { std::ostringstream os; os << cmd << ' '; if (action == defs::HELP_ACTION) { - os << "[n_clock (0-8)] [freq_in_Hz]\n\t[Gotthard2] Frequency of clock n_clock in Hz. Use clkdiv to set frequency." << '\n'; + os << "[n_clock (0-8)] [freq_in_Hz]\n\t[Gotthard2][Mythen3] Frequency of clock n_clock in Hz. Use clkdiv to set frequency." << '\n'; } else { - if (det->getDetectorType().squash(defs::GENERIC) != defs::GOTTHARD2) { + defs::detectorType type = det->getDetectorType().squash(defs::GENERIC); + if (type != defs::GOTTHARD2 && type != MYTHEN3) { throw sls::RuntimeError("Not implemented for this detector."); } if (action == defs::GET_ACTION) { @@ -433,9 +434,10 @@ std::string CmdProxy::ClockPhase(int action) { std::ostringstream os; os << cmd << ' '; if (action == defs::HELP_ACTION) { - os << "[n_clock (0-8)] [phase] [deg (optional)]\n\t[Gotthard2] Phase of clock n_clock. If deg, then phase shift in degrees, else absolute phase shift values." << '\n'; + os << "[n_clock (0-8)] [phase] [deg (optional)]\n\t[Gotthard2][Mythen3] Phase of clock n_clock. If deg, then phase shift in degrees, else absolute phase shift values." << '\n'; } else { - if (det->getDetectorType().squash(defs::GENERIC) != defs::GOTTHARD2) { + defs::detectorType type = det->getDetectorType().squash(defs::GENERIC); + if (type != defs::GOTTHARD2 && type != MYTHEN3) { throw sls::RuntimeError("Not implemented for this detector."); } if (action == defs::GET_ACTION) { @@ -475,9 +477,10 @@ std::string CmdProxy::MaxClockPhaseShift(int action) { std::ostringstream os; os << cmd << ' '; if (action == defs::HELP_ACTION) { - os << "[n_clock (0-8)]\n\t[Gotthard2] Absolute Maximum Phase shift of clock n_clock." << '\n'; + os << "[n_clock (0-8)]\n\t[Gotthard2][Mythen3] Absolute Maximum Phase shift of clock n_clock." << '\n'; } else { - if (det->getDetectorType().squash(defs::GENERIC) != defs::GOTTHARD2) { + defs::detectorType type = det->getDetectorType().squash(defs::GENERIC); + if (type != defs::GOTTHARD2 && type != MYTHEN3) { throw sls::RuntimeError("Not implemented for this detector."); } if (action == defs::GET_ACTION) { @@ -499,9 +502,10 @@ std::string CmdProxy::ClockDivider(int action) { std::ostringstream os; os << cmd << ' '; if (action == defs::HELP_ACTION) { - os << "[n_clock (0-8)] [n_divider]\n\t[Gotthard2] Clock Divider of clock n_clock. Must be greater than 1." << '\n'; + os << "[n_clock (0-8)] [n_divider]\n\t[Gotthard2][Mythen3] Clock Divider of clock n_clock. Must be greater than 1." << '\n'; } else { - if (det->getDetectorType().squash(defs::GENERIC) != defs::GOTTHARD2) { + defs::detectorType type = det->getDetectorType().squash(defs::GENERIC); + if (type != defs::GOTTHARD2 && type != MYTHEN3) { throw sls::RuntimeError("Not implemented for this detector."); } if (action == defs::GET_ACTION) { diff --git a/slsDetectorSoftware/tests/test-multiSlsDetectorClient.cpp b/slsDetectorSoftware/tests/test-multiSlsDetectorClient.cpp index a4b417382..a6492ad2f 100644 --- a/slsDetectorSoftware/tests/test-multiSlsDetectorClient.cpp +++ b/slsDetectorSoftware/tests/test-multiSlsDetectorClient.cpp @@ -4044,8 +4044,8 @@ TEST_CASE("delayl", "[.cmd][.jungfrau][gotthard][ctb]") { REQUIRE_NOTHROW(multiSlsDetectorClient("delay 0", PUT)); } } -TEST_CASE("clk", "[.cmd]") { - if(test::type == slsDetectorDefs::GOTTHARD2) { +TEST_CASE("clk", "[.cmd][.gotthard2][.mythen3]") { + if(test::type == slsDetectorDefs::GOTTHARD2 || test::type == slsDetectorDefs::MYTHEN3) { REQUIRE_THROWS(multiSlsDetectorClient("clkfreq 0 2", PUT)); // cannot get REQUIRE_THROWS(multiSlsDetectorClient("clkfreq", GET)); // requires clk index REQUIRE_THROWS(multiSlsDetectorClient("clkfreq 7", GET)); // 7 doesnt exist diff --git a/slsSupportLib/include/versionAPI.h b/slsSupportLib/include/versionAPI.h index 7a76c0f6a..82056f70f 100644 --- a/slsSupportLib/include/versionAPI.h +++ b/slsSupportLib/include/versionAPI.h @@ -7,6 +7,6 @@ #define APIJUNGFRAU 0x191106 #define APIEIGER 0x191106 #define APIGOTTHARD 0x191106 -#define APIMYTHEN3 0x191106 -#define APIGOTTHARD2 0x191106 #define APICTB 0x191106 +#define APIGOTTHARD2 0x191106 +#define APIMYTHEN3 0x191106