updated mythen3 to configure phase, freq, delay left, period left, actual time, measurement time, framesfrom start and othe register mappings

This commit is contained in:
2019-11-06 18:58:22 +01:00
parent 0f9fd5cd73
commit 1797d39216
16 changed files with 493 additions and 147 deletions

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@ -10,7 +10,6 @@
#define NCHIP (10)
#define NDAC (16)
#define DYNAMIC_RANGE (16)
#define HV_SOFT_MAX_VOLTAGE (200)
#define HV_HARD_MAX_VOLTAGE (530)
#define HV_DRIVER_FILE_NAME ("/etc/devlinks/hvdac")
@ -29,7 +28,6 @@
#define DEFAULT_SYSTEM_C1 (72222224) // chip_clk, 72 MHz
#define DEFAULT_SYSTEM_C2 (18055556) // sync_clk, 18 MHz
#define DEFAULT_SYSTEM_C3 (144444448) // str_clk, 144 MHz
#define DEFAULT_TX_UDP_PORT (0x7e9a)
/* Firmware Definitions */
#define IP_HEADER_SIZE (20)
@ -78,6 +76,7 @@ enum DACINDEX {G2_VREF_H_ADC, /* 0 */ \
};
enum CLKINDEX {READOUT_C0, READOUT_C1, SYSTEM_C0, SYSTEM_C1, SYSTEM_C2, SYSTEM_C3, NUM_CLOCKS};
#define CLK_NAMES "READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2", "SYSTEM_C3"
enum PLLINDEX {READOUT_PLL, SYSTEM_PLL};
/* Struct Definitions */
typedef struct udp_header_struct {