mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-04-23 06:50:02 +02:00
somewhere
This commit is contained in:
Dhanya Maliakal
parent
978af1009e
commit
0ea61a1e3f
File diff suppressed because it is too large
Load Diff
@ -1,10 +1,7 @@
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#ifndef FIRMWARE_FUNCS_H
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#define FIRMWARE_FUNCS_H
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#include "sls_detector_defs.h"
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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@ -20,87 +17,38 @@
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#include <stdarg.h>
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#include <unistd.h>
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int mapCSP0(void);
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void defineGPIOpins();
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void resetFPGA();
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void FPGAdontTouchFlash();
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void FPGATouchFlash();
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int powerChip (int on);
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void initializeDetector();
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int checkType();
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void printVersions();
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u_int16_t bus_w16(u_int32_t offset, u_int16_t data);
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u_int16_t bus_r16(u_int32_t offset);
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u_int16_t bus_w16(u_int32_t offset, u_int16_t data);//aldos function
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u_int16_t ram_w16(u_int32_t ramType, int adc, int adcCh, int Ch, u_int16_t data);
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u_int16_t ram_r16(u_int32_t ramType, int adc, int adcCh, int Ch);
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u_int32_t bus_w(u_int32_t offset, u_int32_t data);
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u_int32_t bus_r(u_int32_t offset);
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int setPhaseShiftOnce();
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int adcPhase(int st);
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int getPhase();
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int cleanFifo();
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int setDAQRegister();
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u_int32_t putout(char *s, int modnum);
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u_int32_t readin(int modnum);
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u_int32_t setClockDivider(int d);
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u_int32_t getClockDivider();
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void resetPLL();
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u_int32_t setPllReconfigReg(u_int32_t reg, u_int32_t val, int trig);
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u_int32_t getPllReconfigReg(u_int32_t reg, int trig);
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u_int32_t setSetLength(int d);
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u_int32_t getSetLength();
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u_int32_t setWaitStates(int d);
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u_int32_t getWaitStates();
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u_int32_t setTotClockDivider(int d);
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u_int32_t getTotClockDivider();
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u_int32_t setTotDutyCycle(int d);
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u_int32_t getTotDutyCycle();
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u_int32_t setOversampling(int d);
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u_int32_t adcPipeline(int d);
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u_int32_t dbitPipeline(int d);
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u_int32_t setExtSignal(int d, enum externalSignalFlag mode);
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int getExtSignal(int d);
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u_int32_t setFPGASignal(int d, enum externalSignalFlag mode);
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int getFPGASignal(int d);
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int setTiming(int t);
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int setConfigurationRegister(int d);
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int setToT(int d);
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int setContinousReadOut(int d);
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int setDACRegister(int idac, int val, int imod);
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int getDacRegister(int dacnum);
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int getTemperature(int tempSensor,int imod);
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int initHighVoltage(int val,int imod);
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int initConfGain(int isettings,int val,int imod);
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int initSpeedConfGain(int val);
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int setADC(int adc);
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//int configureMAC(int ipad, long long int macad, long long int detectormacadd, int detipad, int ival, int udpport);
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int configureMAC(uint32_t destip,uint64_t destmac,uint64_t sourcemac,int detipad,int ival,uint32_t destport);
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int getAdcConfigured();
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u_int64_t getDetectorNumber();
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u_int64_t getFirmwareVersion();
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int64_t getId(enum idMode arg);
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void initializeDetector();
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int checkType();
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void printVersions();
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int testFifos(void);
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u_int32_t testFpga(void);
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u_int32_t testRAM(void);
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int testBus(void);
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int setDigitalTestBit(int ival);
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u_int64_t getDetectorNumber();
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u_int64_t getFirmwareVersion();
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int64_t getId(enum idMode arg);
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void defineGPIOpins();
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void resetFPGA();
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void FPGAdontTouchFlash();
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void FPGATouchFlash();
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void eraseFlash();
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int startWritingFPGAprogram(FILE** filefp);
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int stopWritingFPGAprogram(FILE* filefp);
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int writeFPGAProgram(char* fpgasrc, size_t fsize, FILE* filefp);
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long int calcChecksum(int sourceip, int destip);
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void configureMAC(uint32_t destip,uint64_t destmac,uint64_t sourcemac,int detipad,int ival,uint32_t destport);
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int64_t set64BitReg(int64_t value, int aLSB, int aMSB);
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int64_t get64BitReg(int aLSB, int aMSB);
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@ -123,7 +71,6 @@ int64_t getPeriod();
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int64_t setTrains(int64_t value);
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int64_t getTrains();
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int64_t setProbes(int64_t value);
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int64_t getProbes();
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@ -134,51 +81,56 @@ int64_t getActualTime();
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int64_t getMeasurementTime();
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int64_t getFramesFromStart();
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u_int32_t runBusy(void);
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u_int32_t runState(void);
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int startStateMachine();
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int stopStateMachine();
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int startReadOut();
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enum runStatus getStatus();
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u_int32_t fifoReset(void);
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u_int32_t fifoReadCounter(int fifonum);
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u_int32_t fifoReadStatus();
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u_int32_t fifo_full(void);
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void waitForAcquisitionEnd();
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u_int32_t* decode_data(int* datain);
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//u_int32_t move_data(u_int64_t* datain, u_int64_t* dataout);
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int setDynamicRange(int dr);
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int getDynamicRange();
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int getNModBoard();
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int setNMod(int n);
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int getNMod();
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int setStoreInRAM(int b);
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int allocateRAM();
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u_int32_t runBusy(void);
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u_int32_t runState(void);
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int startStateMachine();
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int stopStateMachine();
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int startReadOut();
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enum runStatus getStatus();
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void waitForAcquisitionEnd();
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int writeADC(int addr, int val);
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int prepareADC();
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void serializeToSPI(int bitsize, u_int32_t val, u_int16_t csmask, int numbitstosend, u_int16_t clkmask, u_int16_t digoutmask, int digofset);
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void initDac(int dacnum);
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int setDac(int dacnum, int dacvalue);
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int setHighVoltage(int val, int imod);
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void setAdc(int addr, int val);
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void configureAdc();
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void prepareADC();
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int powerChip (int on);
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int setPhaseShiftOnce();
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int adcPhase(int st);
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int getPhase();
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int clearRAM();
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u_int32_t putout(char *s, int modnum);
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u_int32_t readin(int modnum);
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u_int32_t setClockDivider(int d);
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u_int32_t getClockDivider();
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void resetPLL();
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u_int32_t setPllReconfigReg(u_int32_t reg, u_int32_t val, int trig);
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u_int32_t getPllReconfigReg(u_int32_t reg, int trig);
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void configurePll(int i);
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int setMaster(int f);
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int setSynchronization(int s);
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int getTemperature(int tempSensor,int imod);
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int initConfGain(int isettings,int val,int imod);
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int initSpeedConfGain(int val);
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ROI *setROI(int nroi,ROI* arg,int *retvalsize, int *ret);
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int getChannels();
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int loadImage(int index, short int ImageVals[]);
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int readCounterBlock(int startACQ, short int CounterVals[]);
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int resetCounterBlock(int startACQ);
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int calibratePedestal(int frames);
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uint64_t readPatternWord(int addr);
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uint64_t writePatternWord(int addr, uint64_t word);
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uint64_t writePatternIOControl(uint64_t word);
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uint64_t writePatternClkControl(uint64_t word);
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@ -186,41 +138,12 @@ int setPatternLoop(int level, int *start, int *stop, int *n);
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int setPatternWaitAddress(int level, int addr);
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uint64_t setPatternWaitTime(int level, uint64_t t);
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void initDac(int dacnum);
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int setDac(int dacnum,int dacvalue);
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ROI *setROI(int nroi,ROI* arg,int *retvalsize, int *ret);
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int getChannels();
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void eraseFlash();
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int startWritingFPGAprogram(FILE** filefp);
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int stopWritingFPGAprogram(FILE* filefp);
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int writeFPGAProgram(char* fpgasrc, size_t fsize, FILE* filefp);
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/*
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u_int32_t setNBits(u_int32_t);
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u_int32_t getNBits();
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*/
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/*
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//move to mcb_funcs?
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int readOutChan(int *val);
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u_int32_t getModuleNumber(int modnum);
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int testShiftIn(int imod);
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int testShiftOut(int imod);
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int testShiftStSel(int imod);
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int testDataInOut(int num, int imod);
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int testExtPulse(int imod);
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int testExtPulseMux(int imod, int ow);
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int testDataInOutMux(int imod, int ow, int num);
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int testOutMux(int imod);
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int testFpgaMux(int imod);
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int calibration_sensor(int num, int *values, int *dacs) ;
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int calibration_chip(int num, int *values, int *dacs);
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*/
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u_int32_t setExtSignal(int d, enum externalSignalFlag mode);
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int getExtSignal(int d);
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u_int32_t setFPGASignal(int d, enum externalSignalFlag mode);
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int getFPGASignal(int d);
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int setTiming(int t);
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int setMaster(int f);
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int setSynchronization(int s);
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#endif
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@ -18,7 +18,7 @@
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/* global variables */
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#undef DEBUG
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#undef DEBUGOUT
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extern enum detectorType myDetectorType;
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extern int nModX;
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@ -799,13 +799,8 @@ int initChip(int obe, int ow,int imod){
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int chipmi, chipma, modmi, modma;
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#ifdef DEBUGOUT
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printf("Initializing chip\n");
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#endif
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putout("0000000000000000",imod);
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#ifdef DEBUGOUT
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printf("Output mode= %d\n", ow);
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#endif
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/* clearing shift in register */
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for (i=0; i<10; i++)
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@ -842,9 +837,7 @@ int initChip(int obe, int ow,int imod){
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putout("0000000000000000",imod);
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}
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}
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#ifdef DEBUGOUT
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printf("Output buffer enable= %d\n", obe);
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#endif
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if (obe) {
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putout("0100000000000000",imod);
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putout("0110000000000000",imod);
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@ -1025,16 +1018,12 @@ int initMCBregisters(int cm, int imod){
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if (cm) {
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putout("0000000001000001",imod);
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#ifdef DEBUGOUT
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printf("enabling cal through sensor\n");
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#endif
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} else {
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putout("0000000001000001",imod);
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putout("0000000001000000",imod);
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putout("0000000001000001",imod);
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#ifdef DEBUGOUT
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printf("disabling cal through sensor\n");
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#endif
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}
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putout("0000000001000000",imod);
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@ -1542,9 +1531,7 @@ int testOutMux(int imod) {
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//dist=2*ibit;
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if (dist==0)
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dist=1;
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#ifdef DEBUGOUT
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printf("Distance is %d\n",dist);
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#endif
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@ -1557,9 +1544,7 @@ int testOutMux(int imod) {
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//for (k=0; k<nModX; k++) {
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val=readin(k);
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//val=bus_r(MCB_DOUT_REG_OFF+(k<<SHIFTMOD)) & 0x3ff;
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#ifdef DEBUGOUT
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printf("%d %x\n",i*dist,val);
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#endif
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for (j=0; j<NCHIP; j++) {
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v=val & 1<< j;
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if (pat & (1<<(i*dist))) {
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@ -1585,9 +1570,7 @@ int testOutMux(int imod) {
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//for (k=0; k<nModX; k++) {
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val=readin(k);
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//val=bus_r(MCB_DOUT_REG_OFF+(k<<SHIFTMOD)) & 0x3ff;
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#ifdef DEBUGOUT
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printf("%d %x\n",i*dist, val);
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#endif
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for (j=0; j<NCHIP; j++) {
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v=val & 1<< j;
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if (pat & (1<<(i*dist))) {
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@ -1618,9 +1601,7 @@ int testOutMux(int imod) {
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//for (k=0; k<nModX; k++) {
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val=readin(k);
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//val=bus_r(MCB_DOUT_REG_OFF+(k<<SHIFTMOD)) & 0x3ff;
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#ifdef DEBUGOUT
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printf("%d %x\n",i*dist, val);
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#endif
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for (j=0; j<NCHIP; j++) {
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v=val & 1<< j;
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if (pat & (1<<(i*dist))) {
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@ -1646,9 +1627,7 @@ int testOutMux(int imod) {
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//for (k=0; k<nModX; k++) {
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val=readin(k);
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//val=bus_r(MCB_DOUT_REG_OFF+(k<<SHIFTMOD)) & 0x3ff;
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#ifdef DEBUGOUT
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printf("%d %x\n",i*dist, val);
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#endif
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for (j=0; j<NCHIP; j++) {
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v=val & 1<< j;
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if (pat & (1<<(i*dist))) {
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@ -1733,9 +1712,7 @@ int testFpgaMux(int imod) {
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//dist=2*ibit;
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if (dist==0)
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dist=1;
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#ifdef DEBUGOUT
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printf("Distance is %d\n",dist);
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#endif
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@ -1747,9 +1724,7 @@ int testFpgaMux(int imod) {
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putout("0000010000000000",ALLMOD) ;
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#ifdef DEBUGOUT
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printf("testing FPGA Mux\n");
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#endif
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for (i=0; i<4; i++) {
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k=imod;
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@ -1758,9 +1733,6 @@ int testFpgaMux(int imod) {
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//val=bus_r(MCB_DOUT_REG_OFF+(k<<SHIFTMOD)) & 0x3ff;
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#ifdef DEBUGOUT
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printf("%d %x\n",i*dist, val);
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#endif
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for (j=0; j<10; j++) {
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v=val & 1<< j;
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if (pat & (1<<(i*dist))) {
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@ -22,14 +22,11 @@
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/* Fix pattern register */
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#define FIX_PATT_REG (0x01 << 11)
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#define FIX_PATT_VAL 0xACDC2014
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/* Status register */
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#define STATUS_REG (0x02 << 11)
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#define RUN_BUSY_OFST (0)
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#define RUN_BUSY_MSK (0x00000001 << RUN_BUSY_BIT_OFST)
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#define RUN_BUSY_MSK (0x00000001 << RUN_BUSY_OFST)
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#define WAITING_FOR_TRIGGER_OFST (3)
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#define WAITING_FOR_TRIGGER_MSK (0x00000001 << WAITING_FOR_TRIGGER_OFST)
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#define DELAYBEFORE_OFST (4) //Not used in software
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@ -99,17 +96,13 @@
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#define GET_GATES_LSB_REG (0x1C << 11)
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#define GET_GATES_MSB_REG (0x1D << 11)
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/* Get Frames from Start 64 bit register (frames from start Data Streaming) ask Carlos used in software firmware_funcs.c getFramesFromStart, but not in firmware*/
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#define FRAMES_FROM_START_LSB_REG (0x22 << 11) /*Not used in firmware,used in software*/
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#define FRAMES_FROM_START_MSB_REG (0x23 << 11) /*Not used in firmware,used in software*/
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/* Get Frames from Start 64 bit register (frames from start Run Control) ask Carlos*/
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/* Get Frames from Start 64 bit register (frames from start Run Control) */
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#define FRAMES_FROM_START_PG_LSB_REG (0x24 << 11)
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#define FRAMES_FROM_START_PG_MSB_REG (0x25 << 11)
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/* Measurement Time 64 bit register (start frame time) tell Carlos it should be measurement started time? */
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#define MEASUREMENT_START_TIME_LSB_REG (0x26 << 11)
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#define MEASUREMENT_START_TIME_MSB_REG (0x27 << 11)
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/* Measurement Time 64 bit register (timestamp at a frame start until reset)*/
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#define START_FRAME_TIME_LSB_REG (0x26 << 11)
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#define START_FRAME_TIME_MSB_REG (0x27 << 11)
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/* SPI (Serial Peripheral Interface) Register */
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#define SPI_REG (0x40 << 11)
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@ -128,13 +121,77 @@
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#define HV_SERIAL_CS_OUT_MSK (0x00000001 << HV_SERIAL_CS_OUT_OFST)
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/* ADC SPI (Serial Peripheral Interface) Register */
|
||||
#define ADC_SPI_REG (0x41 << 11)
|
||||
|
||||
#define ADC_SERIAL_CLK_OUT_OFST (0)
|
||||
#define ADC_SERIAL_CLK_OUT_MSK (0x00000001 << ADC_SERIAL_CLK_OUT_OFST)
|
||||
#define ADC_SERIAL_DATA_OUT_OFST (1)
|
||||
#define ADC_SERIAL_DATA_OUT_MSK (0x00000001 << ADC_SERIAL_DATA_OUT_OFST)
|
||||
#define ADC_SERIAL_CS_OUT_OFST (2)
|
||||
#define ADC_SERIAL_CS_OUT_MSK (0x0000000F << ADC_SERIAL_CS_OUT_OFST)
|
||||
|
||||
/* ADC offset Register */
|
||||
#define ADC_OFST_REG (0x42 << 11)
|
||||
|
||||
/* ADC Port Invert Register */
|
||||
#define ADC_PORT_INVERT_REG (0x43 << 11)
|
||||
|
||||
/* Receiver IP Address Register */
|
||||
#define RX_IP_REG (0x45 << 11)
|
||||
|
||||
/* UDP Port */
|
||||
#define UDP_PORT_REG (0x46 << 11)
|
||||
|
||||
#define UDP_PORT_RX_OFST (0)
|
||||
#define UDP_PORT_RX_MSK (0x0000FFFF << UDP_PORT_RX_OFST)
|
||||
#define UDP_PORT_TX_OFST (16)
|
||||
#define UDP_PORT_TX_MSK (0x0000FFFF << UDP_PORT_TX_OFST)
|
||||
|
||||
/* Receiver Mac Address 64 bit Register */
|
||||
#define RX_MAC_LSB_REG (0x47 << 11)
|
||||
#define RX_MAC_MSB_REG (0x48 << 11)
|
||||
|
||||
#define RX_MAC_LSB_OFST (0)
|
||||
#define RX_MAC_LSB_MSK (0x0000FFFF << RX_MAC_LSB_OFST)
|
||||
#define RX_MAC_MSB_OFST (0)
|
||||
#define RX_MAC_MSB_MSK (0x000000FF << RX_MAC_MSB_OFST)
|
||||
|
||||
/* Detector/ Transmitter Mac Address 64 bit Register */
|
||||
#define TX_MAC_LSB_REG (0x49 << 11)
|
||||
#define TX_MAC_MSB_REG (0x4A << 11)
|
||||
|
||||
#define TX_MAC_LSB_OFST (0)
|
||||
#define TX_MAC_LSB_MSK (0x0000FFFF << TX_MAC_LSB_OFST)
|
||||
#define TX_MAC_MSB_OFST (0)
|
||||
#define TX_MAC_MSB_MSK (0x000000FF << TX_MAC_MSB_OFST)
|
||||
|
||||
/* Detector/ Transmitter IP Address Register */
|
||||
#define TX_IP_REG (0x4B << 11)
|
||||
|
||||
/** Detector/ Transmitter IP Checksum Register */
|
||||
#define TX_IP_CHECKSUM_REG (0x4C << 11)
|
||||
|
||||
#define TX_IP_CHECKSUM_OFST (0)
|
||||
#define TX_IP_CHECKSUM_MSK (0x000000FF << TX_IP_CHECKSUM_OFST)
|
||||
|
||||
/** Configuration Register */
|
||||
#define CONFIG_REG (0x4D << 11) //Not used in software Carlos
|
||||
|
||||
#define CONFIG_OPERATION_MODE_OFST (16) //Not used in software
|
||||
#define CONFIG_OPERATION_MODE_MSK (0x00000001 << CONFIG_OPERATION_MODE_OFST) //Not used in software
|
||||
#define CONFIG_READOUT_SPEED_OFST (20) //Not used in software
|
||||
#define CONFIG_READOUT_SPEED_MSK (0x00000003 << CONFIG_READOUT_SPEED_OFST) //Not used in software
|
||||
#define CONFIG_QUARTER_SPEED_10MHZ_VAL (0x0 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK //Not used in software
|
||||
#define CONFIG_HALF_SPEED_20MHZ_VAL (0x1 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK //Not used in software
|
||||
#define CONFIG_FULL_SPEED_VAL (0x2 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK //Not used in software and firmware
|
||||
|
||||
|
||||
|
||||
|
||||
//Constants
|
||||
#define HALFSPEED_DBIT_PIPELINE 0x7f7c
|
||||
#define QUARTERSPEED_DBIT_PIPELINE 0x8981
|
||||
#define HALFSPEED_ADC_PIPELINE 0x20
|
||||
#define QUARTERSPEED_ADC_PIPELINE 0x10
|
||||
#define HALFSPEED_CONF 0x0
|
||||
#define QUARTERSPEED_CONF 0xf
|
||||
#define HALFSPEED_ADC_PHASE 65
|
||||
@ -150,22 +207,16 @@
|
||||
|
||||
//#ifdef JUNGFRAU_DHANYA
|
||||
#define POWER_ON_REG 0x5e<<11
|
||||
#define ADCREG1 0x8 //same as PLL_BANDWIDTH_REG
|
||||
#define ADCREG2 0x14
|
||||
#define ADCREG3 0x4 //same as PLL_M_COUNTER_REG
|
||||
#define ADCREG4 0x5 //same as PLL_C_COUNTER_REG
|
||||
#define ADCREG_VREFS 0x18
|
||||
#define DBIT_PIPELINE_REG 0x59<<11 //same PATTERN_N_LOOP2_REG
|
||||
#define MEM_MACHINE_FIFOS_REG 0x4f<<11 //same as CONTROL_REG
|
||||
#define CONFGAIN_REG 0x5d<<11 //same as DAQ_REG
|
||||
#define ADC_PIPELINE_REG 0x42<<11 //same as ADC_OFFSET_REG
|
||||
|
||||
//#endif
|
||||
|
||||
//#define ADC_OFFSET_REG 66<<11 //same as CONFGAIN_REG
|
||||
#define ADC_INVERSION_REG 0x43<<11
|
||||
|
||||
//ADC
|
||||
#define ADC_WRITE_REG 65<<11//0x18<<11
|
||||
|
||||
//#define ADC_SYNC_REG 66<<11//0x19<<11
|
||||
//#define HV_REG 67<<11//0x20<<11
|
||||
|
||||
@ -188,7 +239,7 @@
|
||||
|
||||
#define CONTROL_REG 79<<11//0x24<<11
|
||||
|
||||
#define CONFIG_REG 77<<11//0x26<<11
|
||||
|
||||
#define EXT_SIGNAL_REG 78<<11// 0x4E<<11
|
||||
#define FPGA_SVN_REG 0x29<<11
|
||||
|
||||
@ -204,10 +255,6 @@
|
||||
|
||||
|
||||
#define FIFO_DATA_REG_OFF 0x50<<11 ///////
|
||||
//to read back dac registers
|
||||
#define MOD_DACS1_REG 0x65<<11
|
||||
#define MOD_DACS2_REG 0x66<<11
|
||||
#define MOD_DACS3_REG 0x67<<11
|
||||
|
||||
//user entered
|
||||
|
||||
@ -260,20 +307,10 @@
|
||||
#define PLL_CNTRL_REG 81<<11//0x34<<11
|
||||
|
||||
|
||||
#ifdef NEW_GBE_INTERFACE
|
||||
#define GBE_PARAM_OUT_REG 40<<11
|
||||
#define GBE_PARAM_REG 69<<11
|
||||
#define GBE_CNTRL_REG 70<<11
|
||||
#else
|
||||
#define RX_UDP_AREG 69<<11 //rx_udpip_AReg_c : integer:= 69; *\/
|
||||
#define UDPPORTS_AREG 70<<11// udpports_AReg_c : integer:= 70; *\/
|
||||
#define RX_UDPMACL_AREG 71<<11//rx_udpmacL_AReg_c : integer:= 71; *\/
|
||||
#define RX_UDPMACH_AREG 72<<11//rx_udpmacH_AReg_c : integer:= 72; *\/
|
||||
#define DETECTORMACL_AREG 73<<11//detectormacL_AReg_c : integer:= 73; *\/
|
||||
#define DETECTORMACH_AREG 74<<11//detectormacH_AReg_c : integer:= 74; *\/
|
||||
#define DETECTORIP_AREG 75<<11//detectorip_AReg_c : integer:= 75; *\/
|
||||
#define IPCHKSUM_AREG 76<<11//ipchksum_AReg_c : integer:= 76; *\/ */
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define PATTERN_CNTRL_REG 82<<11
|
||||
|
||||
@ -1,61 +1,147 @@
|
||||
#ifndef SERVER_DEFS_H
|
||||
#define SERVER_DEFS_H
|
||||
|
||||
#include "sls_detector_defs.h"
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* Hardware Definitions */
|
||||
#define NMAXMODY 1
|
||||
#define NMAXMODX 1
|
||||
#define NMAXMOD (NMAXMODX*NMAXMODY)
|
||||
#define NCHAN (256*256)
|
||||
#define NCHIP 8
|
||||
#define NADC 0
|
||||
#define NDAC 8
|
||||
#define NCHANS (NCHAN*NCHIP*NMAXMOD)
|
||||
#define NDACS (NDAC*NMAXMOD)
|
||||
|
||||
// Hardware definitions
|
||||
#define NMAXMODY 1
|
||||
#define NMAXMODX 1
|
||||
#define NMAXMOD (NMAXMODX*NMAXMODY)
|
||||
#define NCHAN (256*256)
|
||||
#define NCHIP 8
|
||||
#define NADC 0
|
||||
#define NDAC 16
|
||||
#define NCHANS (NCHAN*NCHIP*NMAXMOD)
|
||||
#define NDACS (NDAC*NMAXMOD)
|
||||
|
||||
|
||||
/**when moench readout tested with gotthard module*/
|
||||
#define GOTTHARDNCHAN 128
|
||||
#define GOTTHARDNCHIP 10
|
||||
|
||||
|
||||
#define NTRIMBITS 6
|
||||
#define NCOUNTBITS 24
|
||||
|
||||
#define NCHIPS_PER_ADC 2
|
||||
|
||||
//#define TRIM_DR ((2**NTRIMBITS)-1)
|
||||
//#define COUNT_DR ((2**NCOUNTBITS)-1)
|
||||
#define TRIM_DR (((int)pow(2,NTRIMBITS))-1)
|
||||
#define COUNT_DR (((int)pow(2,NCOUNTBITS))-1)
|
||||
|
||||
|
||||
#define ALLMOD 0xffff
|
||||
#define ALLFIFO 0xffff
|
||||
|
||||
#define GOTTHARD_ADCSYNC_VAL 0x32214
|
||||
#define ADCSYNC_VAL 0x02111
|
||||
#define TOKEN_RESTART_DELAY 0x88000000
|
||||
#define TOKEN_RESTART_DELAY_ROI 0x1b000000
|
||||
#define TOKEN_TIMING_REV1 0x1f16
|
||||
#define TOKEN_TIMING_REV2 0x1f0f
|
||||
|
||||
#define DEFAULT_PHASE_SHIFT 0 // 120
|
||||
#define DEFAULT_PHASE_SHIFT 0 // 120
|
||||
#define DEFAULT_IP_PACKETSIZE 0x0522
|
||||
#define DEFAULT_UDP_PACKETSIZE 0x050E
|
||||
#define ADC1_IP_PACKETSIZE 256*2+14+20
|
||||
#define ADC1_UDP_PACKETSIZE 256*2+4+8+2
|
||||
|
||||
#ifdef VIRTUAL
|
||||
#define DEBUGOUT
|
||||
#endif
|
||||
|
||||
#define CLK_FREQ 156.25E+6
|
||||
#define ADC_CLK_FREQ 32E+6
|
||||
|
||||
/** DEFAULT */
|
||||
enum DACNAMES { VB_COMP, VDD_PROT, VIN_COM, VREF_PRECH, VB_PIXBUF, VB_DS, VREF_DS, VREF_COMP };
|
||||
#define DEFAULT_DAC_VALS { 1220, 3000, 1053, 1450, 750, 1000, 480, 420 };
|
||||
#define DEFAULT_NUM_FRAMES (1*1000*1000)
|
||||
#define DEFAULT_NUM_CYCLES (0)
|
||||
#define DEFAULT_EXPTIME (10*1000)
|
||||
#define DEFAULT_PERIOD (2*1000*1000)
|
||||
#define DEFAULT_DELAY (0)
|
||||
#define DEFAULT_NUM_GATES (0)
|
||||
#define DEFAULT_HIGH_VOLTAGE (0)
|
||||
#define DEFAULT_SETTINGS (DYNAMICGAIN)
|
||||
#define DEFAULT_TX_UDP_PORT (0x7e9a)
|
||||
|
||||
/* Defines in the Firmware */
|
||||
#define FIX_PATT_VAL (0xACDC2014)
|
||||
#define ADC_PORT_INVERT_VAL (0x453b2a9c)
|
||||
#define ADC_OFST_HALF_SPEED_VAL (0x20)
|
||||
#define ADC_OFST_QUARTER_SPEED_VAL (0x10)
|
||||
|
||||
/* Maybe not required for jungfrau */
|
||||
#define NTRIMBITS 6
|
||||
#define NCOUNTBITS 24
|
||||
#define NCHIPS_PER_ADC 2
|
||||
#define TRIM_DR (((int)pow(2,NTRIMBITS))-1)
|
||||
#define COUNT_DR (((int)pow(2,NCOUNTBITS))-1)
|
||||
#define ALLMOD 0xffff
|
||||
#define ALLFIFO 0xffff
|
||||
|
||||
/* LTC2620 DAC DEFINES */
|
||||
#define LTC2620_DAC_CMD_OFST (20)
|
||||
#define LTC2620_DAC_CMD_MSK (0x0000000F << LTC2620_DAC_CMD_OFST)
|
||||
#define LTC2620_DAC_ADDR_OFST (16)
|
||||
#define LTC2620_DAC_ADDR_MSK (0x0000000F << LTC2620_DAC_ADDR_OFST)
|
||||
#define LTC2620_DAC_DATA_OFST (4)
|
||||
#define LTC2620_DAC_DATA_MSK (0x00000FFF << LTC2620_DAC_DATA_OFST)
|
||||
|
||||
#define LTC2620_DAC_CMD_WRITE (0x00000000 << LTC2620_DAC_CMD_OFST)
|
||||
#define LTC2620_DAC_CMD_SET (0x00000003 << LTC2620_DAC_CMD_OFST)
|
||||
#define LTC2620_DAC_CMD_POWER_DOWN (0x00000004 << LTC2620_DAC_CMD_OFST)
|
||||
#define LTC2620_DAC_NUMBITS (24)
|
||||
|
||||
|
||||
/* MAX1932 HV DEFINES */
|
||||
#define MAX1932_HV_NUMBITS (8)
|
||||
#define MAX1932_HV_DATA_OFST (0)
|
||||
#define MAX1932_HV_DATA_MSK (0x000000FF << MAX1932_HV_DATA_OFST)
|
||||
|
||||
/* AD9257 ADC DEFINES */
|
||||
#define AD9257_ADC_NUMBITS (24)
|
||||
|
||||
#define AD9257_DEV_IND_2_REG (0x04)
|
||||
#define AD9257_CHAN_H_OFST (0)
|
||||
#define AD9257_CHAN_H_MSK (0x00000001 << AD9257_CHAN_H_OFST)
|
||||
#define AD9257_CHAN_G_OFST (1)
|
||||
#define AD9257_CHAN_G_MSK (0x00000001 << AD9257_CHAN_G_OFST)
|
||||
#define AD9257_CHAN_F_OFST (2)
|
||||
#define AD9257_CHAN_F_MSK (0x00000001 << AD9257_CHAN_F_OFST)
|
||||
#define AD9257_CHAN_E_OFST (3)
|
||||
#define AD9257_CHAN_E_MSK (0x00000001 << AD9257_CHAN_E_OFST)
|
||||
|
||||
#define AD9257_DEV_IND_1_REG (0x05)
|
||||
#define AD9257_CHAN_D_OFST (0)
|
||||
#define AD9257_CHAN_D_MSK (0x00000001 << AD9257_CHAN_D_OFST)
|
||||
#define AD9257_CHAN_C_OFST (1)
|
||||
#define AD9257_CHAN_C_MSK (0x00000001 << AD9257_CHAN_C_OFST)
|
||||
#define AD9257_CHAN_B_OFST (2)
|
||||
#define AD9257_CHAN_B_MSK (0x00000001 << AD9257_CHAN_B_OFST)
|
||||
#define AD9257_CHAN_A_OFST (3)
|
||||
#define AD9257_CHAN_A_MSK (0x00000001 << AD9257_CHAN_A_OFST)
|
||||
#define AD9257_CLK_CH_DCO_OFST (4)
|
||||
#define AD9257_CLK_CH_DCO_MSK (0x00000001 << AD9257_CLK_CH_DCO_OFST)
|
||||
#define AD9257_CLK_CH_IFCO_OFST (5)
|
||||
#define AD9257_CLK_CH_IFCO_MSK (0x00000001 << AD9257_CLK_CH_IFCO_OFST)
|
||||
|
||||
#define AD9257_POWER_MODE_REG (0x08)
|
||||
#define AD9257_POWER_INTERNAL_OFST (0)
|
||||
#define AD9257_POWER_INTERNAL_MSK (0x00000003 << AD9257_POWER_INTERNAL_OFST)
|
||||
#define AD9257_INT_RESET_VAL (0x3)
|
||||
#define AD9257_INT_CHIP_RUN_VAL (0x0)
|
||||
#define AD9257_POWER_EXTERNAL_OFST (5)
|
||||
#define AD9257_POWER_EXTERNAL_MSK (0x00000001 << AD9257_POWER_EXTERNAL_OFST)
|
||||
#define AD9257_EXT_FULL_POWER_VAL (0x0)
|
||||
#define AD9257_EXT_STANDBY_VAL (0x1)
|
||||
|
||||
#define AD9257_OUT_MODE_REG (0x14)
|
||||
#define AD9257_OUT_FORMAT_OFST (0)
|
||||
#define AD9257_OUT_FORMAT_MSK (0x00000001 << AD9257_OUT_FORMAT_OFST)
|
||||
#define AD9257_OUT_BINARY_OFST_VAL (0)
|
||||
#define AD9257_OUT_TWOS_COMPL_VAL (1)
|
||||
#define AD9257_OUT_LVDS_OPT_OFST (6)
|
||||
#define AD9257_OUT_LVDS_OPT_MSK (0x00000001 << AD9257_OUT_LVDS_OPT_OFST)
|
||||
#define AD9257_OUT_LVDS_ANSI_VAL (0)
|
||||
#define AD9257_OUT_LVDS_IEEE_VAL (1)
|
||||
|
||||
#define AD9257_OUT_PHASE_REG (0x16)
|
||||
#define AD9257_OUT_CLK_OFST (0)
|
||||
#define AD9257_OUT_CLK_MSK (0x0000000F << AD9257_OUT_CLK_OFST)
|
||||
#define AD9257_OUT_CLK_60_VAL (0x1)
|
||||
#define AD9257_IN_CLK_OFST (4)
|
||||
#define AD9257_IN_CLK_MSK (0x00000007 << AD9257_IN_CLK_OFST)
|
||||
#define AD9257_IN_CLK_0_VAL (0x0)
|
||||
|
||||
#define AD9257_VREF_REG (0x18)
|
||||
#define AD9257_VREF_OFST (0)
|
||||
#define AD9257_VREF_MSK (0x00000003 << AD9257_VREF_OFST)
|
||||
#define AD9257_VREF_1_33_VAL (0x2)
|
||||
|
||||
#define AD9257_TEST_MODE_REG (0x0D)
|
||||
#define AD9257_OUT_TEST_OFST (0)
|
||||
#define AD9257_OUT_TEST_MSK (0x0000000F << AD9257_OUT_TEST_OFST)
|
||||
#define AD9257_NONE_VAL (0x0)
|
||||
#define AD9257_MIXED_BIT_FREQ_VAL (0xC)
|
||||
#define AD9257_TEST_RESET_SHORT_GEN (4)
|
||||
#define AD9257_TEST_RESET_LONG_GEN (5)
|
||||
#define AD9257_USER_IN_MODE_OFST (6)
|
||||
#define AD9257_USER_IN_MODE_MSK (0x00000003 << AD9257_USER_IN_MODE_OFST)
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
@ -910,13 +910,13 @@ int set_dac(int file_des) {
|
||||
if (val>4 || val<0)
|
||||
printf("Cannot set ADC VPP to %d\n",val);
|
||||
else {
|
||||
writeADC(0x18,val);
|
||||
setAdc(0x18,val);
|
||||
adcvpp=val;
|
||||
}
|
||||
retval=adcvpp;;
|
||||
|
||||
} else if (ind==HV_NEW )
|
||||
retval=initHighVoltage(val,0);
|
||||
retval=setHighVoltage(val,0);
|
||||
else
|
||||
printf("**********No dac with index %d\n",ind);
|
||||
}
|
||||
@ -2411,13 +2411,12 @@ int configure_mac(int file_des) {
|
||||
|
||||
if(ret==OK)
|
||||
configureMAC(ipad,imacadd,idetectormacadd,detipad,digitalTestBit,udpport);
|
||||
retval=getAdcConfigured();
|
||||
}
|
||||
#endif
|
||||
if (ret==FAIL)
|
||||
printf("configuring MAC of mod %d failed\n", imod);
|
||||
else
|
||||
printf("Configuremac successful of mod %d and adc %d\n",imod,retval);
|
||||
printf("Configuremac successful of mod %d\n",imod);
|
||||
|
||||
if (differentClients)
|
||||
ret=FORCE_UPDATE;
|
||||
@ -2960,7 +2959,7 @@ int write_adc_register(int file_des) {
|
||||
|
||||
|
||||
if(ret!=FAIL){
|
||||
ret=writeADC(addr,val);
|
||||
ret=setAdc(addr,val);
|
||||
if (ret==OK)
|
||||
retval=val;
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user