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cleaning up of servers

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This commit is contained in:
Dhanya Maliakal
2017-06-02 19:29:34 +02:00
parent 2465eafff0
commit 0254ff0281
8 changed files with 1083 additions and 820 deletions
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3
slsDetectorSoftware/commonFiles/sls_detector_defs.h
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@ -19,9 +19,6 @@
/** header length for data :gotthard*/ /** header length for data :gotthard*/
#define HEADERLENGTH 12 #define HEADERLENGTH 12
#define DEFAULT_SUBFRAME_EXPOSURE_VAL 2621440 /** default value for sub frame value 2.6ms*/
#define MAX_SUBFRAME_EXPOSURE_VAL_IN_10NS 0x1FFFFFFF /** 29 bit register for max subframe exposure value */
/** maximum rois */ /** maximum rois */
#define MAX_ROIS 100 #define MAX_ROIS 100

1075
slsDetectorSoftware/eigerDetectorServer/slsDetectorFunctionList.c
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File diff suppressed because it is too large Load Diff

92
slsDetectorSoftware/eigerDetectorServer/slsDetectorServer_defs.h
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@ -8,46 +8,76 @@
#ifndef SLSDETECTORSERVER_DEFS_H_ #ifndef SLSDETECTORSERVER_DEFS_H_
#define SLSDETECTORSERVER_DEFS_H_ #define SLSDETECTORSERVER_DEFS_H_
//#include "sls_detector_defs.h" #include "sls_detector_defs.h"
#include <stdint.h> #include <stdint.h>
#define GOODBYE -200 #define GOODBYE (-200)
#define REQUIRED_FIRMWARE_VERSION (16)
#define FEB_PORT 43210 /* Enums */
#define BEB_PORT 43212 enum CLK_SPEED_INDEX {FULL_SPEED, HALF_SPEED, QUARTER_SPEED};
enum DAC_INDEX {SVP,VTR,VRF,VRS,SVN,VTGSTV,VCMP_LL,VCMP_LR,CAL,VCMP_RL,RXB_RB,RXB_LB,VCMP_RR,VCP,VCN,VIS,VTHRESHOLD};
#define REQUIRED_FIRMWARE_VERSION 16 #define DEFAULT_DAC_VALS[16] { \
0, /* SvP */ \
#define FIRMWAREREV 0xcaba //temporary should be in firmware 2480, /* Vtr */ \
3300, /* Vrf */ \
1400, /* Vrs */ \
4000, /* SvN */ \
2556, /* Vtgstv */ \
1000, /* Vcmp_ll */ \
1000, /* Vcmp_lr */ \
4000, /* cal */ \
1000, /* Vcmp_rl */ \
1100, /* rxb_rb */ \
1100, /* rxb_lb */ \
1000, /* Vcmp_rr */ \
1000, /* Vcp */ \
2000, /* Vcn */ \
1550 /* Vis */ \
};
enum ADC_INDEX {TEMP_FPGAEXT, TEMP_10GE, TEMP_DCDC, TEMP_SODL, TEMP_SODR, TEMP_FPGA, TEMP_FPGAFEBL, TEMP_FPGAFEBR};
enum NETWORK_PARA_INDEX {TXN_LEFT, TXN_RIGHT, TXN_FRAME,FLOWCTRL_10G};
#define NCHAN 256*256 /* Hardware Definitions */
#define NCHIP 4 #define NMAXMOD (1)
#define NDAC 16 #define NMOD (1)
#define NADC 0 #define NCHAN (256 * 256)
#define NGAIN 0 #define NCHIP (4)
#define NOFFSET 0 #define NADC (0)
#define NDAC (16)
#define NMAXMODX 1 #define NGAIN (0)
#define NMAXMODY 1 #define NOFFSET (0)
#define NMAXMOD NMAXMODX*NMAXMODY
#define NCHANS NCHAN*NCHIP*NMAXMOD
#define NDACS NDAC*NMAXMOD
#define DYNAMIC_RANGE 16 #define TEN_GIGA_BUFFER_SIZE (4112)
#define ONE_GIGA_BUFFER_SIZE (1040)
#define TEN_GIGA_CONSTANT (4)
#define ONE_GIGA_CONSTANT (16)
#define NORMAL_HIGHVOLTAGE_INPUTPORT "/sys/class/hwmon/hwmon5/device/in0_input"
#define NORMAL_HIGHVOLTAGE_OUTPUTPORT "/sys/class/hwmon/hwmon5/device/out0_output"
#define SPECIAL9M_HIGHVOLTAGE_PORT "/dev/ttyS1"
#define SPECIAL9M_HIGHVOLTAGE_BUFFERSIZE (16)
/** Default Parameters */
#define DEFAULT_MOD_INDEX (0)
#define DEFAULT_NUM_FRAMES (1)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_EXPTIME (1E9) //ns
#define DEFAULT_PERIOD (1E9) //ns
#define DEFAULT_DELAY (0)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_SETTINGS (DYNAMICGAIN)
#define DEFAULT_SUBFRAME_EXPOSURE_VAL (2621440) // 2.6ms
#define DEFAULT_DYNAMIC_RANGE (16)
#define DEFAULT_READOUT_FLAG (NONPARALLEL)
#define DEFAULT_CLK_SPEED (HALF_SPEED)
#define DEFAULT_IO_DELAY (650)
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_PHOTON_ENERGY (-1)
#define DEFAULT_RATE_CORRECTION (0)
enum detDacIndex{SVP,VTR,VRF,VRS,SVN,VTGSTV,VCMP_LL,VCMP_LR,CAL,VCMP_RL,RXB_RB,RXB_LB,VCMP_RR,VCP,VCN,VIS,VTHRESHOLD}; #define MAX_SUBFRAME_EXPOSURE_VAL_IN_10NS (0x1FFFFFFF) /** 29 bit register for max subframe exposure value */
enum detAdcIndex{TEMP_FPGAEXT, TEMP_10GE, TEMP_DCDC, TEMP_SODL, TEMP_SODR, TEMP_FPGA, TEMP_FPGAFEBL, TEMP_FPGAFEBR};
enum detNetworkParameter{TXN_LEFT, TXN_RIGHT, TXN_FRAME,FLOWCTRL_10G};
#define NORMAL_HIGHVOLTAGE_INPUTPORT "/sys/class/hwmon/hwmon5/device/in0_input"
#define NORMAL_HIGHVOLTAGE_OUTPUTPORT "/sys/class/hwmon/hwmon5/device/out0_output"
#define SPECIAL9M_HIGHVOLTAGE_PORT "/dev/ttyS1"
#define SPECIAL9M_HIGHVOLTAGE_BUFFERSIZE 16

3
slsDetectorSoftware/jungfrauDetectorServerNewStructure/RegisterDefs.h
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@ -84,6 +84,9 @@
#define GET_PERIOD_LSB_REG (0x18 << 11) #define GET_PERIOD_LSB_REG (0x18 << 11)
#define GET_PERIOD_MSB_REG (0x19 << 11) #define GET_PERIOD_MSB_REG (0x19 << 11)
/** Get Temperature Carlos, incorrectl as get gates */
#define GET_TEMPERATURE_TMP112_REG (0x1c << 11) // in 10ths of millidegrees of TMP112
/* Get Frames from Start 64 bit register (frames from start Run Control) */ /* Get Frames from Start 64 bit register (frames from start Run Control) */
#define FRAMES_FROM_START_PG_LSB_REG (0x24 << 11) #define FRAMES_FROM_START_PG_LSB_REG (0x24 << 11)
#define FRAMES_FROM_START_PG_MSB_REG (0x25 << 11) #define FRAMES_FROM_START_PG_MSB_REG (0x25 << 11)

655
slsDetectorSoftware/jungfrauDetectorServerNewStructure/slsDetectorFunctionList.c
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@ -6,6 +6,7 @@
#include "slsDetectorFunctionList.h" #include "slsDetectorFunctionList.h"
#include "gitInfoJungfrau.h" #include "gitInfoJungfrau.h"
#include "slsDetectorServer_defs.h" //also include RegisterDefs.h
@ -208,7 +209,6 @@ u_int16_t getHardwareSerialNumber() {
return ((bus_r(MOD_SERIAL_NUM_REG) & HARDWARE_SERIAL_NUM_MSK) >> HARDWARE_SERIAL_NUM_OFST); return ((bus_r(MOD_SERIAL_NUM_REG) & HARDWARE_SERIAL_NUM_MSK) >> HARDWARE_SERIAL_NUM_OFST);
} }
u_int32_t getDetectorNumber(){ u_int32_t getDetectorNumber(){
return bus_r(MOD_SERIAL_NUM_REG); return bus_r(MOD_SERIAL_NUM_REG);
} }
@ -396,7 +396,7 @@ void FPGATouchFlash(){
/* set up detector*/ /* set up detector */
void allocateDetectorStructureMemory(){ void allocateDetectorStructureMemory(){
printf("This Server is for 1 Jungfrau module (500k)\n"); printf("This Server is for 1 Jungfrau module (500k)\n");
@ -475,7 +475,7 @@ void setupDetector() {
setTimer(FRAME_PERIOD, DEFAULT_PERIOD); setTimer(FRAME_PERIOD, DEFAULT_PERIOD);
setTimer(DELAY_AFTER_TRIGGER, DEFAULT_DELAY); setTimer(DELAY_AFTER_TRIGGER, DEFAULT_DELAY);
/*setSpeed(CLOCK_DIVIDER, HALF_SPEED); depends if all the previous stuff works*/ /*setSpeed(CLOCK_DIVIDER, HALF_SPEED); depends if all the previous stuff works*/
setTiming(AUTO_TIMING); setTiming(DEFAULT_TIMING_MODE);
setHighVoltage(DEFAULT_HIGH_VOLTAGE); setHighVoltage(DEFAULT_HIGH_VOLTAGE);
} }
@ -576,6 +576,7 @@ int setDynamicRange(int dr){
/* parameters - readout */ /* parameters - readout */
int setSpeed(enum speedVariable arg, int val) { int setSpeed(enum speedVariable arg, int val) {
if (arg != CLOCK_DIVIDER) if (arg != CLOCK_DIVIDER)
@ -587,7 +588,7 @@ int setSpeed(enum speedVariable arg, int val) {
switch(val){ switch(val){
// stop state machine if running // stop state machine if running
if(((bus_r(STATUS_REG) & RUN_BUSY_MSK) >> RUN_BUSY_OFST)) if(runBusy())
stopStateMachine(); stopStateMachine();
// todo in firmware, for now setting half speed // todo in firmware, for now setting half speed
@ -767,7 +768,7 @@ int setModule(sls_detector_module myMod){
//set dac values //set dac values
for(i=0;i<myMod.ndac;i++) for(i=0;i<myMod.ndac;i++)
setDAC((enum detDacIndex)i,myMod.dacs[i],myMod.module,0,retval); setDAC((enum DAC_INDEX)i,myMod.dacs[i],myMod.module,0,retval);
return thisSettings; return thisSettings;
} }
@ -779,7 +780,7 @@ int getModule(sls_detector_module *myMod){
//dacs //dacs
for(i=0;i<NDAC;i++) for(i=0;i<NDAC;i++)
setDAC((enum detDacIndex)i,-1,-1,0,retval); setDAC((enum DAC_INDEX)i,-1,-1,0,retval);
//copy to local copy as well //copy to local copy as well
if (detectorModules) if (detectorModules)
@ -862,66 +863,227 @@ enum detectorSettings getSettings(){
/* parameters - dac, adc, hv */ /* parameters - dac, adc, hv */
void setDAC(enum detDacIndex ind, int val, int imod, int mV, int retval[]){
if(ind == VTHRESHOLD){ void serializeToSPI(u_int32_t addr, u_int32_t val, u_int16_t csmask, int numbitstosend, u_int16_t clkmask, u_int16_t digoutmask, int digofset) {
int ret[5];
setDAC(VCMP_LL,val,imod,mV,retval);
ret[0] = retval[mV];
setDAC(VCMP_LR,val,imod,mV,retval);
ret[1] = retval[mV];
setDAC(VCMP_RL,val,imod,mV,retval);
ret[2] = retval[mV];
setDAC(VCMP_RR,val,imod,mV,retval);
ret[3] = retval[mV];
setDAC(VCP,val,imod,mV,retval);
ret[4] = retval[mV];
if((ret[0]== ret[1])&&
(ret[1]==ret[2])&&
(ret[2]==ret[3]) &&
(ret[3]==ret[4]))
cprintf(GREEN,"vthreshold match\n");
else{
retval[0] = -1;retval[1] = -1;
cprintf(RED,"vthreshold mismatch 0:%d 1:%d 2:%d 3:%d\n",
ret[0],ret[1],ret[2],ret[3]);
}
return;
}
char iname[10];
if(((int)ind>=0)&&((int)ind<NDAC))
strcpy(iname,dac_names[(int)ind]);
else{
printf("dac value outside range:%d\n",(int)ind);
strcpy(iname,dac_names[0]);
}
#ifdef VERBOSE #ifdef VERBOSE
if(val >= 0) if (numbitstosend == 16)
printf("Setting dac %d: %s to %d ",ind, iname,val); printf("Writing to ADC SPI Register: 0x%04x\n",val);
else else
printf("Getting dac %d: %s ",ind, iname); printf("Writing to SPI Register: 0x%08x\n", val);
if(mV)
printf("in mV\n");
else
printf("in dac units\n");
#endif #endif
if(val >= 0)
Feb_Control_SetDAC(iname,val,mV);
int k;
Feb_Control_GetDAC(iname, &k,0);
retval[0] = k;
Feb_Control_GetDAC(iname,&k,1);
retval[1] = k;
(detectorModules)->dacs[ind] = retval[0]; u_int16_t valw;
// start point
valw = 0xffff; /**todo testwith old board 0xff for adc_spi */ // old board compatibility (not using specific bits)
bus_w16 (addr, valw);
// chip sel bar down
valw &= ~csmask; /* todo with test: done a bit different, not with previous value */
bus_w16 (addr, valw);
{
int i = 0;
for (i = 0; i < numbitstosend; ++i) {
// clk down
valw &= ~clkmask;
bus_w16 (addr, valw);
// write data (i)
valw = ((valw & ~digoutmask) + // unset bit
(((val >> (numbitstosend - 1 - i)) & 0x1) << digofset)); // each bit from val starting from msb
bus_w16 (addr, valw);
// clk up
valw |= clkmask ;
bus_w16 (addr, valw);
}
}
// chip sel bar up
valw |= csmask; /* todo with test: not done for spi */
bus_w16 (addr, valw);
//clk down
valw &= ~clkmask;
bus_w16 (addr, valw);
// stop point = start point of course
valw = 0xffff; /**todo testwith old board 0xff for adc_spi */ // old board compatibility (not using specific bits)
bus_w16 (addr, valw);
printf("\n");
}
void initDac(int dacnum) {
printf("\n Initializing dac for %d to \n",dacnum);
u_int32_t codata;
int csdx = dacnum / NDAC + DAC_SERIAL_CS_OUT_OFST; // old board (16 dacs),so can be DAC_SERIAL_CS_OUT_OFST or +1
int dacchannel = 0xf; // all channels
int dacvalue = 0x6; // can be any random value (just writing to power up)
printf("Write to Input Register\n"
"Chip select bit:%d\n"
"Dac Channel:0x%x\n3"
"Dac Value:0x%x",
csdx, dacchannel, dacvalue);
codata = LTC2620_DAC_CMD_WRITE + // command to write to input register
((dacchannel << LTC2620_DAC_ADDR_OFST) & LTC2620_DAC_ADDR_MSK) + // all channels
((dacvalue << LTC2620_DAC_DATA_OFST) & LTC2620_DAC_DATA_MSK); // any random value
serializeToSPI(SPI_REG, codata, (0x1 << csdx), LTC2620_DAC_NUMBITS,
DAC_SERIAL_CLK_OUT_MSK, DAC_SERIAL_DIGITAL_OUT_MSK, DAC_SERIAL_DIGITAL_OUT_OFST);
}
void prepareADC(){
printf("Preparing ADC\n");
//power mode reset
setAdc(AD9257_POWER_MODE_REG,
(AD9257_INT_RESET_VAL << AD9257_POWER_INTERNAL_OFST) & AD9257_POWER_INTERNAL_MSK);
//power mode chip run
setAdc(AD9257_POWER_MODE_REG,
(AD9257_INT_CHIP_RUN_VAL << AD9257_POWER_INTERNAL_OFST) & AD9257_POWER_INTERNAL_MSK);
//output clock phase
setAdc(AD9257_OUT_PHASE_REG,
(AD9257_OUT_CLK_60_VAL << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK);
// lvds-iee reduced , binary offset
setAdc(AD9257_OUT_MODE_REG,
(AD9257_OUT_LVDS_IEEE_VAL << AD9257_OUT_LVDS_OPT_OFST) & AD9257_OUT_LVDS_OPT_MSK);
// all devices on chip to receive next command
setAdc(AD9257_DEV_IND_2_REG,
AD9257_CHAN_H_MSK | AD9257_CHAN_G_MSK | AD9257_CHAN_F_MSK | AD9257_CHAN_E_MSK);
setAdc(AD9257_DEV_IND_1_REG,
AD9257_CHAN_D_MSK | AD9257_CHAN_C_MSK | AD9257_CHAN_B_MSK | AD9257_CHAN_A_MSK |
AD9257_CLK_CH_DCO_MSK | AD9257_CLK_CH_IFCO_MSK);
// vref 1.33
setAdc(AD9257_VREF_REG,
(AD9257_VREF_1_33_VAL << AD9257_VREF_OFST) & AD9257_VREF_MSK);
// no test mode
setAdc(AD9257_TEST_MODE_REG,
(AD9257_NONE_VAL << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK);
#ifdef TESTADC
printf("***************************************** *******\n");
printf("******* PUTTING ADC IN TEST MODE!!!!!!!!! *******\n");
printf("***************************************** *******\n");
// mixed bit frequency test mode
setAdc(AD9257_TEST_MODE_REG,
(AD9257_MIXED_BIT_FREQ_VAL << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK);
#endif
}
void setAdc(int addr, int val) {
u_int32_t codata;
codata = val + (addr << 8);
printf("\n Setting Adc spi register. Addr: 0x%04x Value: 0x%04x\n", addr, val);
serializeToSPI(ADC_SPI_REG, codata, ADC_SERIAL_CS_OUT_MSK, AD9257_ADC_NUMBITS,
ADC_SERIAL_CLK_OUT_MSK, ADC_SERIAL_DATA_OUT_MSK, ADC_SERIAL_DATA_OUT_OFST);
}
int voltageToDac(int value){
int vmin = 0;
int vmax = 2500;
int nsteps = 4096;
if ((value < vmin) || (value > vmax)) return -1;
return (int)(((value - vmin) / (vmax - vmin)) * (nsteps - 1) + 0.5);
}
int dacToVoltage(unsigned int digital){
int vmin = 0;
int vmax = 2500;
int nsteps = 4096;
int v = vmin + (vmax - vmin) * digital / (nsteps - 1);
if((v < 0) || (v > nsteps - 1))
return -1;
return v;
}
void setDAC(enum DAC_INDEX ind, int val, int imod, int mV, int retval[]){
//if set and mv, convert to dac
if (val > 0 && mV)
val = voltageToDac(val); //gives -1 on error
if ( (val >= 0) || (val == -100)) {
u_int32_t codata;
int csdx = dacnum / NDAC + DAC_SERIAL_CS_OUT_OFST; // old board (16 dacs),so can be DAC_SERIAL_CS_OUT_OFST or +1
int dacchannel = dacnum % NDAC; // 0-8, dac channel number (also for dacnum 9-15 in old board)
printf("\n Setting of DAC %d with value %d\n",dacnum, dacvalue);
// command
if (dacvalue >= 0) {
printf("Write to Input Register and Update\n");
codata = LTC2620_DAC_CMD_SET;
} else if (dacvalue == -100) {
printf("POWER DOWN\n");
codata = LTC2620_DAC_CMD_POWER_DOWN;
}
// address
printf("Chip select bit:%d\n"
"Dac Channel:0x%x\n3"
"Dac Value:0x%x",
csdx, dacchannel, dacvalue);
codata += ((dacchannel << LTC2620_DAC_ADDR_OFST) & LTC2620_DAC_ADDR_MSK) +
((dacvalue << LTC2620_DAC_DATA_OFST) & LTC2620_DAC_DATA_MSK);
// to spi
serializeToSPI(SPI_REG, codata, (0x1 << csdx), LTC2620_DAC_NUMBITS,
DAC_SERIAL_CLK_OUT_MSK, DAC_SERIAL_DIGITAL_OUT_MSK, DAC_SERIAL_DIGITAL_OUT_OFST);
dacValues[dacnum] = dacvalue;
}
printf("\nGetting DAC %d\n",dacnum);
retval[0] = dacValues[dacnum];
retval[1] = dacToVoltage(retval[0]);
}
int getADC(enum ADC_INDEX ind, int imod){
char tempnames[2][20]={"VRs/FPGAs Temperature", "ADCs/ASICs Temperature"};
printf("Getting Temperature for %s\n",tempnames[ind]);
u_int32_t addr = GET_TEMPERATURE_TMP112_REG;
u_int32_t val = 0;
int retval = -1;
for(int i = 0; i < 10; i++) {
switch((int)ind){
case TEMP_FPGA:
val = (val<<1) + ((bus_r(GET_TEMPERATURE_TMP112_REG) & (2)) >> 1);
break;
case TEMPADC:
val= (val<<1) + (bus_r(GET_TEMPERATURE_TMP112_REG) & (1));
break;
}
}
/** or just read it */
retval = ((int)tempVal) / 4.0;
printf("Temperature %s: %.2f°C\n",tempnames[ind],retval);
return retval;
} }
@ -952,158 +1114,34 @@ int setHighVoltage(int val){
} }
int getADC(enum detAdcIndex ind, int imod){
int retval = -1;
char tempnames[6][20]={"FPGA EXT", "10GE","DCDC", "SODL", "SODR", "FPGA"};
char cstore[255];
switch(ind){
case TEMP_FPGA:
retval=getBebFPGATemp()*1000;
break; /* parameters - timing, extsig */
case TEMP_FPGAFEBL:
retval=Feb_Control_GetLeftFPGATemp();
break; enum externalCommunicationMode setTiming( enum externalCommunicationMode arg){
case TEMP_FPGAFEBR:
retval=Feb_Control_GetRightFPGATemp(); if(arg != GET_EXTERNAL_COMMUNICATION_MODE){
break; switch((int)arg){
case TEMP_FPGAEXT: case AUTO_TIMING: bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) & ~EXT_SIGNAL_MSK); break;
case TEMP_10GE: case TRIGGER_EXPOSURE: bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) | EXT_SIGNAL_MSK); break;
case TEMP_DCDC:
case TEMP_SODL:
case TEMP_SODR:
sprintf(cstore,"more /sys/class/hwmon/hwmon%d/device/temp1_input",ind);
FILE* sysFile = popen(cstore, "r");
fgets(cstore, sizeof(cstore), sysFile);
pclose(sysFile);
sscanf(cstore,"%d",&retval);
break;
default: default:
return -1; cprintf(RED,"Unknown timing mode %d\n", arg);
} return GET_EXTERNAL_COMMUNICATION_MODE;
printf("Temperature %s: %f°C\n",tempnames[ind],(double)retval/1000.00);
return retval;
}
int startStateMachine(){
printf("*******Starting State Machine*******\n");
cleanFifos();
//start state machine
bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_START_ACQ_MSK);
bus_w(CONTROL_REG, bus_r(CONTROL_REG) & ~CONTROL_START_ACQ_MSK);
printf("Status Register: %08x\n",bus_r(STATUS_REG));
}
int stopStateMachine(){
cprintf(BG_RED,"*******Stopping State Machine*******\n");
//stop state machine
bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_STOP_ACQ_MSK);
usleep(100);
bus_w(CONTROL_REG, bus_r(CONTROL_REG) & ~CONTROL_STOP_ACQ_MSK);
printf("Status Register: %08x\n",bus_r(STATUS_REG));
return OK;
}
enum runStatus getRunStatus(){
#ifdef VERBOSE
printf("Getting status\n");
#endif
enum runStatus s;
u_int32_t retval = bus_r(STATUS_REG);
printf("Status Register: %08x\n",retval);
//running
if(((retval & RUN_BUSY_MSK) >> RUN_BUSY_OFST)) {
if ((retval & WAITING_FOR_TRIGGER_MSK) >> WAITING_FOR_TRIGGER_OFST) {
printf("-----------------------------------WAITING-----------------------------------\n");
s=WAITING;
}
else{
printf("-----------------------------------RUNNING-----------------------------------\n");
s=RUNNING;
} }
} }
if (bus_r(EXT_SIGNAL_REG) == EXT_SIGNAL_MSK)
//not running return TRIGGER_EXPOSURE;
else { return AUTO_TIMING;
if ((retval & STOPPED_MSK) >> STOPPED_OFST) {
printf("-----------------------------------STOPPED--------------------------\n");
s=STOPPED;
} else if ((retval & RUNMACHINE_BUSY_MSK) >> RUNMACHINE_BUSY_OFST) {
printf("-----------------------------------READ MACHINE BUSY--------------------------\n");
s=TRANSMITTING;
} else if (!retval) {
printf("-----------------------------------IDLE--------------------------------------\n");
s=IDLE;
} else {
printf("-----------------------------------Unknown status %08x--------------------------------------\n", retval);
s=ERROR;
}
}
return s;
}
void readFrame(int *ret, char *mess){
if(!Feb_Control_WaitForFinishedFlag(5000))
cprintf(RED,"Error: Waiting for finished flag\n");
cprintf(GREEN,"Acquisition finished***\n");
if(eiger_storeinmem){
printf("requesting images after storing in memory\n");
if(startReadOut() == FAIL){
strcpy(mess,"Could not execute read image requests\n");
*ret = (int)FAIL;
return;
}
}
//wait for detector to send
Beb_EndofDataSend(send_to_ten_gig);
printf("*****Done Waiting...\n");
*ret = (int)FINISHED;
strcpy(mess,"acquisition successfully finished\n");
} }
/* configure mac */
long int calcChecksum(int sourceip, int destip) { long int calcChecksum(int sourceip, int destip) {
@ -1190,6 +1228,71 @@ int configureMAC(uint32_t destip, uint64_t destmac, uint64_t sourcemac, uint32_t
/* jungfrau specific - pll, flashing fpga */
void resetPLL() {
// reset PLL Reconfiguration and PLL
bus_w(PLL_CONTROL_REG, bus_r(PLL_CONTROL_REG) | PLL_CTRL_RECONFIG_RST_MSK | PLL_CTRL_RST_MSK);
usleep(100);
bus_w(PLL_CONTROL_REG, bus_r(PLL_CONTROL_REG) & ~PLL_CTRL_RECONFIG_RST_MSK & ~PLL_CTRL_RST_MSK);
}
u_int32_t setPllReconfigReg(u_int32_t reg, u_int32_t val) {
// set parameter
bus_w(PLL_PARAM_REG, val);
// set address
bus_w(PLL_CONTROL_REG, (reg << PLL_CTRL_ADDR_OFST) & PLL_CTRL_ADDR_MSK);
usleep(10*1000);
//write parameter
bus_w(PLL_CONTROL_REG, bus_r(PLL_CONTROL_REG) | PLL_CTRL_WR_PARAMETER_MSK);
bus_w(PLL_CONTROL_REG, bus_r(PLL_CONTROL_REG) & ~PLL_CTRL_WR_PARAMETER_MSK);
usleep(10*1000);
return val;
}
void configurePll() {
u_int32_t val;
int32_t phase=0, inv=0;
printf("phase in %d\n", clkPhase[1]);
if (clkPhase[1]>0) {
inv=0;
phase=clkPhase[1];
} else {
inv=1;
phase=-1*clkPhase[1];
}
printf("phase out %d %08x\n", phase, phase);
if (inv) {
val = ((phase << PLL_SHIFT_NUM_SHIFTS_OFST) & PLL_SHIFT_NUM_SHIFTS_MSK) | PLL_SHIFT_CNT_SLCT_C1_VAL | PLL_SHIFT_UP_DOWN_NEG_VAL;
printf("**************** phase word %08x\n", val);
setPllReconfigReg(PLL_PHASE_SHIFT_REG, val);
} else {
val = ((phase << PLL_SHIFT_NUM_SHIFTS_OFST) & PLL_SHIFT_NUM_SHIFTS_MSK) | PLL_SHIFT_CNT_SLCT_C0_VAL | PLL_SHIFT_UP_DOWN_NEG_VAL;
printf("**************** phase word %08x\n", val);
setPllReconfigReg(PLL_PHASE_SHIFT_REG, val);
printf("**************** phase word %08x\n", val);
val = ((phase << PLL_SHIFT_NUM_SHIFTS_OFST) & PLL_SHIFT_NUM_SHIFTS_MSK) | PLL_SHIFT_CNT_SLCT_C2_VAL;
setPllReconfigReg(PLL_PHASE_SHIFT_REG, val);
}
usleep(10000);
}
void eraseFlash(){ void eraseFlash(){
#ifdef VERY_VERBOSE #ifdef VERY_VERBOSE
printf("\nErasing Flash\n"); printf("\nErasing Flash\n");
@ -1290,17 +1393,124 @@ int writeFPGAProgram(char* fpgasrc, size_t fsize, FILE* filefp){
/* aquisition */
int startStateMachine(){
printf("*******Starting State Machine*******\n");
cleanFifos();
int calculateDataBytes(){ //start state machine
if(send_to_ten_gig) bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_START_ACQ_MSK);
return setDynamicRange(-1)*16*TEN_GIGA_BUFFER_SIZE; bus_w(CONTROL_REG, bus_r(CONTROL_REG) & ~CONTROL_START_ACQ_MSK);
else
return setDynamicRange(-1)*16*ONE_GIGA_BUFFER_SIZE; printf("Status Register: %08x\n",bus_r(STATUS_REG));
} }
int stopStateMachine(){
cprintf(BG_RED,"*******Stopping State Machine*******\n");
//stop state machine
bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_STOP_ACQ_MSK);
usleep(100);
bus_w(CONTROL_REG, bus_r(CONTROL_REG) & ~CONTROL_STOP_ACQ_MSK);
printf("Status Register: %08x\n",bus_r(STATUS_REG));
return OK;
}
enum runStatus getRunStatus(){
#ifdef VERBOSE
printf("Getting status\n");
#endif
enum runStatus s;
u_int32_t retval = bus_r(STATUS_REG);
printf("Status Register: %08x\n",retval);
//running
if(((retval & RUN_BUSY_MSK) >> RUN_BUSY_OFST)) {
if ((retval & WAITING_FOR_TRIGGER_MSK) >> WAITING_FOR_TRIGGER_OFST) {
printf("-----------------------------------WAITING-----------------------------------\n");
s=WAITING;
}
else{
printf("-----------------------------------RUNNING-----------------------------------\n");
s=RUNNING;
}
}
//not running
else {
if ((retval & STOPPED_MSK) >> STOPPED_OFST) {
printf("-----------------------------------STOPPED--------------------------\n");
s=STOPPED;
} else if ((retval & RUNMACHINE_BUSY_MSK) >> RUNMACHINE_BUSY_OFST) {
printf("-----------------------------------READ MACHINE BUSY--------------------------\n");
s=TRANSMITTING;
} else if (!retval) {
printf("-----------------------------------IDLE--------------------------------------\n");
s=IDLE;
} else {
printf("-----------------------------------Unknown status %08x--------------------------------------\n", retval);
s=ERROR;
}
}
return s;
}
void readFrame(int *ret, char *mess){
// wait for status to be done
while(runBusy()){
usleep(500);
}
// frames left to give status
int64_t retval = getTimeLeft(FRAME_NUMBER) + 1;
if ( retval > 0) {
*ret = (int)FAIL;
sprintf(mess,"no data and run stopped: %lld frames left\n",retval);
cprintf(RED,"%s\n",mess);
} else {
*ret = (int)FINISHED;
sprintf(mess,"acquisition successfully finished\n");
printf("%s",mess);
}
}
u_int32_t runBusy(void) {
u_int32_t s = ((bus_r(STATUS_REG) & RUN_BUSY_MSK) >> RUN_BUSY_OFST);
#ifdef VERBOSE
printf("Status Register: %08x\n", s);
#endif
return s;
}
/* common */
int copyModule(sls_detector_module *destMod, sls_detector_module *srcMod){ int copyModule(sls_detector_module *destMod, sls_detector_module *srcMod){
int ichip, idac, ichan, iadc; int ichip, idac, ichan, iadc;
@ -1378,36 +1588,22 @@ int copyModule(sls_detector_module *destMod, sls_detector_module *srcMod){
} }
int calculateDataBytes(){
return DATA_BYTES;
}
int getTotalNumberOfChannels(){return getNumberOfChannelsPerModule();} int getTotalNumberOfChannels(){return getNumberOfChannelsPerModule() * getTotalNumberOfModules;}
int getTotalNumberOfChips(){return NCHIP;} int getTotalNumberOfChips(){return getNumberOfChipsPerModule * getTotalNumberOfModules;}
int getTotalNumberOfModules(){return 1;} int getTotalNumberOfModules(){return NMOD;}
int getNumberOfChannelsPerChip(){return NCHAN;}
int getNumberOfChannelsPerModule(){return getNumberOfChannelsPerChip() * getTotalNumberOfChips();} int getNumberOfChannelsPerModule(){return getNumberOfChannelsPerChip() * getTotalNumberOfChips();}
int getNumberOfChipsPerModule(){return NCHIP;} int getNumberOfChipsPerModule(){return NCHIP;}
int getNumberOfDACsPerModule(){return NDAC;} int getNumberOfDACsPerModule(){return NDAC;}
int getNumberOfADCsPerModule(){return NADC;} int getNumberOfADCsPerModule(){return NADC;}
int getNumberOfGainsPerModule(){return NGAIN;} int getNumberOfChannelsPerChip(){return NCHAN;}
int getNumberOfOffsetsPerModule(){return NOFFSET;}
/* sync */
enum externalCommunicationMode setTiming( enum externalCommunicationMode arg){
if(arg != GET_EXTERNAL_COMMUNICATION_MODE){
switch((int)arg){
case AUTO_TIMING: bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) & ~EXT_SIGNAL_MSK); break;
case TRIGGER_EXPOSURE: bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) | EXT_SIGNAL_MSK); break;
default:
cprintf(RED,"Unknown timing mode %d\n", arg);
return GET_EXTERNAL_COMMUNICATION_MODE;
}
}
if (bus_r(EXT_SIGNAL_REG) == EXT_SIGNAL_MSK)
return TRIGGER_EXPOSURE;
return AUTO_TIMING;
}
enum masterFlags setMaster(enum masterFlags arg){ enum masterFlags setMaster(enum masterFlags arg){
return NO_MASTER; return NO_MASTER;
@ -1417,4 +1613,9 @@ enum synchronizationMode setSynchronization(enum synchronizationMode arg){
return NO_SYNCHRONIZATION; return NO_SYNCHRONIZATION;
} }
//#endif //#endif

22
slsDetectorSoftware/jungfrauDetectorServerNewStructure/slsDetectorServer_defs.h
View File

@ -2,7 +2,7 @@
#define SLSDETECTORSERVER_DEFS_H #define SLSDETECTORSERVER_DEFS_H
#include "sls_detector_defs.h" //default dynamicgain in settings #include "sls_detector_defs.h" //default dynamicgain in settings
#include "registers_m.h" #include "RegisterDefs.h"
#include <stdint.h> #include <stdint.h>
@ -10,7 +10,7 @@
#define GOODBYE (-200) #define GOODBYE (-200)
#define CTRL_SRVR_INIT_TIME_US (300 * 1000) #define CTRL_SRVR_INIT_TIME_US (300 * 1000)
//#define REQUIRED_FIRMWARE_VERSION 16 //#define REQUIRED_FIRMWARE_VERSION 16
//#define FIRMWAREREV 0xcaba //temporary should be in firmware
/* Struct Definitions */ /* Struct Definitions */
typedef struct ip_header_struct { typedef struct ip_header_struct {
@ -27,9 +27,9 @@ typedef struct ip_header_struct {
} ip_header; } ip_header;
/* Enums */ /* Enums */
enum clkspeed {FULL_SPEED, HALF_SPEED, QUARTER_SPEED}; enum CLK_SPEED_INDEX {FULL_SPEED, HALF_SPEED, QUARTER_SPEED};
enum ADC_INDEX {TEMP_FPGA, TEMP_ADC}; enum ADC_INDEX {TEMP_FPGA, TEMP_ADC};
enum DAC_INDEX { VB_COMP, VDD_PROT, VIN_COM, VREF_PRECH, VB_PIXBUF, VB_DS, VREF_DS, VREF_COMP }; enum DAC_INDEX {VB_COMP, VDD_PROT, VIN_COM, VREF_PRECH, VB_PIXBUF, VB_DS, VREF_DS, VREF_COMP };
#define DEFAULT_DAC_VALS { 1220, /* VB_COMP */ \ #define DEFAULT_DAC_VALS { 1220, /* VB_COMP */ \
3000, /* VDD_PROT */ \ 3000, /* VDD_PROT */ \
1053, /* VIN_COM */ \ 1053, /* VIN_COM */ \
@ -52,20 +52,15 @@ enum DAC_INDEX { VB_COMP, VDD_PROT, VIN_COM, VREF_PRECH, VB_PIXBUF, VB_DS, VR
/* Hardware Definitions */ /* Hardware Definitions */
#define NMAXMODY (1) #define NMAXMOD (1)
#define NMAXMODX (1) #define NMOD (1)
#define NMAXMOD (NMAXMODX * NMAXMODY)
#define NMODY (1)
#define NMODX (1)
#define NMOD (NMODX * NMODY)
#define NCHAN (256 * 256) #define NCHAN (256 * 256)
#define NCHIP (8) #define NCHIP (8)
#define NADC (0) #define NADC (0)
#define NDAC (8) #define NDAC (8)
#define NCHANS (NCHAN * NCHIP * NMAXMOD)
#define NDACS (NDAC * NMAXMOD)
#define DYNAMIC_RANGE (16) #define DYNAMIC_RANGE (16)
#define DATA_BYTES (NMAXMOD * NCHIP * NCHAN * 2) #define NUM_BITS_PER_PIXEL (DYNAMIC_RANGE / 8)
#define DATA_BYTES (NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
#define IP_PACKETSIZE (0x2052) #define IP_PACKETSIZE (0x2052)
#define CLK_RUN (40) /* MHz */ #define CLK_RUN (40) /* MHz */
#define CLK_SYNC (20) /* MHz */ #define CLK_SYNC (20) /* MHz */
@ -78,6 +73,7 @@ enum DAC_INDEX { VB_COMP, VDD_PROT, VIN_COM, VREF_PRECH, VB_PIXBUF, VB_DS, VR
#define DEFAULT_PERIOD (2*1000*1000) //ns #define DEFAULT_PERIOD (2*1000*1000) //ns
#define DEFAULT_DELAY (0) #define DEFAULT_DELAY (0)
#define DEFAULT_HIGH_VOLTAGE (0) #define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_SETTINGS (DYNAMICGAIN) #define DEFAULT_SETTINGS (DYNAMICGAIN)
#define DEFAULT_TX_UDP_PORT (0x7e9a) #define DEFAULT_TX_UDP_PORT (0x7e9a)

33
slsDetectorSoftware/slsDetectorServer/slsDetectorFunctionList.h
View File

@ -97,12 +97,17 @@ int setROI(int n, ROI arg[], int *retvalsize, int *ret);
int setSpeed(enum speedVariable arg, int val); int setSpeed(enum speedVariable arg, int val);
#if defined(EIGERD) || defined(MYTHEND) #if defined(EIGERD) || defined(MYTHEND)
enum readOutFlags setReadOutFlags(enum readOutFlags val); enum readOutFlags setReadOutFlags(enum readOutFlags val);
#endif
#ifdef MYTHEND
int executeTrimming(enum trimMode mode, int par1, int par2, int imod); int executeTrimming(enum trimMode mode, int par1, int par2, int imod);
#endif #endif
// parameters - timer // parameters - timer
int64_t setTimer(enum timerIndex ind, int64_t val); int64_t setTimer(enum timerIndex ind, int64_t val);
#ifndef EIGERD
int64_t getTimeLeft(enum timerIndex ind); int64_t getTimeLeft(enum timerIndex ind);
#endif
// parameters - channel, chip, module, settings // parameters - channel, chip, module, settings
#ifdef MYTHEND #ifdef MYTHEND
@ -128,12 +133,22 @@ int setThresholdEnergy(int ev, int imod);
#endif #endif
// parameters - dac, adc, hv // parameters - dac, adc, hv
void setDAC(enum detDacIndex ind, int val, int imod, int mV, int retval[]); #ifdef JUNGFRAUD
int getADC(enum detAdcIndex ind, int imod); void serializeToSPI(u_int32_t addr, u_int32_t val, u_int16_t csmask, int numbitstosend, u_int16_t clkmask, u_int16_t digoutmask, int digofset);
void initDac(int dacnum);
void prepareADC();
void setAdc(int addr, int val);
int voltageToDac(int value);
int dacToVoltage(unsigned int digital);
#endif
void setDAC(enum DAC_INDEX ind, int val, int imod, int mV, int retval[]);
int getADC(enum ADC_INDEX ind, int imod);
#ifndef MYTHEND #ifndef MYTHEND
int setHighVoltage(int val); int setHighVoltage(int val);
#endif #endif
// parameters - timing, extsig // parameters - timing, extsig
#ifdef MYTHEND #ifdef MYTHEND
enum externalSignalFlag getExtSignal(int signalindex); enum externalSignalFlag getExtSignal(int signalindex);
@ -159,7 +174,10 @@ int resetCounterBlock(int startACQ);
int calibratePedestal(int frames); int calibratePedestal(int frames);
#elif JUNGFRAUD #elif JUNGFRAUD
// jungfrau specific - flashing fpga // jungfrau specific - pll, flashing firmware
void resetPLL();
u_int32_t setPllReconfigReg(u_int32_t reg, u_int32_t val);
void configurePll();
void eraseFlash(); void eraseFlash();
int startWritingFPGAprogram(FILE** filefp); int startWritingFPGAprogram(FILE** filefp);
int stopWritingFPGAprogram(FILE* filefp); int stopWritingFPGAprogram(FILE* filefp);
@ -183,7 +201,7 @@ int setAllTrimbits(int val);
int getAllTrimbits(); int getAllTrimbits();
int getBebFPGATemp(); int getBebFPGATemp();
int activate(int enable); int activate(int enable);
int setNetworkParameter(enum detNetworkParameter mode, int value); int setNetworkParameter(enum NETWORK_PARA_INDEX mode, int value);
#endif #endif
@ -195,9 +213,14 @@ int startReceiver(int d);
#endif #endif
int startStateMachine(); int startStateMachine();
int stopStateMachine(); int stopStateMachine();
#ifndef JUNGFRAUD
int startReadOut(); int startReadOut();
#endif
enum runStatus getRunStatus(); enum runStatus getRunStatus();
void readFrame(int *ret, char *mess); void readFrame(int *ret, char *mess);
#ifdef JUNGFRAUD
u_int32_t runBusy(void);
#endif
//common //common
@ -206,7 +229,6 @@ int calculateDataBytes();
int getTotalNumberOfChannels(); int getTotalNumberOfChannels();
int getTotalNumberOfChips(); int getTotalNumberOfChips();
int getTotalNumberOfModules(); int getTotalNumberOfModules();
int getNumberOfChannelsPerChip();
int getNumberOfChannelsPerModule(); int getNumberOfChannelsPerModule();
int getNumberOfChipsPerModule(); int getNumberOfChipsPerModule();
int getNumberOfDACsPerModule(); int getNumberOfDACsPerModule();
@ -215,6 +237,7 @@ int getNumberOfADCsPerModule();
int getNumberOfGainsPerModule(); int getNumberOfGainsPerModule();
int getNumberOfOffsetsPerModule(); int getNumberOfOffsetsPerModule();
#endif #endif
int getNumberOfChannelsPerChip();
// sync // sync
enum masterFlags setMaster(enum masterFlags arg); enum masterFlags setMaster(enum masterFlags arg);

20
slsDetectorSoftware/slsDetectorServer/slsDetectorServer_funcs.c
View File

@ -1210,6 +1210,7 @@ int set_dac(int file_des) {
retval[0] = setIODelay(val,imod); retval[0] = setIODelay(val,imod);
else{ else{
setDAC(idac,val,imod,mV,retval); setDAC(idac,val,imod,mV,retval);
#ifdef EIGERD
if(val != -1) { if(val != -1) {
//changing dac changes settings to undefined //changing dac changes settings to undefined
switch(idac){ switch(idac){
@ -1226,6 +1227,7 @@ int set_dac(int file_des) {
break; break;
} }
} }
#endif
} }
} }
@ -1344,10 +1346,12 @@ int get_adc(int file_des) {
iadc = TEMP_FPGAFEBR; iadc = TEMP_FPGAFEBR;
break; break;
#endif #endif
#ifdef GOTTHARDD #if defined(GOTTHARD) || defined(JUNGFRAUD)
case TEMPERATURE_FPGA: case TEMPERATURE_FPGA:
iadc = TEMP_FPGA;
break; break;
case TEMPERATURE_ADC: case TEMPERATURE_ADC:
iadc = TEMP_ADC;
break; break;
#endif #endif
default: default:
@ -2751,15 +2755,24 @@ int set_dynamic_range(int file_des) {
ret=FAIL; ret=FAIL;
sprintf(mess,"Detector locked by %s\n",lastClientIP); sprintf(mess,"Detector locked by %s\n",lastClientIP);
} else { } else {
#ifdef EIGERD
switch(dr){ switch(dr){
#ifdef EIGERD
case -1:case 4: case 8: case 16:case 32:break; case -1:case 4: case 8: case 16:case 32:break;
#elif JUNGFRAUD
case 16: break;
#endif
default: default:
#ifdef EIGERD
strcpy(mess,"could not set dynamic range. Must be 4,8,16 or 32.\n"); strcpy(mess,"could not set dynamic range. Must be 4,8,16 or 32.\n");
#elif JUNGFRAUD
strcpy(mess,"could not change dynamic range from 16 for this detector.\n");
#endif
ret = FAIL; ret = FAIL;
} }
#endif
} }
#ifdef EIGERD
if(ret == OK){ if(ret == OK){
int old_dr = setDynamicRange(-1); int old_dr = setDynamicRange(-1);
retval=setDynamicRange(dr); retval=setDynamicRange(dr);
@ -2783,6 +2796,7 @@ int set_dynamic_range(int file_des) {
} }
} }
} }
#endif
#endif #endif
if (dr>=0 && retval!=dr) if (dr>=0 && retval!=dr)
ret=FAIL; ret=FAIL;