mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-04-24 23:30:03 +02:00
cleaning up of servers
This commit is contained in:
Dhanya Maliakal
parent
2465eafff0
commit
0254ff0281
@ -19,9 +19,6 @@
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/** header length for data :gotthard*/
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#define HEADERLENGTH 12
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#define DEFAULT_SUBFRAME_EXPOSURE_VAL 2621440 /** default value for sub frame value 2.6ms*/
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#define MAX_SUBFRAME_EXPOSURE_VAL_IN_10NS 0x1FFFFFFF /** 29 bit register for max subframe exposure value */
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/** maximum rois */
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#define MAX_ROIS 100
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File diff suppressed because it is too large
Load Diff
@ -8,46 +8,76 @@
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#ifndef SLSDETECTORSERVER_DEFS_H_
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#define SLSDETECTORSERVER_DEFS_H_
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//#include "sls_detector_defs.h"
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#include "sls_detector_defs.h"
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#include <stdint.h>
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#define GOODBYE -200
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#define GOODBYE (-200)
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#define REQUIRED_FIRMWARE_VERSION (16)
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#define FEB_PORT 43210
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#define BEB_PORT 43212
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#define REQUIRED_FIRMWARE_VERSION 16
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#define FIRMWAREREV 0xcaba //temporary should be in firmware
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/* Enums */
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enum CLK_SPEED_INDEX {FULL_SPEED, HALF_SPEED, QUARTER_SPEED};
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enum DAC_INDEX {SVP,VTR,VRF,VRS,SVN,VTGSTV,VCMP_LL,VCMP_LR,CAL,VCMP_RL,RXB_RB,RXB_LB,VCMP_RR,VCP,VCN,VIS,VTHRESHOLD};
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#define DEFAULT_DAC_VALS[16] { \
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0, /* SvP */ \
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2480, /* Vtr */ \
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3300, /* Vrf */ \
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1400, /* Vrs */ \
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4000, /* SvN */ \
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2556, /* Vtgstv */ \
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1000, /* Vcmp_ll */ \
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1000, /* Vcmp_lr */ \
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4000, /* cal */ \
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1000, /* Vcmp_rl */ \
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1100, /* rxb_rb */ \
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1100, /* rxb_lb */ \
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1000, /* Vcmp_rr */ \
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1000, /* Vcp */ \
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2000, /* Vcn */ \
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1550 /* Vis */ \
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};
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enum ADC_INDEX {TEMP_FPGAEXT, TEMP_10GE, TEMP_DCDC, TEMP_SODL, TEMP_SODR, TEMP_FPGA, TEMP_FPGAFEBL, TEMP_FPGAFEBR};
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enum NETWORK_PARA_INDEX {TXN_LEFT, TXN_RIGHT, TXN_FRAME,FLOWCTRL_10G};
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#define NCHAN 256*256
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#define NCHIP 4
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#define NDAC 16
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#define NADC 0
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#define NGAIN 0
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#define NOFFSET 0
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#define NMAXMODX 1
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#define NMAXMODY 1
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#define NMAXMOD NMAXMODX*NMAXMODY
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#define NCHANS NCHAN*NCHIP*NMAXMOD
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#define NDACS NDAC*NMAXMOD
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/* Hardware Definitions */
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#define NMAXMOD (1)
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#define NMOD (1)
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#define NCHAN (256 * 256)
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#define NCHIP (4)
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#define NADC (0)
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#define NDAC (16)
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#define NGAIN (0)
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#define NOFFSET (0)
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#define DYNAMIC_RANGE 16
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#define TEN_GIGA_BUFFER_SIZE (4112)
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#define ONE_GIGA_BUFFER_SIZE (1040)
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#define TEN_GIGA_CONSTANT (4)
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#define ONE_GIGA_CONSTANT (16)
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#define NORMAL_HIGHVOLTAGE_INPUTPORT "/sys/class/hwmon/hwmon5/device/in0_input"
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#define NORMAL_HIGHVOLTAGE_OUTPUTPORT "/sys/class/hwmon/hwmon5/device/out0_output"
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#define SPECIAL9M_HIGHVOLTAGE_PORT "/dev/ttyS1"
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#define SPECIAL9M_HIGHVOLTAGE_BUFFERSIZE (16)
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/** Default Parameters */
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#define DEFAULT_MOD_INDEX (0)
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#define DEFAULT_NUM_FRAMES (1)
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#define DEFAULT_NUM_CYCLES (1)
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#define DEFAULT_EXPTIME (1E9) //ns
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#define DEFAULT_PERIOD (1E9) //ns
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#define DEFAULT_DELAY (0)
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#define DEFAULT_HIGH_VOLTAGE (0)
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#define DEFAULT_SETTINGS (DYNAMICGAIN)
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#define DEFAULT_SUBFRAME_EXPOSURE_VAL (2621440) // 2.6ms
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#define DEFAULT_DYNAMIC_RANGE (16)
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#define DEFAULT_READOUT_FLAG (NONPARALLEL)
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#define DEFAULT_CLK_SPEED (HALF_SPEED)
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#define DEFAULT_IO_DELAY (650)
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#define DEFAULT_TIMING_MODE (AUTO_TIMING)
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#define DEFAULT_PHOTON_ENERGY (-1)
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#define DEFAULT_RATE_CORRECTION (0)
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enum detDacIndex{SVP,VTR,VRF,VRS,SVN,VTGSTV,VCMP_LL,VCMP_LR,CAL,VCMP_RL,RXB_RB,RXB_LB,VCMP_RR,VCP,VCN,VIS,VTHRESHOLD};
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enum detAdcIndex{TEMP_FPGAEXT, TEMP_10GE, TEMP_DCDC, TEMP_SODL, TEMP_SODR, TEMP_FPGA, TEMP_FPGAFEBL, TEMP_FPGAFEBR};
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enum detNetworkParameter{TXN_LEFT, TXN_RIGHT, TXN_FRAME,FLOWCTRL_10G};
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#define NORMAL_HIGHVOLTAGE_INPUTPORT "/sys/class/hwmon/hwmon5/device/in0_input"
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#define NORMAL_HIGHVOLTAGE_OUTPUTPORT "/sys/class/hwmon/hwmon5/device/out0_output"
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#define SPECIAL9M_HIGHVOLTAGE_PORT "/dev/ttyS1"
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#define SPECIAL9M_HIGHVOLTAGE_BUFFERSIZE 16
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#define MAX_SUBFRAME_EXPOSURE_VAL_IN_10NS (0x1FFFFFFF) /** 29 bit register for max subframe exposure value */
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@ -84,6 +84,9 @@
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#define GET_PERIOD_LSB_REG (0x18 << 11)
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#define GET_PERIOD_MSB_REG (0x19 << 11)
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/** Get Temperature Carlos, incorrectl as get gates */
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#define GET_TEMPERATURE_TMP112_REG (0x1c << 11) // in 10ths of millidegrees of TMP112
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/* Get Frames from Start 64 bit register (frames from start Run Control) */
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#define FRAMES_FROM_START_PG_LSB_REG (0x24 << 11)
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#define FRAMES_FROM_START_PG_MSB_REG (0x25 << 11)
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@ -6,6 +6,7 @@
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#include "slsDetectorFunctionList.h"
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#include "gitInfoJungfrau.h"
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#include "slsDetectorServer_defs.h" //also include RegisterDefs.h
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@ -208,7 +209,6 @@ u_int16_t getHardwareSerialNumber() {
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return ((bus_r(MOD_SERIAL_NUM_REG) & HARDWARE_SERIAL_NUM_MSK) >> HARDWARE_SERIAL_NUM_OFST);
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}
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u_int32_t getDetectorNumber(){
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return bus_r(MOD_SERIAL_NUM_REG);
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}
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@ -396,7 +396,7 @@ void FPGATouchFlash(){
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/* set up detector*/
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/* set up detector */
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void allocateDetectorStructureMemory(){
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printf("This Server is for 1 Jungfrau module (500k)\n");
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@ -475,7 +475,7 @@ void setupDetector() {
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setTimer(FRAME_PERIOD, DEFAULT_PERIOD);
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setTimer(DELAY_AFTER_TRIGGER, DEFAULT_DELAY);
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/*setSpeed(CLOCK_DIVIDER, HALF_SPEED); depends if all the previous stuff works*/
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setTiming(AUTO_TIMING);
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setTiming(DEFAULT_TIMING_MODE);
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setHighVoltage(DEFAULT_HIGH_VOLTAGE);
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}
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@ -576,6 +576,7 @@ int setDynamicRange(int dr){
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/* parameters - readout */
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int setSpeed(enum speedVariable arg, int val) {
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if (arg != CLOCK_DIVIDER)
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@ -587,7 +588,7 @@ int setSpeed(enum speedVariable arg, int val) {
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switch(val){
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// stop state machine if running
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if(((bus_r(STATUS_REG) & RUN_BUSY_MSK) >> RUN_BUSY_OFST))
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if(runBusy())
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stopStateMachine();
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// todo in firmware, for now setting half speed
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@ -767,7 +768,7 @@ int setModule(sls_detector_module myMod){
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//set dac values
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for(i=0;i<myMod.ndac;i++)
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setDAC((enum detDacIndex)i,myMod.dacs[i],myMod.module,0,retval);
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setDAC((enum DAC_INDEX)i,myMod.dacs[i],myMod.module,0,retval);
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return thisSettings;
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}
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@ -779,7 +780,7 @@ int getModule(sls_detector_module *myMod){
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//dacs
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for(i=0;i<NDAC;i++)
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setDAC((enum detDacIndex)i,-1,-1,0,retval);
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setDAC((enum DAC_INDEX)i,-1,-1,0,retval);
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//copy to local copy as well
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if (detectorModules)
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@ -862,66 +863,227 @@ enum detectorSettings getSettings(){
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/* parameters - dac, adc, hv */
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void setDAC(enum detDacIndex ind, int val, int imod, int mV, int retval[]){
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if(ind == VTHRESHOLD){
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int ret[5];
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setDAC(VCMP_LL,val,imod,mV,retval);
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ret[0] = retval[mV];
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setDAC(VCMP_LR,val,imod,mV,retval);
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ret[1] = retval[mV];
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setDAC(VCMP_RL,val,imod,mV,retval);
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ret[2] = retval[mV];
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setDAC(VCMP_RR,val,imod,mV,retval);
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ret[3] = retval[mV];
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setDAC(VCP,val,imod,mV,retval);
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ret[4] = retval[mV];
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if((ret[0]== ret[1])&&
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(ret[1]==ret[2])&&
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(ret[2]==ret[3]) &&
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(ret[3]==ret[4]))
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cprintf(GREEN,"vthreshold match\n");
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else{
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retval[0] = -1;retval[1] = -1;
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cprintf(RED,"vthreshold mismatch 0:%d 1:%d 2:%d 3:%d\n",
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ret[0],ret[1],ret[2],ret[3]);
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}
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return;
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}
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char iname[10];
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if(((int)ind>=0)&&((int)ind<NDAC))
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strcpy(iname,dac_names[(int)ind]);
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else{
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printf("dac value outside range:%d\n",(int)ind);
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strcpy(iname,dac_names[0]);
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}
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void serializeToSPI(u_int32_t addr, u_int32_t val, u_int16_t csmask, int numbitstosend, u_int16_t clkmask, u_int16_t digoutmask, int digofset) {
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#ifdef VERBOSE
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if(val >= 0)
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printf("Setting dac %d: %s to %d ",ind, iname,val);
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if (numbitstosend == 16)
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printf("Writing to ADC SPI Register: 0x%04x\n",val);
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else
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printf("Getting dac %d: %s ",ind, iname);
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if(mV)
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printf("in mV\n");
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else
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printf("in dac units\n");
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printf("Writing to SPI Register: 0x%08x\n", val);
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#endif
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if(val >= 0)
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Feb_Control_SetDAC(iname,val,mV);
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int k;
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Feb_Control_GetDAC(iname, &k,0);
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retval[0] = k;
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Feb_Control_GetDAC(iname,&k,1);
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retval[1] = k;
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(detectorModules)->dacs[ind] = retval[0];
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u_int16_t valw;
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// start point
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valw = 0xffff; /**todo testwith old board 0xff for adc_spi */ // old board compatibility (not using specific bits)
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bus_w16 (addr, valw);
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// chip sel bar down
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valw &= ~csmask; /* todo with test: done a bit different, not with previous value */
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bus_w16 (addr, valw);
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{
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int i = 0;
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for (i = 0; i < numbitstosend; ++i) {
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// clk down
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valw &= ~clkmask;
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bus_w16 (addr, valw);
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// write data (i)
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valw = ((valw & ~digoutmask) + // unset bit
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(((val >> (numbitstosend - 1 - i)) & 0x1) << digofset)); // each bit from val starting from msb
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bus_w16 (addr, valw);
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// clk up
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valw |= clkmask ;
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bus_w16 (addr, valw);
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}
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}
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// chip sel bar up
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valw |= csmask; /* todo with test: not done for spi */
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bus_w16 (addr, valw);
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//clk down
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valw &= ~clkmask;
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bus_w16 (addr, valw);
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// stop point = start point of course
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valw = 0xffff; /**todo testwith old board 0xff for adc_spi */ // old board compatibility (not using specific bits)
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bus_w16 (addr, valw);
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printf("\n");
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}
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void initDac(int dacnum) {
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printf("\n Initializing dac for %d to \n",dacnum);
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u_int32_t codata;
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int csdx = dacnum / NDAC + DAC_SERIAL_CS_OUT_OFST; // old board (16 dacs),so can be DAC_SERIAL_CS_OUT_OFST or +1
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int dacchannel = 0xf; // all channels
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int dacvalue = 0x6; // can be any random value (just writing to power up)
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printf("Write to Input Register\n"
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"Chip select bit:%d\n"
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"Dac Channel:0x%x\n3"
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"Dac Value:0x%x",
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csdx, dacchannel, dacvalue);
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codata = LTC2620_DAC_CMD_WRITE + // command to write to input register
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((dacchannel << LTC2620_DAC_ADDR_OFST) & LTC2620_DAC_ADDR_MSK) + // all channels
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((dacvalue << LTC2620_DAC_DATA_OFST) & LTC2620_DAC_DATA_MSK); // any random value
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serializeToSPI(SPI_REG, codata, (0x1 << csdx), LTC2620_DAC_NUMBITS,
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DAC_SERIAL_CLK_OUT_MSK, DAC_SERIAL_DIGITAL_OUT_MSK, DAC_SERIAL_DIGITAL_OUT_OFST);
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}
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void prepareADC(){
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printf("Preparing ADC\n");
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//power mode reset
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setAdc(AD9257_POWER_MODE_REG,
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(AD9257_INT_RESET_VAL << AD9257_POWER_INTERNAL_OFST) & AD9257_POWER_INTERNAL_MSK);
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//power mode chip run
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setAdc(AD9257_POWER_MODE_REG,
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(AD9257_INT_CHIP_RUN_VAL << AD9257_POWER_INTERNAL_OFST) & AD9257_POWER_INTERNAL_MSK);
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//output clock phase
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setAdc(AD9257_OUT_PHASE_REG,
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(AD9257_OUT_CLK_60_VAL << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK);
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// lvds-iee reduced , binary offset
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setAdc(AD9257_OUT_MODE_REG,
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(AD9257_OUT_LVDS_IEEE_VAL << AD9257_OUT_LVDS_OPT_OFST) & AD9257_OUT_LVDS_OPT_MSK);
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// all devices on chip to receive next command
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setAdc(AD9257_DEV_IND_2_REG,
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AD9257_CHAN_H_MSK | AD9257_CHAN_G_MSK | AD9257_CHAN_F_MSK | AD9257_CHAN_E_MSK);
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setAdc(AD9257_DEV_IND_1_REG,
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AD9257_CHAN_D_MSK | AD9257_CHAN_C_MSK | AD9257_CHAN_B_MSK | AD9257_CHAN_A_MSK |
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AD9257_CLK_CH_DCO_MSK | AD9257_CLK_CH_IFCO_MSK);
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// vref 1.33
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setAdc(AD9257_VREF_REG,
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(AD9257_VREF_1_33_VAL << AD9257_VREF_OFST) & AD9257_VREF_MSK);
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// no test mode
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setAdc(AD9257_TEST_MODE_REG,
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(AD9257_NONE_VAL << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK);
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#ifdef TESTADC
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printf("***************************************** *******\n");
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printf("******* PUTTING ADC IN TEST MODE!!!!!!!!! *******\n");
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printf("***************************************** *******\n");
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// mixed bit frequency test mode
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setAdc(AD9257_TEST_MODE_REG,
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(AD9257_MIXED_BIT_FREQ_VAL << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK);
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#endif
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}
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void setAdc(int addr, int val) {
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u_int32_t codata;
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codata = val + (addr << 8);
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printf("\n Setting Adc spi register. Addr: 0x%04x Value: 0x%04x\n", addr, val);
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serializeToSPI(ADC_SPI_REG, codata, ADC_SERIAL_CS_OUT_MSK, AD9257_ADC_NUMBITS,
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ADC_SERIAL_CLK_OUT_MSK, ADC_SERIAL_DATA_OUT_MSK, ADC_SERIAL_DATA_OUT_OFST);
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}
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int voltageToDac(int value){
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int vmin = 0;
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int vmax = 2500;
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int nsteps = 4096;
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if ((value < vmin) || (value > vmax)) return -1;
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return (int)(((value - vmin) / (vmax - vmin)) * (nsteps - 1) + 0.5);
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}
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int dacToVoltage(unsigned int digital){
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int vmin = 0;
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int vmax = 2500;
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int nsteps = 4096;
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int v = vmin + (vmax - vmin) * digital / (nsteps - 1);
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if((v < 0) || (v > nsteps - 1))
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return -1;
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return v;
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}
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void setDAC(enum DAC_INDEX ind, int val, int imod, int mV, int retval[]){
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//if set and mv, convert to dac
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if (val > 0 && mV)
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val = voltageToDac(val); //gives -1 on error
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||||
if ( (val >= 0) || (val == -100)) {
|
||||
u_int32_t codata;
|
||||
int csdx = dacnum / NDAC + DAC_SERIAL_CS_OUT_OFST; // old board (16 dacs),so can be DAC_SERIAL_CS_OUT_OFST or +1
|
||||
int dacchannel = dacnum % NDAC; // 0-8, dac channel number (also for dacnum 9-15 in old board)
|
||||
|
||||
printf("\n Setting of DAC %d with value %d\n",dacnum, dacvalue);
|
||||
// command
|
||||
if (dacvalue >= 0) {
|
||||
printf("Write to Input Register and Update\n");
|
||||
codata = LTC2620_DAC_CMD_SET;
|
||||
|
||||
} else if (dacvalue == -100) {
|
||||
printf("POWER DOWN\n");
|
||||
codata = LTC2620_DAC_CMD_POWER_DOWN;
|
||||
}
|
||||
// address
|
||||
printf("Chip select bit:%d\n"
|
||||
"Dac Channel:0x%x\n3"
|
||||
"Dac Value:0x%x",
|
||||
csdx, dacchannel, dacvalue);
|
||||
codata += ((dacchannel << LTC2620_DAC_ADDR_OFST) & LTC2620_DAC_ADDR_MSK) +
|
||||
((dacvalue << LTC2620_DAC_DATA_OFST) & LTC2620_DAC_DATA_MSK);
|
||||
// to spi
|
||||
serializeToSPI(SPI_REG, codata, (0x1 << csdx), LTC2620_DAC_NUMBITS,
|
||||
DAC_SERIAL_CLK_OUT_MSK, DAC_SERIAL_DIGITAL_OUT_MSK, DAC_SERIAL_DIGITAL_OUT_OFST);
|
||||
|
||||
dacValues[dacnum] = dacvalue;
|
||||
}
|
||||
|
||||
printf("\nGetting DAC %d\n",dacnum);
|
||||
retval[0] = dacValues[dacnum];
|
||||
retval[1] = dacToVoltage(retval[0]);
|
||||
}
|
||||
|
||||
|
||||
int getADC(enum ADC_INDEX ind, int imod){
|
||||
|
||||
char tempnames[2][20]={"VRs/FPGAs Temperature", "ADCs/ASICs Temperature"};
|
||||
printf("Getting Temperature for %s\n",tempnames[ind]);
|
||||
u_int32_t addr = GET_TEMPERATURE_TMP112_REG;
|
||||
u_int32_t val = 0;
|
||||
int retval = -1;
|
||||
|
||||
for(int i = 0; i < 10; i++) {
|
||||
switch((int)ind){
|
||||
|
||||
case TEMP_FPGA:
|
||||
val = (val<<1) + ((bus_r(GET_TEMPERATURE_TMP112_REG) & (2)) >> 1);
|
||||
break;
|
||||
case TEMPADC:
|
||||
val= (val<<1) + (bus_r(GET_TEMPERATURE_TMP112_REG) & (1));
|
||||
break;
|
||||
}
|
||||
}
|
||||
/** or just read it */
|
||||
retval = ((int)tempVal) / 4.0;
|
||||
|
||||
printf("Temperature %s: %.2f°C\n",tempnames[ind],retval);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
|
||||
@ -952,158 +1114,34 @@ int setHighVoltage(int val){
|
||||
}
|
||||
|
||||
|
||||
int getADC(enum detAdcIndex ind, int imod){
|
||||
int retval = -1;
|
||||
char tempnames[6][20]={"FPGA EXT", "10GE","DCDC", "SODL", "SODR", "FPGA"};
|
||||
char cstore[255];
|
||||
|
||||
switch(ind){
|
||||
case TEMP_FPGA:
|
||||
retval=getBebFPGATemp()*1000;
|
||||
break;
|
||||
case TEMP_FPGAFEBL:
|
||||
retval=Feb_Control_GetLeftFPGATemp();
|
||||
break;
|
||||
case TEMP_FPGAFEBR:
|
||||
retval=Feb_Control_GetRightFPGATemp();
|
||||
break;
|
||||
case TEMP_FPGAEXT:
|
||||
case TEMP_10GE:
|
||||
case TEMP_DCDC:
|
||||
case TEMP_SODL:
|
||||
case TEMP_SODR:
|
||||
sprintf(cstore,"more /sys/class/hwmon/hwmon%d/device/temp1_input",ind);
|
||||
FILE* sysFile = popen(cstore, "r");
|
||||
fgets(cstore, sizeof(cstore), sysFile);
|
||||
pclose(sysFile);
|
||||
sscanf(cstore,"%d",&retval);
|
||||
break;
|
||||
|
||||
|
||||
|
||||
/* parameters - timing, extsig */
|
||||
|
||||
|
||||
enum externalCommunicationMode setTiming( enum externalCommunicationMode arg){
|
||||
|
||||
if(arg != GET_EXTERNAL_COMMUNICATION_MODE){
|
||||
switch((int)arg){
|
||||
case AUTO_TIMING: bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) & ~EXT_SIGNAL_MSK); break;
|
||||
case TRIGGER_EXPOSURE: bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) | EXT_SIGNAL_MSK); break;
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
|
||||
printf("Temperature %s: %f°C\n",tempnames[ind],(double)retval/1000.00);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
int startStateMachine(){
|
||||
printf("*******Starting State Machine*******\n");
|
||||
|
||||
cleanFifos();
|
||||
|
||||
//start state machine
|
||||
bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_START_ACQ_MSK);
|
||||
bus_w(CONTROL_REG, bus_r(CONTROL_REG) & ~CONTROL_START_ACQ_MSK);
|
||||
|
||||
printf("Status Register: %08x\n",bus_r(STATUS_REG));
|
||||
}
|
||||
|
||||
|
||||
int stopStateMachine(){
|
||||
cprintf(BG_RED,"*******Stopping State Machine*******\n");
|
||||
|
||||
//stop state machine
|
||||
bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_STOP_ACQ_MSK);
|
||||
usleep(100);
|
||||
bus_w(CONTROL_REG, bus_r(CONTROL_REG) & ~CONTROL_STOP_ACQ_MSK);
|
||||
|
||||
printf("Status Register: %08x\n",bus_r(STATUS_REG));
|
||||
return OK;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
enum runStatus getRunStatus(){
|
||||
#ifdef VERBOSE
|
||||
printf("Getting status\n");
|
||||
#endif
|
||||
|
||||
enum runStatus s;
|
||||
u_int32_t retval = bus_r(STATUS_REG);
|
||||
printf("Status Register: %08x\n",retval);
|
||||
|
||||
//running
|
||||
if(((retval & RUN_BUSY_MSK) >> RUN_BUSY_OFST)) {
|
||||
if ((retval & WAITING_FOR_TRIGGER_MSK) >> WAITING_FOR_TRIGGER_OFST) {
|
||||
printf("-----------------------------------WAITING-----------------------------------\n");
|
||||
s=WAITING;
|
||||
}
|
||||
else{
|
||||
printf("-----------------------------------RUNNING-----------------------------------\n");
|
||||
s=RUNNING;
|
||||
cprintf(RED,"Unknown timing mode %d\n", arg);
|
||||
return GET_EXTERNAL_COMMUNICATION_MODE;
|
||||
}
|
||||
}
|
||||
|
||||
//not running
|
||||
else {
|
||||
if ((retval & STOPPED_MSK) >> STOPPED_OFST) {
|
||||
printf("-----------------------------------STOPPED--------------------------\n");
|
||||
s=STOPPED;
|
||||
} else if ((retval & RUNMACHINE_BUSY_MSK) >> RUNMACHINE_BUSY_OFST) {
|
||||
printf("-----------------------------------READ MACHINE BUSY--------------------------\n");
|
||||
s=TRANSMITTING;
|
||||
} else if (!retval) {
|
||||
printf("-----------------------------------IDLE--------------------------------------\n");
|
||||
s=IDLE;
|
||||
} else {
|
||||
printf("-----------------------------------Unknown status %08x--------------------------------------\n", retval);
|
||||
s=ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return s;
|
||||
}
|
||||
|
||||
|
||||
|
||||
void readFrame(int *ret, char *mess){
|
||||
if(!Feb_Control_WaitForFinishedFlag(5000))
|
||||
cprintf(RED,"Error: Waiting for finished flag\n");
|
||||
cprintf(GREEN,"Acquisition finished***\n");
|
||||
|
||||
if(eiger_storeinmem){
|
||||
printf("requesting images after storing in memory\n");
|
||||
if(startReadOut() == FAIL){
|
||||
strcpy(mess,"Could not execute read image requests\n");
|
||||
*ret = (int)FAIL;
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
//wait for detector to send
|
||||
Beb_EndofDataSend(send_to_ten_gig);
|
||||
|
||||
|
||||
printf("*****Done Waiting...\n");
|
||||
*ret = (int)FINISHED;
|
||||
strcpy(mess,"acquisition successfully finished\n");
|
||||
if (bus_r(EXT_SIGNAL_REG) == EXT_SIGNAL_MSK)
|
||||
return TRIGGER_EXPOSURE;
|
||||
return AUTO_TIMING;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* configure mac */
|
||||
|
||||
|
||||
long int calcChecksum(int sourceip, int destip) {
|
||||
@ -1190,6 +1228,71 @@ int configureMAC(uint32_t destip, uint64_t destmac, uint64_t sourcemac, uint32_t
|
||||
|
||||
|
||||
|
||||
|
||||
/* jungfrau specific - pll, flashing fpga */
|
||||
|
||||
|
||||
|
||||
void resetPLL() {
|
||||
// reset PLL Reconfiguration and PLL
|
||||
bus_w(PLL_CONTROL_REG, bus_r(PLL_CONTROL_REG) | PLL_CTRL_RECONFIG_RST_MSK | PLL_CTRL_RST_MSK);
|
||||
usleep(100);
|
||||
bus_w(PLL_CONTROL_REG, bus_r(PLL_CONTROL_REG) & ~PLL_CTRL_RECONFIG_RST_MSK & ~PLL_CTRL_RST_MSK);
|
||||
}
|
||||
|
||||
|
||||
u_int32_t setPllReconfigReg(u_int32_t reg, u_int32_t val) {
|
||||
|
||||
// set parameter
|
||||
bus_w(PLL_PARAM_REG, val);
|
||||
|
||||
// set address
|
||||
bus_w(PLL_CONTROL_REG, (reg << PLL_CTRL_ADDR_OFST) & PLL_CTRL_ADDR_MSK);
|
||||
usleep(10*1000);
|
||||
|
||||
//write parameter
|
||||
bus_w(PLL_CONTROL_REG, bus_r(PLL_CONTROL_REG) | PLL_CTRL_WR_PARAMETER_MSK);
|
||||
bus_w(PLL_CONTROL_REG, bus_r(PLL_CONTROL_REG) & ~PLL_CTRL_WR_PARAMETER_MSK);
|
||||
usleep(10*1000);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
void configurePll() {
|
||||
u_int32_t val;
|
||||
int32_t phase=0, inv=0;
|
||||
|
||||
printf("phase in %d\n", clkPhase[1]);
|
||||
if (clkPhase[1]>0) {
|
||||
inv=0;
|
||||
phase=clkPhase[1];
|
||||
} else {
|
||||
inv=1;
|
||||
phase=-1*clkPhase[1];
|
||||
}
|
||||
printf("phase out %d %08x\n", phase, phase);
|
||||
|
||||
if (inv) {
|
||||
val = ((phase << PLL_SHIFT_NUM_SHIFTS_OFST) & PLL_SHIFT_NUM_SHIFTS_MSK) | PLL_SHIFT_CNT_SLCT_C1_VAL | PLL_SHIFT_UP_DOWN_NEG_VAL;
|
||||
printf("**************** phase word %08x\n", val);
|
||||
setPllReconfigReg(PLL_PHASE_SHIFT_REG, val);
|
||||
} else {
|
||||
val = ((phase << PLL_SHIFT_NUM_SHIFTS_OFST) & PLL_SHIFT_NUM_SHIFTS_MSK) | PLL_SHIFT_CNT_SLCT_C0_VAL | PLL_SHIFT_UP_DOWN_NEG_VAL;
|
||||
printf("**************** phase word %08x\n", val);
|
||||
setPllReconfigReg(PLL_PHASE_SHIFT_REG, val);
|
||||
|
||||
printf("**************** phase word %08x\n", val);
|
||||
val = ((phase << PLL_SHIFT_NUM_SHIFTS_OFST) & PLL_SHIFT_NUM_SHIFTS_MSK) | PLL_SHIFT_CNT_SLCT_C2_VAL;
|
||||
setPllReconfigReg(PLL_PHASE_SHIFT_REG, val);
|
||||
}
|
||||
usleep(10000);
|
||||
}
|
||||
|
||||
|
||||
|
||||
void eraseFlash(){
|
||||
#ifdef VERY_VERBOSE
|
||||
printf("\nErasing Flash\n");
|
||||
@ -1290,17 +1393,124 @@ int writeFPGAProgram(char* fpgasrc, size_t fsize, FILE* filefp){
|
||||
|
||||
|
||||
|
||||
/* aquisition */
|
||||
|
||||
int startStateMachine(){
|
||||
printf("*******Starting State Machine*******\n");
|
||||
|
||||
cleanFifos();
|
||||
|
||||
int calculateDataBytes(){
|
||||
if(send_to_ten_gig)
|
||||
return setDynamicRange(-1)*16*TEN_GIGA_BUFFER_SIZE;
|
||||
else
|
||||
return setDynamicRange(-1)*16*ONE_GIGA_BUFFER_SIZE;
|
||||
//start state machine
|
||||
bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_START_ACQ_MSK);
|
||||
bus_w(CONTROL_REG, bus_r(CONTROL_REG) & ~CONTROL_START_ACQ_MSK);
|
||||
|
||||
printf("Status Register: %08x\n",bus_r(STATUS_REG));
|
||||
}
|
||||
|
||||
|
||||
int stopStateMachine(){
|
||||
cprintf(BG_RED,"*******Stopping State Machine*******\n");
|
||||
|
||||
//stop state machine
|
||||
bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_STOP_ACQ_MSK);
|
||||
usleep(100);
|
||||
bus_w(CONTROL_REG, bus_r(CONTROL_REG) & ~CONTROL_STOP_ACQ_MSK);
|
||||
|
||||
printf("Status Register: %08x\n",bus_r(STATUS_REG));
|
||||
return OK;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
enum runStatus getRunStatus(){
|
||||
#ifdef VERBOSE
|
||||
printf("Getting status\n");
|
||||
#endif
|
||||
|
||||
enum runStatus s;
|
||||
u_int32_t retval = bus_r(STATUS_REG);
|
||||
printf("Status Register: %08x\n",retval);
|
||||
|
||||
//running
|
||||
if(((retval & RUN_BUSY_MSK) >> RUN_BUSY_OFST)) {
|
||||
if ((retval & WAITING_FOR_TRIGGER_MSK) >> WAITING_FOR_TRIGGER_OFST) {
|
||||
printf("-----------------------------------WAITING-----------------------------------\n");
|
||||
s=WAITING;
|
||||
}
|
||||
else{
|
||||
printf("-----------------------------------RUNNING-----------------------------------\n");
|
||||
s=RUNNING;
|
||||
}
|
||||
}
|
||||
|
||||
//not running
|
||||
else {
|
||||
if ((retval & STOPPED_MSK) >> STOPPED_OFST) {
|
||||
printf("-----------------------------------STOPPED--------------------------\n");
|
||||
s=STOPPED;
|
||||
} else if ((retval & RUNMACHINE_BUSY_MSK) >> RUNMACHINE_BUSY_OFST) {
|
||||
printf("-----------------------------------READ MACHINE BUSY--------------------------\n");
|
||||
s=TRANSMITTING;
|
||||
} else if (!retval) {
|
||||
printf("-----------------------------------IDLE--------------------------------------\n");
|
||||
s=IDLE;
|
||||
} else {
|
||||
printf("-----------------------------------Unknown status %08x--------------------------------------\n", retval);
|
||||
s=ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return s;
|
||||
}
|
||||
|
||||
|
||||
|
||||
void readFrame(int *ret, char *mess){
|
||||
|
||||
// wait for status to be done
|
||||
while(runBusy()){
|
||||
usleep(500);
|
||||
}
|
||||
|
||||
// frames left to give status
|
||||
int64_t retval = getTimeLeft(FRAME_NUMBER) + 1;
|
||||
if ( retval > 0) {
|
||||
*ret = (int)FAIL;
|
||||
sprintf(mess,"no data and run stopped: %lld frames left\n",retval);
|
||||
cprintf(RED,"%s\n",mess);
|
||||
} else {
|
||||
*ret = (int)FINISHED;
|
||||
sprintf(mess,"acquisition successfully finished\n");
|
||||
printf("%s",mess);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
u_int32_t runBusy(void) {
|
||||
u_int32_t s = ((bus_r(STATUS_REG) & RUN_BUSY_MSK) >> RUN_BUSY_OFST);
|
||||
#ifdef VERBOSE
|
||||
printf("Status Register: %08x\n", s);
|
||||
#endif
|
||||
return s;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* common */
|
||||
|
||||
|
||||
|
||||
|
||||
int copyModule(sls_detector_module *destMod, sls_detector_module *srcMod){
|
||||
|
||||
int ichip, idac, ichan, iadc;
|
||||
@ -1378,36 +1588,22 @@ int copyModule(sls_detector_module *destMod, sls_detector_module *srcMod){
|
||||
}
|
||||
|
||||
|
||||
int calculateDataBytes(){
|
||||
return DATA_BYTES;
|
||||
}
|
||||
|
||||
int getTotalNumberOfChannels(){return getNumberOfChannelsPerModule();}
|
||||
int getTotalNumberOfChips(){return NCHIP;}
|
||||
int getTotalNumberOfModules(){return 1;}
|
||||
int getNumberOfChannelsPerChip(){return NCHAN;}
|
||||
int getTotalNumberOfChannels(){return getNumberOfChannelsPerModule() * getTotalNumberOfModules;}
|
||||
int getTotalNumberOfChips(){return getNumberOfChipsPerModule * getTotalNumberOfModules;}
|
||||
int getTotalNumberOfModules(){return NMOD;}
|
||||
int getNumberOfChannelsPerModule(){return getNumberOfChannelsPerChip() * getTotalNumberOfChips();}
|
||||
int getNumberOfChipsPerModule(){return NCHIP;}
|
||||
int getNumberOfDACsPerModule(){return NDAC;}
|
||||
int getNumberOfADCsPerModule(){return NADC;}
|
||||
int getNumberOfGainsPerModule(){return NGAIN;}
|
||||
int getNumberOfOffsetsPerModule(){return NOFFSET;}
|
||||
int getNumberOfChannelsPerChip(){return NCHAN;}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
enum externalCommunicationMode setTiming( enum externalCommunicationMode arg){
|
||||
if(arg != GET_EXTERNAL_COMMUNICATION_MODE){
|
||||
switch((int)arg){
|
||||
case AUTO_TIMING: bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) & ~EXT_SIGNAL_MSK); break;
|
||||
case TRIGGER_EXPOSURE: bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) | EXT_SIGNAL_MSK); break;
|
||||
default:
|
||||
cprintf(RED,"Unknown timing mode %d\n", arg);
|
||||
return GET_EXTERNAL_COMMUNICATION_MODE;
|
||||
}
|
||||
}
|
||||
if (bus_r(EXT_SIGNAL_REG) == EXT_SIGNAL_MSK)
|
||||
return TRIGGER_EXPOSURE;
|
||||
return AUTO_TIMING;
|
||||
}
|
||||
/* sync */
|
||||
|
||||
enum masterFlags setMaster(enum masterFlags arg){
|
||||
return NO_MASTER;
|
||||
@ -1417,4 +1613,9 @@ enum synchronizationMode setSynchronization(enum synchronizationMode arg){
|
||||
return NO_SYNCHRONIZATION;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//#endif
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
#define SLSDETECTORSERVER_DEFS_H
|
||||
|
||||
#include "sls_detector_defs.h" //default dynamicgain in settings
|
||||
#include "registers_m.h"
|
||||
#include "RegisterDefs.h"
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
@ -10,7 +10,7 @@
|
||||
#define GOODBYE (-200)
|
||||
#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
|
||||
//#define REQUIRED_FIRMWARE_VERSION 16
|
||||
//#define FIRMWAREREV 0xcaba //temporary should be in firmware
|
||||
|
||||
|
||||
/* Struct Definitions */
|
||||
typedef struct ip_header_struct {
|
||||
@ -27,9 +27,9 @@ typedef struct ip_header_struct {
|
||||
} ip_header;
|
||||
|
||||
/* Enums */
|
||||
enum clkspeed {FULL_SPEED, HALF_SPEED, QUARTER_SPEED};
|
||||
enum CLK_SPEED_INDEX {FULL_SPEED, HALF_SPEED, QUARTER_SPEED};
|
||||
enum ADC_INDEX {TEMP_FPGA, TEMP_ADC};
|
||||
enum DAC_INDEX { VB_COMP, VDD_PROT, VIN_COM, VREF_PRECH, VB_PIXBUF, VB_DS, VREF_DS, VREF_COMP };
|
||||
enum DAC_INDEX {VB_COMP, VDD_PROT, VIN_COM, VREF_PRECH, VB_PIXBUF, VB_DS, VREF_DS, VREF_COMP };
|
||||
#define DEFAULT_DAC_VALS { 1220, /* VB_COMP */ \
|
||||
3000, /* VDD_PROT */ \
|
||||
1053, /* VIN_COM */ \
|
||||
@ -52,20 +52,15 @@ enum DAC_INDEX { VB_COMP, VDD_PROT, VIN_COM, VREF_PRECH, VB_PIXBUF, VB_DS, VR
|
||||
|
||||
|
||||
/* Hardware Definitions */
|
||||
#define NMAXMODY (1)
|
||||
#define NMAXMODX (1)
|
||||
#define NMAXMOD (NMAXMODX * NMAXMODY)
|
||||
#define NMODY (1)
|
||||
#define NMODX (1)
|
||||
#define NMOD (NMODX * NMODY)
|
||||
#define NMAXMOD (1)
|
||||
#define NMOD (1)
|
||||
#define NCHAN (256 * 256)
|
||||
#define NCHIP (8)
|
||||
#define NADC (0)
|
||||
#define NDAC (8)
|
||||
#define NCHANS (NCHAN * NCHIP * NMAXMOD)
|
||||
#define NDACS (NDAC * NMAXMOD)
|
||||
#define DYNAMIC_RANGE (16)
|
||||
#define DATA_BYTES (NMAXMOD * NCHIP * NCHAN * 2)
|
||||
#define NUM_BITS_PER_PIXEL (DYNAMIC_RANGE / 8)
|
||||
#define DATA_BYTES (NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
|
||||
#define IP_PACKETSIZE (0x2052)
|
||||
#define CLK_RUN (40) /* MHz */
|
||||
#define CLK_SYNC (20) /* MHz */
|
||||
@ -78,6 +73,7 @@ enum DAC_INDEX { VB_COMP, VDD_PROT, VIN_COM, VREF_PRECH, VB_PIXBUF, VB_DS, VR
|
||||
#define DEFAULT_PERIOD (2*1000*1000) //ns
|
||||
#define DEFAULT_DELAY (0)
|
||||
#define DEFAULT_HIGH_VOLTAGE (0)
|
||||
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
|
||||
#define DEFAULT_SETTINGS (DYNAMICGAIN)
|
||||
#define DEFAULT_TX_UDP_PORT (0x7e9a)
|
||||
|
||||
|
||||
@ -97,12 +97,17 @@ int setROI(int n, ROI arg[], int *retvalsize, int *ret);
|
||||
int setSpeed(enum speedVariable arg, int val);
|
||||
#if defined(EIGERD) || defined(MYTHEND)
|
||||
enum readOutFlags setReadOutFlags(enum readOutFlags val);
|
||||
#endif
|
||||
#ifdef MYTHEND
|
||||
int executeTrimming(enum trimMode mode, int par1, int par2, int imod);
|
||||
#endif
|
||||
|
||||
// parameters - timer
|
||||
int64_t setTimer(enum timerIndex ind, int64_t val);
|
||||
#ifndef EIGERD
|
||||
int64_t getTimeLeft(enum timerIndex ind);
|
||||
#endif
|
||||
|
||||
|
||||
// parameters - channel, chip, module, settings
|
||||
#ifdef MYTHEND
|
||||
@ -128,12 +133,22 @@ int setThresholdEnergy(int ev, int imod);
|
||||
#endif
|
||||
|
||||
// parameters - dac, adc, hv
|
||||
void setDAC(enum detDacIndex ind, int val, int imod, int mV, int retval[]);
|
||||
int getADC(enum detAdcIndex ind, int imod);
|
||||
#ifdef JUNGFRAUD
|
||||
void serializeToSPI(u_int32_t addr, u_int32_t val, u_int16_t csmask, int numbitstosend, u_int16_t clkmask, u_int16_t digoutmask, int digofset);
|
||||
void initDac(int dacnum);
|
||||
void prepareADC();
|
||||
void setAdc(int addr, int val);
|
||||
int voltageToDac(int value);
|
||||
int dacToVoltage(unsigned int digital);
|
||||
#endif
|
||||
void setDAC(enum DAC_INDEX ind, int val, int imod, int mV, int retval[]);
|
||||
int getADC(enum ADC_INDEX ind, int imod);
|
||||
#ifndef MYTHEND
|
||||
int setHighVoltage(int val);
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
// parameters - timing, extsig
|
||||
#ifdef MYTHEND
|
||||
enum externalSignalFlag getExtSignal(int signalindex);
|
||||
@ -159,7 +174,10 @@ int resetCounterBlock(int startACQ);
|
||||
int calibratePedestal(int frames);
|
||||
|
||||
#elif JUNGFRAUD
|
||||
// jungfrau specific - flashing fpga
|
||||
// jungfrau specific - pll, flashing firmware
|
||||
void resetPLL();
|
||||
u_int32_t setPllReconfigReg(u_int32_t reg, u_int32_t val);
|
||||
void configurePll();
|
||||
void eraseFlash();
|
||||
int startWritingFPGAprogram(FILE** filefp);
|
||||
int stopWritingFPGAprogram(FILE* filefp);
|
||||
@ -183,7 +201,7 @@ int setAllTrimbits(int val);
|
||||
int getAllTrimbits();
|
||||
int getBebFPGATemp();
|
||||
int activate(int enable);
|
||||
int setNetworkParameter(enum detNetworkParameter mode, int value);
|
||||
int setNetworkParameter(enum NETWORK_PARA_INDEX mode, int value);
|
||||
#endif
|
||||
|
||||
|
||||
@ -195,9 +213,14 @@ int startReceiver(int d);
|
||||
#endif
|
||||
int startStateMachine();
|
||||
int stopStateMachine();
|
||||
#ifndef JUNGFRAUD
|
||||
int startReadOut();
|
||||
#endif
|
||||
enum runStatus getRunStatus();
|
||||
void readFrame(int *ret, char *mess);
|
||||
#ifdef JUNGFRAUD
|
||||
u_int32_t runBusy(void);
|
||||
#endif
|
||||
|
||||
|
||||
//common
|
||||
@ -206,7 +229,6 @@ int calculateDataBytes();
|
||||
int getTotalNumberOfChannels();
|
||||
int getTotalNumberOfChips();
|
||||
int getTotalNumberOfModules();
|
||||
int getNumberOfChannelsPerChip();
|
||||
int getNumberOfChannelsPerModule();
|
||||
int getNumberOfChipsPerModule();
|
||||
int getNumberOfDACsPerModule();
|
||||
@ -215,6 +237,7 @@ int getNumberOfADCsPerModule();
|
||||
int getNumberOfGainsPerModule();
|
||||
int getNumberOfOffsetsPerModule();
|
||||
#endif
|
||||
int getNumberOfChannelsPerChip();
|
||||
|
||||
// sync
|
||||
enum masterFlags setMaster(enum masterFlags arg);
|
||||
|
||||
@ -1210,6 +1210,7 @@ int set_dac(int file_des) {
|
||||
retval[0] = setIODelay(val,imod);
|
||||
else{
|
||||
setDAC(idac,val,imod,mV,retval);
|
||||
#ifdef EIGERD
|
||||
if(val != -1) {
|
||||
//changing dac changes settings to undefined
|
||||
switch(idac){
|
||||
@ -1226,6 +1227,7 @@ int set_dac(int file_des) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
@ -1344,10 +1346,12 @@ int get_adc(int file_des) {
|
||||
iadc = TEMP_FPGAFEBR;
|
||||
break;
|
||||
#endif
|
||||
#ifdef GOTTHARDD
|
||||
#if defined(GOTTHARD) || defined(JUNGFRAUD)
|
||||
case TEMPERATURE_FPGA:
|
||||
iadc = TEMP_FPGA;
|
||||
break;
|
||||
case TEMPERATURE_ADC:
|
||||
iadc = TEMP_ADC;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
@ -2751,15 +2755,24 @@ int set_dynamic_range(int file_des) {
|
||||
ret=FAIL;
|
||||
sprintf(mess,"Detector locked by %s\n",lastClientIP);
|
||||
} else {
|
||||
#ifdef EIGERD
|
||||
|
||||
switch(dr){
|
||||
#ifdef EIGERD
|
||||
case -1:case 4: case 8: case 16:case 32:break;
|
||||
#elif JUNGFRAUD
|
||||
case 16: break;
|
||||
#endif
|
||||
default:
|
||||
#ifdef EIGERD
|
||||
strcpy(mess,"could not set dynamic range. Must be 4,8,16 or 32.\n");
|
||||
#elif JUNGFRAUD
|
||||
strcpy(mess,"could not change dynamic range from 16 for this detector.\n");
|
||||
#endif
|
||||
ret = FAIL;
|
||||
}
|
||||
#endif
|
||||
|
||||
}
|
||||
#ifdef EIGERD
|
||||
if(ret == OK){
|
||||
int old_dr = setDynamicRange(-1);
|
||||
retval=setDynamicRange(dr);
|
||||
@ -2783,6 +2796,7 @@ int set_dynamic_range(int file_des) {
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
if (dr>=0 && retval!=dr)
|
||||
ret=FAIL;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user