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cleaning up of servers

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This commit is contained in:
Dhanya Maliakal
2017-06-02 19:29:34 +02:00
parent 2465eafff0
commit 0254ff0281
8 changed files with 1083 additions and 820 deletions
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1075
slsDetectorSoftware/eigerDetectorServer/slsDetectorFunctionList.c
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slsDetectorSoftware/eigerDetectorServer/slsDetectorServer_defs.h
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@ -8,46 +8,76 @@
#ifndef SLSDETECTORSERVER_DEFS_H_
#define SLSDETECTORSERVER_DEFS_H_
//#include "sls_detector_defs.h"
#include "sls_detector_defs.h"
#include <stdint.h>
#define GOODBYE -200
#define GOODBYE (-200)
#define REQUIRED_FIRMWARE_VERSION (16)
#define FEB_PORT 43210
#define BEB_PORT 43212
#define REQUIRED_FIRMWARE_VERSION 16
#define FIRMWAREREV 0xcaba //temporary should be in firmware
/* Enums */
enum CLK_SPEED_INDEX {FULL_SPEED, HALF_SPEED, QUARTER_SPEED};
enum DAC_INDEX {SVP,VTR,VRF,VRS,SVN,VTGSTV,VCMP_LL,VCMP_LR,CAL,VCMP_RL,RXB_RB,RXB_LB,VCMP_RR,VCP,VCN,VIS,VTHRESHOLD};
#define DEFAULT_DAC_VALS[16] { \
0, /* SvP */ \
2480, /* Vtr */ \
3300, /* Vrf */ \
1400, /* Vrs */ \
4000, /* SvN */ \
2556, /* Vtgstv */ \
1000, /* Vcmp_ll */ \
1000, /* Vcmp_lr */ \
4000, /* cal */ \
1000, /* Vcmp_rl */ \
1100, /* rxb_rb */ \
1100, /* rxb_lb */ \
1000, /* Vcmp_rr */ \
1000, /* Vcp */ \
2000, /* Vcn */ \
1550 /* Vis */ \
};
enum ADC_INDEX {TEMP_FPGAEXT, TEMP_10GE, TEMP_DCDC, TEMP_SODL, TEMP_SODR, TEMP_FPGA, TEMP_FPGAFEBL, TEMP_FPGAFEBR};
enum NETWORK_PARA_INDEX {TXN_LEFT, TXN_RIGHT, TXN_FRAME,FLOWCTRL_10G};
#define NCHAN 256*256
#define NCHIP 4
#define NDAC 16
#define NADC 0
#define NGAIN 0
#define NOFFSET 0
#define NMAXMODX 1
#define NMAXMODY 1
#define NMAXMOD NMAXMODX*NMAXMODY
#define NCHANS NCHAN*NCHIP*NMAXMOD
#define NDACS NDAC*NMAXMOD
/* Hardware Definitions */
#define NMAXMOD (1)
#define NMOD (1)
#define NCHAN (256 * 256)
#define NCHIP (4)
#define NADC (0)
#define NDAC (16)
#define NGAIN (0)
#define NOFFSET (0)
#define DYNAMIC_RANGE 16
#define TEN_GIGA_BUFFER_SIZE (4112)
#define ONE_GIGA_BUFFER_SIZE (1040)
#define TEN_GIGA_CONSTANT (4)
#define ONE_GIGA_CONSTANT (16)
#define NORMAL_HIGHVOLTAGE_INPUTPORT "/sys/class/hwmon/hwmon5/device/in0_input"
#define NORMAL_HIGHVOLTAGE_OUTPUTPORT "/sys/class/hwmon/hwmon5/device/out0_output"
#define SPECIAL9M_HIGHVOLTAGE_PORT "/dev/ttyS1"
#define SPECIAL9M_HIGHVOLTAGE_BUFFERSIZE (16)
/** Default Parameters */
#define DEFAULT_MOD_INDEX (0)
#define DEFAULT_NUM_FRAMES (1)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_EXPTIME (1E9) //ns
#define DEFAULT_PERIOD (1E9) //ns
#define DEFAULT_DELAY (0)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_SETTINGS (DYNAMICGAIN)
#define DEFAULT_SUBFRAME_EXPOSURE_VAL (2621440) // 2.6ms
#define DEFAULT_DYNAMIC_RANGE (16)
#define DEFAULT_READOUT_FLAG (NONPARALLEL)
#define DEFAULT_CLK_SPEED (HALF_SPEED)
#define DEFAULT_IO_DELAY (650)
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_PHOTON_ENERGY (-1)
#define DEFAULT_RATE_CORRECTION (0)
enum detDacIndex{SVP,VTR,VRF,VRS,SVN,VTGSTV,VCMP_LL,VCMP_LR,CAL,VCMP_RL,RXB_RB,RXB_LB,VCMP_RR,VCP,VCN,VIS,VTHRESHOLD};
enum detAdcIndex{TEMP_FPGAEXT, TEMP_10GE, TEMP_DCDC, TEMP_SODL, TEMP_SODR, TEMP_FPGA, TEMP_FPGAFEBL, TEMP_FPGAFEBR};
enum detNetworkParameter{TXN_LEFT, TXN_RIGHT, TXN_FRAME,FLOWCTRL_10G};
#define NORMAL_HIGHVOLTAGE_INPUTPORT "/sys/class/hwmon/hwmon5/device/in0_input"
#define NORMAL_HIGHVOLTAGE_OUTPUTPORT "/sys/class/hwmon/hwmon5/device/out0_output"
#define SPECIAL9M_HIGHVOLTAGE_PORT "/dev/ttyS1"
#define SPECIAL9M_HIGHVOLTAGE_BUFFERSIZE 16
#define MAX_SUBFRAME_EXPOSURE_VAL_IN_10NS (0x1FFFFFFF) /** 29 bit register for max subframe exposure value */