detectors/slsDetectorPackage
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added smp_clk, changed rdo vco freq from 1.25GHz to 1GHz, changed rdo clock dividers

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This commit is contained in:
maliakal_d 2020-09-01 12:06:39 +02:00
parent 8400c686b5
commit 00978a52c8
4 changed files with 12 additions and 8 deletions
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BIN
slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer
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2
slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c
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@ -378,6 +378,7 @@ void setupDetector() {
clkDivider[SYSTEM_C0] = DEFAULT_SYSTEM_C0; clkDivider[SYSTEM_C0] = DEFAULT_SYSTEM_C0;
clkDivider[SYSTEM_C1] = DEFAULT_SYSTEM_C1; clkDivider[SYSTEM_C1] = DEFAULT_SYSTEM_C1;
clkDivider[SYSTEM_C2] = DEFAULT_SYSTEM_C2; clkDivider[SYSTEM_C2] = DEFAULT_SYSTEM_C2;
clkDivider[SYSTEM_C3] = DEFAULT_SYSTEM_C3;
highvoltage = 0; highvoltage = 0;
trimmingPrint = logINFO; trimmingPrint = logINFO;
@ -2044,6 +2045,7 @@ int setClockDivider(enum CLKINDEX ind, int val) {
clkPhase[SYSTEM_C0] = 0; clkPhase[SYSTEM_C0] = 0;
clkPhase[SYSTEM_C1] = 0; clkPhase[SYSTEM_C1] = 0;
clkPhase[SYSTEM_C2] = 0; clkPhase[SYSTEM_C2] = 0;
clkPhase[SYSTEM_C3] = 0;
} }
// set the phase in degrees (reset by pll) // set the phase in degrees (reset by pll)

16
slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h
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@ -36,11 +36,12 @@
#define DEFAULT_DELAY_AFTER_TRIGGER (0) #define DEFAULT_DELAY_AFTER_TRIGGER (0)
#define DEFAULT_HIGH_VOLTAGE (0) #define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_TIMING_MODE (AUTO_TIMING) #define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_READOUT_C0 (10) //(125000000) // rdo_clk, 125 MHz #define DEFAULT_READOUT_C0 (8) //(125000000) // rdo_clk, 125 MHz
#define DEFAULT_READOUT_C1 (10) //(125000000) // rdo_x2_clk, 125 MHz #define DEFAULT_READOUT_C1 (8) //(125000000) // rdo_x2_clk, 125 MHz
#define DEFAULT_SYSTEM_C0 (4) //(250000000) // run_clk, 250 MHz #define DEFAULT_SYSTEM_C0 (4) //(250000000) // run_clk, 250 MHz
#define DEFAULT_SYSTEM_C1 (8) //(125000000) // chip_clk, 125 MHz #define DEFAULT_SYSTEM_C1 (8) //(125000000) // sync_clk, 125 MHz
#define DEFAULT_SYSTEM_C2 (8) //(125000000) // sync_clk, 125 MHz #define DEFAULT_SYSTEM_C2 (8) //(125000000) // str_clk, 125 MHz
#define DEFAULT_SYSTEM_C3 (5) //(200000000) // smp_clk, 200 MHz (only for timing receiver)
#define DEFAULT_ASIC_LATCHING_NUM_PULSES (10) #define DEFAULT_ASIC_LATCHING_NUM_PULSES (10)
#define DEFAULT_MSTR_OTPT_P1_NUM_PULSES (20) #define DEFAULT_MSTR_OTPT_P1_NUM_PULSES (20)
@ -48,7 +49,7 @@
#define MAX_TIMESLOT_VAL (0xFFFFFF) #define MAX_TIMESLOT_VAL (0xFFFFFF)
#define IP_HEADER_SIZE (20) #define IP_HEADER_SIZE (20)
#define FIXED_PLL_FREQUENCY (020000000) // 20MHz #define FIXED_PLL_FREQUENCY (020000000) // 20MHz
#define READOUT_PLL_VCO_FREQ_HZ (1250000000) // 1.25GHz #define READOUT_PLL_VCO_FREQ_HZ (1000000000) // 1GHz
#define SYSTEM_PLL_VCO_FREQ_HZ (1000000000) // 1GHz #define SYSTEM_PLL_VCO_FREQ_HZ (1000000000) // 1GHz
#define MAX_NUM_DESERIALIZERS (40) #define MAX_NUM_DESERIALIZERS (40)
@ -105,10 +106,11 @@ enum CLKINDEX {
SYSTEM_C0, SYSTEM_C0,
SYSTEM_C1, SYSTEM_C1,
SYSTEM_C2, SYSTEM_C2,
SYSTEM_C3,
NUM_CLOCKS NUM_CLOCKS
}; };
#define CLK_NAMES \ #define CLK_NAMES \
"READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2" "READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2", "SYSTEM_C3"
enum PLLINDEX { READOUT_PLL, SYSTEM_PLL }; enum PLLINDEX { READOUT_PLL, SYSTEM_PLL };
/* Struct Definitions */ /* Struct Definitions */
@ -164,4 +166,4 @@ typedef struct udp_header_struct {
#define SIGNAL_resStorage (22) #define SIGNAL_resStorage (22)
#define SIGNAL_resCounter (23) #define SIGNAL_resCounter (23)
#define SIGNAL_CHSclk (24) #define SIGNAL_CHSclk (24)
#define SIGNAL_exposing (25) #define SIGNAL_exposing (25)

2
slsSupportLib/include/versionAPI.h
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@ -8,5 +8,5 @@
#define APIGOTTHARD2 0x200810 #define APIGOTTHARD2 0x200810
#define APIJUNGFRAU 0x200810 #define APIJUNGFRAU 0x200810
#define APIMOENCH 0x200810 #define APIMOENCH 0x200810
#define APIMYTHEN3 0x200818
#define APIEIGER 0x200831 #define APIEIGER 0x200831
#define APIMYTHEN3 0x200901