diff --git a/slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer b/slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer index 7ba030459..043cdff1e 100755 Binary files a/slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer and b/slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer differ diff --git a/slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c b/slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c index 1e624f57d..7643fc0fa 100644 --- a/slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c +++ b/slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c @@ -378,6 +378,7 @@ void setupDetector() { clkDivider[SYSTEM_C0] = DEFAULT_SYSTEM_C0; clkDivider[SYSTEM_C1] = DEFAULT_SYSTEM_C1; clkDivider[SYSTEM_C2] = DEFAULT_SYSTEM_C2; + clkDivider[SYSTEM_C3] = DEFAULT_SYSTEM_C3; highvoltage = 0; trimmingPrint = logINFO; @@ -2044,6 +2045,7 @@ int setClockDivider(enum CLKINDEX ind, int val) { clkPhase[SYSTEM_C0] = 0; clkPhase[SYSTEM_C1] = 0; clkPhase[SYSTEM_C2] = 0; + clkPhase[SYSTEM_C3] = 0; } // set the phase in degrees (reset by pll) diff --git a/slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h b/slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h index 3fd3dd250..e02872239 100644 --- a/slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h +++ b/slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h @@ -36,11 +36,12 @@ #define DEFAULT_DELAY_AFTER_TRIGGER (0) #define DEFAULT_HIGH_VOLTAGE (0) #define DEFAULT_TIMING_MODE (AUTO_TIMING) -#define DEFAULT_READOUT_C0 (10) //(125000000) // rdo_clk, 125 MHz -#define DEFAULT_READOUT_C1 (10) //(125000000) // rdo_x2_clk, 125 MHz +#define DEFAULT_READOUT_C0 (8) //(125000000) // rdo_clk, 125 MHz +#define DEFAULT_READOUT_C1 (8) //(125000000) // rdo_x2_clk, 125 MHz #define DEFAULT_SYSTEM_C0 (4) //(250000000) // run_clk, 250 MHz -#define DEFAULT_SYSTEM_C1 (8) //(125000000) // chip_clk, 125 MHz -#define DEFAULT_SYSTEM_C2 (8) //(125000000) // sync_clk, 125 MHz +#define DEFAULT_SYSTEM_C1 (8) //(125000000) // sync_clk, 125 MHz +#define DEFAULT_SYSTEM_C2 (8) //(125000000) // str_clk, 125 MHz +#define DEFAULT_SYSTEM_C3 (5) //(200000000) // smp_clk, 200 MHz (only for timing receiver) #define DEFAULT_ASIC_LATCHING_NUM_PULSES (10) #define DEFAULT_MSTR_OTPT_P1_NUM_PULSES (20) @@ -48,7 +49,7 @@ #define MAX_TIMESLOT_VAL (0xFFFFFF) #define IP_HEADER_SIZE (20) #define FIXED_PLL_FREQUENCY (020000000) // 20MHz -#define READOUT_PLL_VCO_FREQ_HZ (1250000000) // 1.25GHz +#define READOUT_PLL_VCO_FREQ_HZ (1000000000) // 1GHz #define SYSTEM_PLL_VCO_FREQ_HZ (1000000000) // 1GHz #define MAX_NUM_DESERIALIZERS (40) @@ -105,10 +106,11 @@ enum CLKINDEX { SYSTEM_C0, SYSTEM_C1, SYSTEM_C2, + SYSTEM_C3, NUM_CLOCKS }; #define CLK_NAMES \ - "READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2" + "READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2", "SYSTEM_C3" enum PLLINDEX { READOUT_PLL, SYSTEM_PLL }; /* Struct Definitions */ @@ -164,4 +166,4 @@ typedef struct udp_header_struct { #define SIGNAL_resStorage (22) #define SIGNAL_resCounter (23) #define SIGNAL_CHSclk (24) -#define SIGNAL_exposing (25) \ No newline at end of file +#define SIGNAL_exposing (25) diff --git a/slsSupportLib/include/versionAPI.h b/slsSupportLib/include/versionAPI.h index 1cdf3790f..4637973d3 100644 --- a/slsSupportLib/include/versionAPI.h +++ b/slsSupportLib/include/versionAPI.h @@ -8,5 +8,5 @@ #define APIGOTTHARD2 0x200810 #define APIJUNGFRAU 0x200810 #define APIMOENCH 0x200810 -#define APIMYTHEN3 0x200818 #define APIEIGER 0x200831 +#define APIMYTHEN3 0x200901