Paul Barron c8775e5ae5 Create bOutput 2,3,6,7 for switches in MAIN.TcPOU ...

modified:   solution/solution.tsproj
	modified:   solution/tc_project_app/POUs/MAIN.TcPOU

2019-12-09 13:29:28 +01:00

solution

Create bOutput 2,3,6,7 for switches in MAIN.TcPOU

2019-12-09 13:29:28 +01:00

.gitattributes

Add files .gitignore and .gitattributes

2017-11-06 09:04:06 +01:00

.gitignore

Exclude *.tmc files

2017-12-08 12:12:31 +01:00

.gitmodules

Add tc_mca_std_lib.

2017-12-08 09:47:56 +01:00

bitbucket-pipelines.yml

bitbucket-pipelines.yml: Print status of git submodule

2019-11-29 11:44:53 +01:00

check_fix_white_space.py

Add check_fix_white_space.py

2019-11-29 08:32:17 +01:00

solution.sln

Commit after updating TwinCAT

2019-12-09 11:54:52 +01:00

twincat_version_manager.py

twincat_version_manager.py: Different versions for *.Tc and *.tsproj

2019-12-06 09:44:27 +01:00

UpgradeLog.htm

tc_mca_std_lib submodule update to remove VAR_INPUTS and VAR_OUPUTS

2019-04-30 14:47:57 +01:00

Description

Testrig with linear axis

2.7 MiB

Languages

Python 93%

sed 3.5%

Shell 3.5%