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fix: formatting DDG

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This commit is contained in:
e21206 2023-07-04 17:29:30 +02:00
parent 25c7ce04e3
commit 4e10a969c8
1 changed files with 4 additions and 4 deletions
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8
ophyd_devices/epics/devices/DelayGeneratorDG645.py
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@ -45,6 +45,7 @@ class DummyPositioner(PVPositioner):
readback = Component(EpicsSignalRO, "DelayAI", kind=Kind.config)
done = Component(Signal, value=1)
class DelayPair(PseudoPositioner):
"""Delay pair interface for DG645
@ -56,8 +57,8 @@ class DelayPair(PseudoPositioner):
delay = Component(PseudoSingle, limits=(0, 2000.0), name="delay")
width = Component(PseudoSingle, limits=(0, 2000.0), name="pulsewidth")
# The real delay axes
#ch1 = Component(EpicsSignal, "DelayAI", write_pv="DelayAO", name="ch1", put_complete=True, kind=Kind.config)
#ch2 = Component(EpicsSignal, "DelayAI", write_pv="DelayAO", name="ch2", put_complete=True, kind=Kind.config)
# ch1 = Component(EpicsSignal, "DelayAI", write_pv="DelayAO", name="ch1", put_complete=True, kind=Kind.config)
# ch2 = Component(EpicsSignal, "DelayAI", write_pv="DelayAO", name="ch2", put_complete=True, kind=Kind.config)
ch1 = Component(DummyPositioner, name="ch1")
ch2 = Component(DummyPositioner, name="ch2")
@ -152,8 +153,7 @@ class DelayGeneratorDG645(Device):
)
# Command PVs
arm = Component(EpicsSignal, "TriggerDelayBO", name="arm", kind=Kind.omitted
)
arm = Component(EpicsSignal, "TriggerDelayBO", name="arm", kind=Kind.omitted)
# Burst mode
burstMode = Component(