w
CI for csaxs_bec / test (push) Failing after 1m26s

This commit is contained in:
2026-02-10 15:26:38 +01:00
parent 4cf0fb3c30
commit be701e97d3
2 changed files with 24 additions and 9 deletions
+19 -1
View File
@@ -347,7 +347,25 @@ class GalilSignalBase(SocketSignal):
def __init__(self, signal_name, **kwargs):
self.signal_name = signal_name
super().__init__(**kwargs)
self.controller = self.parent.controller
self.controller = self._find_controller_recursively()
def _find_controller_recursively(self) -> Controller:
"""
Find controller instance recursively for nested sub-devices.
This is for example needed for the GalilRIO which has DDC components for the analog
and digital channels. (DDC components are sub-devices).
"""
_MAX_DEPTH = 10 # to prevent infinite recursion
current_parent = self.parent
depth = 0
while current_parent is not None and depth < _MAX_DEPTH:
if hasattr(current_parent, "controller") and isinstance(
current_parent.controller, Controller
):
return current_parent.controller
current_parent = getattr(current_parent, "parent", None)
depth += 1
raise RuntimeError("Controller not found within maximum depth")
class GalilSignalRO(GalilSignalBase):
+5 -8
View File
@@ -162,9 +162,6 @@ class GalilRIODigitalOutSignal(GalilSignalBase):
ret = self.controller.socket_put_and_receive(cmd)
logger.debug(f"Received readback for digital output channel {self._channel}: {ret}")
self._readback = float(ret.strip())
# Update timestamp for the readback
timestamp = time.time()
self._metadata["timestamp"] = timestamp
return self._readback
def _socket_set(self, value: Literal[0, 1]) -> None:
@@ -233,9 +230,9 @@ def _create_analog_channels(num_channels: int) -> dict[str, tuple]:
"""
an_channels = {}
for i in range(0, num_channels):
an_channels[f"an_ch{i}"] = (
an_channels[f"ch{i}"] = (
GalilRIOSignalRO,
f"ch{i}.VAL",
f"ch{i}",
{
"kind": Kind.normal,
"auto_monitor": True,
@@ -256,9 +253,9 @@ def _create_digital_output_channels(num_channels: int) -> dict[str, tuple]:
"""
di_out_channels = {}
for i in range(0, num_channels):
di_out_channels[f"di_out{i}"] = (
di_out_channels[f"ch{i}"] = (
GalilRIODigitalOutSignal,
f"ch{i}.VAL",
f"ch{i}",
{
"kind": Kind.config,
"auto_monitor": True,
@@ -285,7 +282,7 @@ class GalilRIO(PSIDeviceBase):
#############################
analog_in = DDC(_create_analog_channels(8)) # Creates an_ch0 to an_ch7
dig_out = DDC(_create_digital_output_channels(8)) # Creates di_out0 to di_out7
digital_out = DDC(_create_digital_output_channels(8)) # Creates di_out0 to di_out7
def __init__(
self,