173 lines
4.9 KiB
VHDL
173 lines
4.9 KiB
VHDL
--##################################################################
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-- Author : Boris Keil, Stefan Ritt
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-- Contents : User FPGA library with various components
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-- $Id: usr_lib.vhd 6908 2007-03-06 07:15:16Z ritt $
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--##################################################################
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--------------------------------------------------------------------
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------------------------ USR_LIB_VEC_IOFD_CPE_NALL -----------------
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--------------------------------------------------------------------
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-- FFs with CE & asynchr. clear (precedence, act. high), preset
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-- (active high) and threestate (act. high)
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library ieee;
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use ieee.std_logic_1164.ALL;
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--use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.ALL;
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-- synopsys translate_off
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library UNISIM;
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use UNISIM.Vcomponents.ALL;
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-- synopsys translate_on
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entity USR_LIB_VEC_IOFD_CPE_NALL is
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generic (
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width : integer := 1;
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init_val_to_pad : string := "0";
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init_val_from_pad : string := "0"
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);
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port (
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O_C : in std_logic_vector (width-1 downto 0);
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O_CE : in std_logic_vector (width-1 downto 0);
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O_CLR : in std_logic_vector (width-1 downto 0);
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O_PRE : in std_logic_vector (width-1 downto 0);
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O : out std_logic_vector (width-1 downto 0);
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I_C : in std_logic_vector (width-1 downto 0);
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I_CE : in std_logic_vector (width-1 downto 0);
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I_CLR : in std_logic_vector (width-1 downto 0);
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I_PRE : in std_logic_vector (width-1 downto 0);
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I : in std_logic_vector (width-1 downto 0);
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IO : inout std_logic_vector (width-1 downto 0);
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T : in std_logic_vector (width-1 downto 0)
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);
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end USR_LIB_VEC_IOFD_CPE_NALL;
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architecture arch of USR_LIB_VEC_IOFD_CPE_NALL is
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attribute BOX_TYPE : STRING ;
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attribute INIT : STRING ;
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attribute IOB : STRING ;
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component IOBUF
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port(
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O : out std_logic;
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IO : inout std_logic;
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I : in std_logic;
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T : in std_logic
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);
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end component;
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attribute BOX_TYPE of IOBUF : component is "PRIMITIVE";
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component FDCPE -- FF with CE & asynchronous clear (precedence) and preset
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generic(
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INIT : bit := '0'
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);
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port(
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Q : out std_logic;
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C : in std_logic;
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CE : in std_logic;
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D : in std_logic;
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CLR : in std_logic;
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PRE : in std_logic
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);
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end component;
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attribute BOX_TYPE of FDCPE : component is "PRIMITIVE";
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signal data_to_pad: std_logic_vector (width-1 downto 0);
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signal data_from_pad: std_logic_vector (width-1 downto 0);
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begin
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gen : for count in 0 to width-1 generate
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attribute INIT of FF1 : label is init_val_to_pad;
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attribute IOB of FF1 : label is "true";
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attribute INIT of FF2 : label is init_val_from_pad;
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attribute IOB of FF2 : label is "true";
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begin
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U1 : IOBUF
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port map (
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I => data_to_pad(count),
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O => data_from_pad(count),
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IO => IO(count),
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T => T(count)
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);
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FF1 : FDCPE
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port map (
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C => I_C(count),
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CE => I_CE(count),
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D => I(count),
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CLR => I_CLR(count),
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PRE => I_PRE(count),
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Q => data_to_pad(count)
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);
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FF2 : FDCPE
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port map (
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C => O_C(count),
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CE => O_CE(count),
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D => data_from_pad(count),
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CLR => O_CLR(count),
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PRE => O_PRE(count),
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Q => O(count)
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);
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end generate;
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end arch;
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--------------------------------------------------------------------
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------------------------ USR_LIB_VEC_FDC ---------------------------
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--------------------------------------------------------------------
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-- Input FFs with asynchr. clear (precedence, act. high)
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library ieee;
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use ieee.std_logic_1164.ALL;
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--use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.ALL;
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-- synopsys translate_off
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library UNISIM;
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use UNISIM.Vcomponents.ALL;
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-- synopsys translate_on
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entity USR_LIB_VEC_FDC is
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generic (
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width : integer := 1
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);
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port (
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I_CLK : in std_logic_vector (width-1 downto 0);
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I_CLR : in std_logic_vector (width-1 downto 0);
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I : in std_logic_vector (width-1 downto 0);
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O : out std_logic_vector (width-1 downto 0)
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);
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end USR_LIB_VEC_FDC;
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architecture arch of USR_LIB_VEC_FDC is
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attribute IOB : STRING ;
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attribute BOX_TYPE : STRING ;
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component FDC -- FF with asynchronous clear (precedence)
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generic(
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INIT : bit := '0'
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);
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port(
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C : in std_logic;
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CLR : in std_logic;
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D : in std_logic;
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Q : out std_logic
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);
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end component;
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attribute BOX_TYPE of FDC : component is "PRIMITIVE";
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begin
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gen : for count in 0 to width-1 generate
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attribute IOB of FF : label is "true";
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begin
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FF : FDC
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port map (
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C => I_CLK(count),
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CLR => I_CLR(count),
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D => I(count),
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Q => O(count)
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);
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end generate;
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end arch;
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