184 lines
7.4 KiB
Plaintext
184 lines
7.4 KiB
Plaintext
###############################################################
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## Author : Stefan Ritt
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## Contents : DRS4_EVAL4 FPGA constraint file
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## $Id: drs4_eval5.ucf 21696 2015-05-13 13:15:31Z ritt $
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###############################################################
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CONFIG PART = XC3S400-4TQ144 ;
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###############################################################
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# Timing constraints
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###############################################################
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# Timing group definitions
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# ------------------------
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NET "P_I_CLK33" TNM_NET = "P_I_CLK33";
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NET "P_I_*" TNM = PADS:P_I_PADS_ALL;
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NET "P_I_CLK33" TNM = PADS:P_I_CLK33_PAD;
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NET "P_O_*" TNM = PADS:P_O_PADS;
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NET "P_IO_*" TNM = PADS:P_IO_PADS;
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NET "P_O_LED*" TNM = PADS:P_O_LED_PADS;
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NET "P_I_J*" TNM = PADS:P_I_EXT_PADS;
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NET "P_I_ATRG*" TNM = PADS:P_I_EXT_PADS;
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NET "P_O_CAL" TNM = PADS:P_I_EXT_PADS;
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NET "P_O_TCA_CTRL" TNM = PADS:P_I_EXT_PADS;
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NET "P_IO_PMC_USR(28)" TNM = PADS:P_IO_PMC_USR28_PADS;
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TIMEGRP "P_I_PADS" = "P_I_PADS_ALL" EXCEPT "P_I_CLK33_PAD";
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# IFCLK is not connected to dedicated clock input
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# Following statement suppresses the error abort
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NET "P_I_CLK33" CLOCK_DEDICATED_ROUTE = FALSE;
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# Same for external trigger input
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NET "P_IO_ETRG_IN" CLOCK_DEDICATED_ROUTE = FALSE;
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# Fix Hold-Time-Violations
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# ------------------------
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NET "P_I_*" IOBDELAY = IFD;
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NET "P_IO_*" IOBDELAY = IFD;
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# Period constraint for 30 MHz main board clock oscillator
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# --------------------------------------------------------
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# 33 ns needed, 32 ns used -> 1 ns safety margin
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TIMESPEC "TS_P_I_CLK33" = PERIOD "P_I_CLK33" 32 ns HIGH 50 % INPUT_JITTER 100 ps;
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# Input pad setup/hold time constraints
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# -------------------------------------
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TIMEGRP "P_I_PADS" OFFSET = IN 20 ns BEFORE "P_I_CLK33";
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TIMEGRP "P_IO_PADS" OFFSET = IN 20 ns BEFORE "P_I_CLK33";
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# Output pad clock to output timing constraints
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# ---------------------------------------------
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TIMEGRP "P_O_PADS" OFFSET = OUT 22 ns AFTER "P_I_CLK33";
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TIMEGRP "P_IO_PADS" OFFSET = OUT 22 ns AFTER "P_I_CLK33";
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# remove noncritical contraints
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# -------------------------------
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TIMESPEC "TS_TIG_I_MMCX" = FROM "P_I_EXT_PADS" TO "FFS" TIG;
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TIMESPEC "TS_TIG_O_LED" = FROM "FFS" TO "P_O_LED_PADS" TIG;
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TIMESPEC "TS_TIG_O_EXT" = FROM "FFS" TO "P_O_EXT_PADS" TIG;
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TIMESPEC "TS_TIG_O_ADCCLK" = FROM "FFS" TO "P_IO_PMC_USR28_PADS" TIG;
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###############################################################
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# IOSTANDARD & pin drive speed constraints
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###############################################################
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NET "P_IO_*" IOSTANDARD = LVCMOS33;
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NET "P_I_*" IOSTANDARD = LVCMOS33;
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NET "P_O_*" IOSTANDARD = LVCMOS33;
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###############################################################
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# Pin location constraints
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###############################################################
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# 42 out of 64 PMC IOs
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# --------------------
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NET "P_I_CLK33" LOC = "P40"; # IFCLK input
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NET "P_I_CLK66" LOC = "P56"; # calibration quarz input
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NET "P_O_CAL" LOC = "P97" | IOSTANDARD = LVCMOS25;
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NET "P_O_TCA_CTRL" LOC = "P53"; # timing calibration control
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NET "P_IO_J42" LOC = "P141"; # J42
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NET "P_IO_J43" LOC = "P140"; # J43
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NET "P_IO_T19" LOC = "P108" | IOSTANDARD = LVCMOS25 | SLEW = FAST ; # T19
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NET "P_IO_T20" LOC = "P103" | IOSTANDARD = LVCMOS25 | SLEW = FAST ; # T20
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NET "P_I_J44" LOC = "P69";
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NET "P_I_ATRG1" LOC = "P70"; # analog trigger CH1
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NET "P_I_ATRG1" CLOCK_DEDICATED_ROUTE = FALSE;
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NET "P_I_ATRG2" LOC = "P68"; # analog trigger CH2
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NET "P_I_ATRG2" CLOCK_DEDICATED_ROUTE = FALSE;
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NET "P_I_ATRG3" LOC = "P60"; # analog trigger CH3
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NET "P_I_ATRG3" CLOCK_DEDICATED_ROUTE = FALSE;
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NET "P_I_ATRG4" LOC = "P59"; # analog trigger CH4
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NET "P_I_ATRG4" CLOCK_DEDICATED_ROUTE = FALSE;
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NET "P_IO_ETRG_IN" LOC = "P107" | IOSTANDARD = LVCMOS25 | SLEW = FAST ; # external trigger in
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NET "P_O_ETRG_IND" LOC = "P105" | IOSTANDARD = LVCMOS25; # external trigger in direciton
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NET "P_IO_ETRG_OUT" LOC = "P104" | IOSTANDARD = LVCMOS25 | SLEW = FAST ; # external trigger out
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NET "P_O_ETRG_OUTD" LOC = "P102" | IOSTANDARD = LVCMOS25; # external trigger out direction
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NET "P_IO_ECLK_IN" LOC = "P100" | IOSTANDARD = LVCMOS25 | SLEW = FAST ; # external clock input
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NET "P_IO_ECLK_IN" CLOCK_DEDICATED_ROUTE = FALSE;
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NET "P_O_ECLK_IND" LOC = "P99" | IOSTANDARD = LVCMOS25; # external clock input direction
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NET "P_IO_ECLK_OUT" LOC = "P98" | IOSTANDARD = LVCMOS25 | SLEW = FAST ; # external clock output
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NET "P_O_ECLK_OUTD" LOC = "P93" | IOSTANDARD = LVCMOS25; # external clock output direction
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NET "P_O_LED_GREEN" LOC = "P132";
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NET "P_O_LED_YELLOW" LOC = "P137";
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NET "P_IO_UC_SLOE" LOC = "P17";
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NET "P_IO_UC_SLRD" LOC = "P35";
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NET "P_IO_UC_SLWR" LOC = "P36";
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NET "P_IO_UC_SLCS" LOC = "P11";
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NET "P_IO_UC_PKTEND" LOC = "P12";
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NET "P_IO_UC_FIFOADR0" LOC = "P14";
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NET "P_IO_UC_FIFOADR1" LOC = "P13";
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NET "P_IO_UC_FLAGA" LOC = "P24";
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NET "P_IO_UC_FLAGB" LOC = "P23";
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NET "P_IO_UC_FLAGC" LOC = "P21";
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NET "P_I_UC_PA0" LOC = "P20";
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NET "P_IO_UC_FD(0)" LOC = "P30";
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NET "P_IO_UC_FD(1)" LOC = "P31";
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NET "P_IO_UC_FD(2)" LOC = "P32";
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NET "P_IO_UC_FD(3)" LOC = "P33";
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NET "P_IO_UC_FD(4)" LOC = "P28";
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NET "P_IO_UC_FD(5)" LOC = "P27";
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NET "P_IO_UC_FD(6)" LOC = "P26";
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NET "P_IO_UC_FD(7)" LOC = "P25";
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NET "P_IO_UC_FD(8)" LOC = "P10";
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NET "P_IO_UC_FD(9)" LOC = "P8";
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NET "P_IO_UC_FD(10)" LOC = "P7";
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NET "P_IO_UC_FD(11)" LOC = "P6";
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NET "P_IO_UC_FD(12)" LOC = "P5";
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NET "P_IO_UC_FD(13)" LOC = "P1";
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NET "P_IO_UC_FD(14)" LOC = "P2";
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NET "P_IO_UC_FD(15)" LOC = "P4";
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NET "P_IO_PMC_USR(0)" LOC = "P131";
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NET "P_IO_PMC_USR(2)" LOC = "P130";
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NET "P_IO_PMC_USR(4)" LOC = "P129";
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NET "P_IO_PMC_USR(6)" LOC = "P128";
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NET "P_IO_PMC_USR(8)" LOC = "P127";
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NET "P_IO_PMC_USR(10)" LOC = "P125";
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NET "P_IO_PMC_USR(12)" LOC = "P124";
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NET "P_IO_PMC_USR(14)" LOC = "P123";
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NET "P_IO_PMC_USR(16)" LOC = "P122";
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NET "P_IO_PMC_USR(18)" LOC = "P119";
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NET "P_IO_PMC_USR(20)" LOC = "P118";
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NET "P_IO_PMC_USR(22)" LOC = "P116";
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NET "P_IO_PMC_USR(24)" LOC = "P113";
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NET "P_IO_PMC_USR(26)" LOC = "P112";
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NET "P_IO_PMC_USR(28)" LOC = "P135";
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NET "P_IO_PMC_USR(29)" LOC = "P50";
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NET "P_IO_PMC_USR(30)" LOC = "P80" | IOSTANDARD = LVCMOS25;
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NET "P_IO_PMC_USR(31)" LOC = "P51";
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NET "P_IO_PMC_USR(33)" LOC = "P52";
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NET "P_IO_PMC_USR(35)" LOC = "P44";
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NET "P_IO_PMC_USR(37)" LOC = "P46";
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NET "P_IO_PMC_USR(39)" LOC = "P47";
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NET "P_IO_PMC_USR(40)" LOC = "P74" | IOSTANDARD = LVCMOS25;
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NET "P_IO_PMC_USR(41)" LOC = "P92" | IOSTANDARD = LVCMOS25;
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NET "P_IO_PMC_USR(42)" LOC = "P76" | IOSTANDARD = LVCMOS25;
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NET "P_IO_PMC_USR(48)" LOC = "P89" | IOSTANDARD = LVCMOS25;
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NET "P_IO_PMC_USR(50)" LOC = "P87" | IOSTANDARD = LVCMOS25;
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NET "P_IO_PMC_USR(51)" LOC = "P90" | IOSTANDARD = LVCMOS25;
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NET "P_IO_PMC_USR(52)" LOC = "P86" | IOSTANDARD = LVCMOS25;
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NET "P_IO_PMC_USR(53)" LOC = "P79" | IOSTANDARD = LVCMOS25;
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NET "P_IO_PMC_USR(54)" LOC = "P78" | IOSTANDARD = LVDS_25;
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NET "P_IO_PMC_USR(55)" LOC = "P77" | IOSTANDARD = LVDS_25;
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NET "P_IO_PMC_USR(56)" LOC = "P85" | IOSTANDARD = LVCMOS25;
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NET "P_IO_PMC_USR(58)" LOC = "P84" | IOSTANDARD = LVCMOS25;
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NET "P_IO_PMC_USR(60)" LOC = "P83" | IOSTANDARD = LVCMOS25;
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NET "P_IO_PMC_USR(62)" LOC = "P82" | IOSTANDARD = LVCMOS25;
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