290 lines
9.2 KiB
VHDL
290 lines
9.2 KiB
VHDL
-- Xilinx Testbench Template produced by program netgen J.39
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--
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--------------------------------------------------------------------------------
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library IEEE;
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library WORK;
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library SIMPRIM;
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use IEEE.STD_LOGIC_1164.ALL;
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use WORK.ALL;
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use SIMPRIM.VCOMPONENTS.ALL;
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use SIMPRIM.VPACKAGE.ALL;
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entity TBX_drs4_eval1 is
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end TBX_drs4_eval1;
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architecture TBX_ARCH of TBX_drs4_eval1 is
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component drs4_eval1
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port (
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P_IO_UC_SLWR : inout STD_LOGIC;
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P_IO_UC_PKTEND : inout STD_LOGIC;
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P_IO_UC_FLAGA : inout STD_LOGIC;
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P_IO_UC_FLAGB : inout STD_LOGIC;
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P_IO_UC_FLAGC : inout STD_LOGIC;
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P_I_UC_PA0 : in STD_LOGIC;
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P_IO_UC_SLCS : inout STD_LOGIC;
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P_IO_UC_FIFOADR0 : inout STD_LOGIC;
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P_IO_UC_FIFOADR1 : inout STD_LOGIC;
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P_IO_UC_SLOE : inout STD_LOGIC;
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P_IO_UC_SLRD : inout STD_LOGIC;
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P_I_CLK33 : in STD_LOGIC := 'X';
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P_I_CLK66 : in STD_LOGIC := 'X';
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P_I_LEMO1 : in STD_LOGIC;
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P_I_J36 : in STD_LOGIC;
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P_I_J37 : in STD_LOGIC;
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P_IO_J38 : inout STD_LOGIC;
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P_IO_J39 : inout STD_LOGIC;
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P_I_ATRG : in STD_LOGIC;
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P_O_LED0 : out STD_LOGIC;
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P_O_LED1 : out STD_LOGIC;
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P_IO_PMC_USR : inout STD_LOGIC_VECTOR ( 63 downto 0 );
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P_IO_UC_FD : inout STD_LOGIC_VECTOR ( 15 downto 0 )
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);
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end component;
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signal P_IO_UC_SLWR : STD_LOGIC;
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signal P_IO_UC_PKTEND : STD_LOGIC;
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signal P_IO_UC_FLAGA : STD_LOGIC;
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signal P_IO_UC_FLAGB : STD_LOGIC;
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signal P_IO_UC_FLAGC : STD_LOGIC;
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signal P_I_UC_PA0 : STD_LOGIC;
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signal P_IO_UC_SLCS : STD_LOGIC;
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signal P_IO_UC_FIFOADR0 : STD_LOGIC;
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signal P_IO_UC_FIFOADR1 : STD_LOGIC;
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signal P_IO_UC_SLOE : STD_LOGIC;
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signal P_IO_UC_SLRD : STD_LOGIC;
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signal P_I_CLK33 : STD_LOGIC;
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signal P_I_CLK66 : STD_LOGIC;
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signal P_I_J36 : STD_LOGIC;
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signal P_I_J37 : STD_LOGIC;
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signal P_IO_J38 : STD_LOGIC;
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signal P_IO_J39 : STD_LOGIC;
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signal P_I_ATRG : STD_LOGIC;
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signal P_O_LED0 : STD_LOGIC;
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signal P_O_LED1 : STD_LOGIC;
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signal P_I_LEMO1 : STD_LOGIC;
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signal P_IO_PMC_USR : STD_LOGIC_VECTOR ( 63 downto 0 );
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signal P_IO_UC_FD : STD_LOGIC_VECTOR ( 15 downto 0 );
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begin
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UUT : drs4_eval1
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port map (
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P_IO_UC_SLWR => P_IO_UC_SLWR,
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P_IO_UC_PKTEND => P_IO_UC_PKTEND,
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P_IO_UC_FLAGA => P_IO_UC_FLAGA,
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P_IO_UC_FLAGB => P_IO_UC_FLAGB,
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P_IO_UC_FLAGC => P_IO_UC_FLAGC,
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P_I_UC_PA0 => P_I_UC_PA0,
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P_IO_UC_SLCS => P_IO_UC_SLCS,
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P_IO_UC_FIFOADR0 => P_IO_UC_FIFOADR0,
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P_IO_UC_FIFOADR1 => P_IO_UC_FIFOADR1,
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P_IO_UC_SLOE => P_IO_UC_SLOE,
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P_IO_UC_SLRD => P_IO_UC_SLRD,
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P_I_CLK33 => P_I_CLK33,
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P_I_CLK66 => P_I_CLK66,
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P_I_J36 => P_I_J36,
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P_I_J37 => P_I_J37,
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P_IO_J38 => P_IO_J38,
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P_IO_J39 => P_IO_J39,
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P_I_ATRG => P_I_ATRG,
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P_I_LEMO1 => P_I_LEMO1,
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P_O_LED0 => P_O_LED0,
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P_O_LED1 => P_O_LED1,
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P_IO_PMC_USR(63) => P_IO_PMC_USR(63),
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P_IO_PMC_USR(62) => P_IO_PMC_USR(62),
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P_IO_PMC_USR(61) => P_IO_PMC_USR(61),
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P_IO_PMC_USR(60) => P_IO_PMC_USR(60),
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P_IO_PMC_USR(59) => P_IO_PMC_USR(59),
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P_IO_PMC_USR(58) => P_IO_PMC_USR(58),
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P_IO_PMC_USR(57) => P_IO_PMC_USR(57),
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P_IO_PMC_USR(56) => P_IO_PMC_USR(56),
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P_IO_PMC_USR(55) => P_IO_PMC_USR(55),
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P_IO_PMC_USR(54) => P_IO_PMC_USR(54),
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P_IO_PMC_USR(53) => P_IO_PMC_USR(53),
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P_IO_PMC_USR(52) => P_IO_PMC_USR(52),
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P_IO_PMC_USR(51) => P_IO_PMC_USR(51),
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P_IO_PMC_USR(50) => P_IO_PMC_USR(50),
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P_IO_PMC_USR(49) => P_IO_PMC_USR(49),
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P_IO_PMC_USR(48) => P_IO_PMC_USR(48),
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P_IO_PMC_USR(47) => P_IO_PMC_USR(47),
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P_IO_PMC_USR(46) => P_IO_PMC_USR(46),
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P_IO_PMC_USR(45) => P_IO_PMC_USR(45),
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P_IO_PMC_USR(44) => P_IO_PMC_USR(44),
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P_IO_PMC_USR(43) => P_IO_PMC_USR(43),
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P_IO_PMC_USR(42) => P_IO_PMC_USR(42),
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P_IO_PMC_USR(41) => P_IO_PMC_USR(41),
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P_IO_PMC_USR(40) => P_IO_PMC_USR(40),
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P_IO_PMC_USR(39) => P_IO_PMC_USR(39),
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P_IO_PMC_USR(38) => P_IO_PMC_USR(38),
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P_IO_PMC_USR(37) => P_IO_PMC_USR(37),
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P_IO_PMC_USR(36) => P_IO_PMC_USR(36),
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P_IO_PMC_USR(35) => P_IO_PMC_USR(35),
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P_IO_PMC_USR(34) => P_IO_PMC_USR(34),
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P_IO_PMC_USR(33) => P_IO_PMC_USR(33),
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P_IO_PMC_USR(32) => P_IO_PMC_USR(32),
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P_IO_PMC_USR(31) => P_IO_PMC_USR(31),
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P_IO_PMC_USR(30) => P_IO_PMC_USR(30),
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P_IO_PMC_USR(29) => P_IO_PMC_USR(29),
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P_IO_PMC_USR(28) => P_IO_PMC_USR(28),
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P_IO_PMC_USR(27) => P_IO_PMC_USR(27),
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P_IO_PMC_USR(26) => P_IO_PMC_USR(26),
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P_IO_PMC_USR(25) => P_IO_PMC_USR(25),
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P_IO_PMC_USR(24) => P_IO_PMC_USR(24),
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P_IO_PMC_USR(23) => P_IO_PMC_USR(23),
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P_IO_PMC_USR(22) => P_IO_PMC_USR(22),
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P_IO_PMC_USR(21) => P_IO_PMC_USR(21),
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P_IO_PMC_USR(20) => P_IO_PMC_USR(20),
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P_IO_PMC_USR(19) => P_IO_PMC_USR(19),
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P_IO_PMC_USR(18) => P_IO_PMC_USR(18),
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P_IO_PMC_USR(17) => P_IO_PMC_USR(17),
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P_IO_PMC_USR(16) => P_IO_PMC_USR(16),
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P_IO_PMC_USR(15) => P_IO_PMC_USR(15),
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P_IO_PMC_USR(14) => P_IO_PMC_USR(14),
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P_IO_PMC_USR(13) => P_IO_PMC_USR(13),
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P_IO_PMC_USR(12) => P_IO_PMC_USR(12),
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P_IO_PMC_USR(11) => P_IO_PMC_USR(11),
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P_IO_PMC_USR(10) => P_IO_PMC_USR(10),
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P_IO_PMC_USR(9) => P_IO_PMC_USR(9),
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P_IO_PMC_USR(8) => P_IO_PMC_USR(8),
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P_IO_PMC_USR(7) => P_IO_PMC_USR(7),
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P_IO_PMC_USR(6) => P_IO_PMC_USR(6),
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P_IO_PMC_USR(5) => P_IO_PMC_USR(5),
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P_IO_PMC_USR(4) => P_IO_PMC_USR(4),
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P_IO_PMC_USR(3) => P_IO_PMC_USR(3),
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P_IO_PMC_USR(2) => P_IO_PMC_USR(2),
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P_IO_PMC_USR(1) => P_IO_PMC_USR(1),
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P_IO_PMC_USR(0) => P_IO_PMC_USR(0),
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P_IO_UC_FD(15) => P_IO_UC_FD(15),
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P_IO_UC_FD(14) => P_IO_UC_FD(14),
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P_IO_UC_FD(13) => P_IO_UC_FD(13),
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P_IO_UC_FD(12) => P_IO_UC_FD(12),
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P_IO_UC_FD(11) => P_IO_UC_FD(11),
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P_IO_UC_FD(10) => P_IO_UC_FD(10),
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P_IO_UC_FD(9) => P_IO_UC_FD(9),
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P_IO_UC_FD(8) => P_IO_UC_FD(8),
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P_IO_UC_FD(7) => P_IO_UC_FD(7),
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P_IO_UC_FD(6) => P_IO_UC_FD(6),
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P_IO_UC_FD(5) => P_IO_UC_FD(5),
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P_IO_UC_FD(4) => P_IO_UC_FD(4),
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P_IO_UC_FD(3) => P_IO_UC_FD(3),
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P_IO_UC_FD(2) => P_IO_UC_FD(2),
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P_IO_UC_FD(1) => P_IO_UC_FD(1),
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P_IO_UC_FD(0) => P_IO_UC_FD(0)
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);
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-- User: Put your stimulus here.
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-- Clock generation
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proc_p_i_clk33_generator : process
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begin
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clock_loop : loop
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P_I_CLK33 <= '1';
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wait for 15 ns;
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P_I_CLK33 <= '0';
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wait for 15 ns;
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end loop;
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end process;
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proc_p_i_clk66_generator : process
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begin
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clock_loop : loop
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P_I_CLK66 <= '1';
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wait for 7.5 ns;
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P_I_CLK66 <= '0';
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wait for 7.5 ns;
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end loop;
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end process;
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-- Static signals
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P_I_LEMO1 <= '0';
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P_I_J36 <= '0';
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P_I_J37 <= '0';
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P_I_ATRG <= '0';
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P_IO_UC_FLAGA <= '1';
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P_IO_UC_FLAGB <= '1';
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P_IO_UC_PKTEND <= 'Z';
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P_I_UC_PA0 <= '1';
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-- Dynamic signals
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proc_p_io_dynamic: process
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-- Write cycle
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-- -----------
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procedure proc_wr_cycle(
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constant I_A : in std_logic_vector(15 downto 0);
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constant I_D : in std_logic_vector(15 downto 0)
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) is
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begin
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P_IO_UC_FLAGC <= '1';
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P_IO_UC_FD <= X"0002"; -- USB2_CMD_WRITE
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wait until P_IO_UC_SLOE = '0';
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wait until P_I_CLK33 = '0';
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wait until P_I_CLK33 = '1';
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wait for 4 ns;
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P_IO_UC_FD <= I_A; -- low word
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wait until P_I_CLK33 = '0';
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wait until P_I_CLK33 = '1';
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wait for 4 ns;
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P_IO_UC_FD <= (others => '0'); -- high word
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wait until P_I_CLK33 = '0';
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wait until P_I_CLK33 = '1';
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wait for 4 ns;
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P_IO_UC_FD <= X"0002"; -- low word
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wait until P_I_CLK33 = '0';
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wait until P_I_CLK33 = '1';
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wait for 4 ns;
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P_IO_UC_FD <= (others => '0'); -- high word
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wait until P_I_CLK33 = '0';
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wait until P_I_CLK33 = '1';
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wait for 4 ns;
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P_IO_UC_FD <= I_D;
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wait until P_I_CLK33 = '0';
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wait until P_I_CLK33 = '1';
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wait for 4 ns;
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P_IO_UC_FLAGC <= '0';
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P_IO_UC_FD <= "ZZZZZZZZZZZZZZZZ"; -- tri state
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end proc_wr_cycle;
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begin
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P_I_UC_PA0 <= '1';
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P_IO_UC_FD <= (others => '0');
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P_IO_UC_FLAGC <= '0';
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wait for 990 ns; -- Until DLLs locked
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proc_wr_cycle(X"0014", X"C000"); -- set ADC clock phase
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wait for 70 us;
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-- proc_wr_cycle(X"0000", X"0001"); -- start domino wave
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-- wait for 3 us;
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-- proc_wr_cycle(X"0000", X"0004"); -- issue soft trigger
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-- wait for 100 us;
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-- stop simulation
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assert false
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report "Simulation Complete (this is not a failure)"
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severity failure;
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end process;
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end TBX_ARCH;
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configuration TBX_CFG_drs4_eval1_TBX_ARCH of TBX_drs4_eval1 is
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for TBX_ARCH
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end for;
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end TBX_CFG_drs4_eval1_TBX_ARCH;
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