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version13

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version 11/12 auch noch
This commit is contained in:
pique_n
2025-05-23 11:44:24 +02:00
parent ec01320c33
commit b98c372f7e
71 changed files with 13172 additions and 16350 deletions
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5
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c
View File

@ -53,7 +53,7 @@
*/
#define STM32L4XX_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define STM32L4XX_HAL_VERSION_SUB1 (0x0DU) /*!< [23:16] sub1 version */
#define STM32L4XX_HAL_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */
#define STM32L4XX_HAL_VERSION_SUB2 (0x05U) /*!< [15:8] sub2 version */
#define STM32L4XX_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define STM32L4XX_HAL_VERSION ((STM32L4XX_HAL_VERSION_MAIN << 24U)\
|(STM32L4XX_HAL_VERSION_SUB1 << 16U)\
@ -381,7 +381,8 @@ HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
/**
* @brief Return tick frequency.
* @retval tick period in Hz
* @retval Tick frequency.
* Value of @ref HAL_TickFreqTypeDef.
*/
HAL_TickFreqTypeDef HAL_GetTickFreq(void)
{

303
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c
View File

@ -220,11 +220,11 @@
The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
allows the user to configure dynamically the driver callbacks.
Use Functions HAL_ADC_RegisterCallback()
Use Functions @ref HAL_ADC_RegisterCallback()
to register an interrupt callback.
[..]
Function HAL_ADC_RegisterCallback() allows to register following callbacks:
Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
(+) ConvCpltCallback : ADC conversion complete callback
(+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
(+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
@ -240,11 +240,11 @@
and a pointer to the user callback function.
[..]
Use function HAL_ADC_UnRegisterCallback to reset a callback to the default
Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
weak function.
[..]
HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
@ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) ConvCpltCallback : ADC conversion complete callback
@ -260,27 +260,27 @@
(+) MspDeInitCallback : ADC Msp DeInit callback
[..]
By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET
By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
all callbacks are set to the corresponding weak functions:
examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback().
examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
Exception done for MspInit and MspDeInit functions that are
reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when
reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
these callbacks are null (not registered beforehand).
[..]
If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit()
If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only.
Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state,
in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
[..]
Then, the user first registers the MspInit/MspDeInit user callbacks
using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit()
or HAL_ADC_Init() function.
using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
or @ref HAL_ADC_Init() function.
[..]
When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
@ -312,10 +312,11 @@
* @{
*/
#define ADC_CFGR_FIELDS_1 ((ADC_CFGR_RES | ADC_CFGR_ALIGN |\
ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\
ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated when no regular conversion is on-going */
#define ADC_CFGR_FIELDS_1 (ADC_CFGR_RES | ADC_CFGR_ALIGN |\
ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\
ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL) /*!< ADC_CFGR fields of parameters that can
be updated when no regular conversion is on-going */
/* Timeout values for ADC operations (enable settling time, */
/* disable settling time, ...). */
@ -393,11 +394,10 @@
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmpCFGR;
uint32_t tmp_adc_reg_is_conversion_on_going;
__IO uint32_t wait_loop_index = 0UL;
uint32_t tmp_cfgr;
uint32_t tmp_adc_is_conversion_on_going_regular;
uint32_t tmp_adc_is_conversion_on_going_injected;
__IO uint32_t wait_loop_index = 0UL;
/* Check ADC handle */
if (hadc == NULL)
@ -411,7 +411,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
#if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
assert_param(IS_ADC_DFSDMCFG_MODE(hadc));
#endif
#endif /* DFSDM */
assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
@ -516,10 +516,10 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
/* correctly completed and if there is no conversion on going on regular */
/* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
/* called to update a parameter on the fly). */
tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
&& (tmp_adc_reg_is_conversion_on_going == 0UL)
&& (tmp_adc_is_conversion_on_going_regular == 0UL)
)
{
/* Set ADC state */
@ -566,15 +566,15 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
/* - overrun Init.Overrun */
/* - discontinuous mode Init.DiscontinuousConvMode */
/* - discontinuous mode channel count Init.NbrOfDiscConversion */
tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
hadc->Init.Overrun |
hadc->Init.DataAlign |
hadc->Init.Resolution |
ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
hadc->Init.Overrun |
hadc->Init.DataAlign |
hadc->Init.Resolution |
ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
if (hadc->Init.DiscontinuousConvMode == ENABLE)
{
tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
tmp_cfgr |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
}
/* Enable external trigger if trigger selection is different of software */
@ -584,13 +584,13 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
/* software start. */
if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
{
tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
| hadc->Init.ExternalTrigConvEdge
);
tmp_cfgr |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
| hadc->Init.ExternalTrigConvEdge
);
}
/* Update Configuration Register CFGR */
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmp_cfgr);
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
@ -598,17 +598,16 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
/* - DMA continuous request Init.DMAContinuousRequests */
/* - LowPowerAutoWait feature Init.LowPowerAutoWait */
/* - Oversampling parameters Init.Oversampling */
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
if ((tmp_adc_is_conversion_on_going_regular == 0UL)
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
)
{
tmpCFGR = (ADC_CFGR_DFSDM(hadc) |
ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
tmp_cfgr = (ADC_CFGR_DFSDM(hadc) |
ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmp_cfgr);
if (hadc->Init.OversamplingMode == ENABLE)
{
@ -1207,7 +1206,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
#if defined(ADC_MULTIMODE_SUPPORT)
const ADC_TypeDef *tmpADC_Master;
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -1241,7 +1240,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
{
CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
}
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/* Set ADC error code */
/* Check if a conversion is on going on ADC group injected */
@ -1310,7 +1309,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
/* Start ADC group regular conversion */
LL_ADC_REG_StartConversion(hadc->Instance);
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
}
else
{
@ -1398,7 +1397,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti
#if defined(ADC_MULTIMODE_SUPPORT)
const ADC_TypeDef *tmpADC_Master;
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -1458,7 +1457,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti
{
tmp_Flag_End = (ADC_FLAG_EOC);
}
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
}
/* Get tick count */
@ -1531,7 +1530,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti
#else
/* Retrieve handle ADC CFGR register */
tmp_cfgr = READ_REG(hadc->Instance->CFGR);
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/* Clear polled flag */
if (tmp_Flag_End == ADC_FLAG_EOS)
@ -1559,9 +1558,12 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti
* @param EventType the ADC event type.
* This parameter can be one of the following values:
* @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event
* @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
* @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
* @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
* @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on
* all STM32 series)
* @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on
* all STM32 series)
* @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on
* all STM32 series)
* @arg @ref ADC_OVR_EVENT ADC Overrun event
* @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow event
* @param Timeout Timeout value in millisecond.
@ -1728,7 +1730,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
#if defined(ADC_MULTIMODE_SUPPORT)
const ADC_TypeDef *tmpADC_Master;
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -1762,7 +1764,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
{
CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
}
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/* Set ADC error code */
/* Check if a conversion is on going on ADC group injected */
@ -1904,7 +1906,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
/* Start ADC group regular conversion */
LL_ADC_REG_StartConversion(hadc->Instance);
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
}
else
{
@ -1987,7 +1989,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, ui
HAL_StatusTypeDef tmp_hal_status;
#if defined(ADC_MULTIMODE_SUPPORT)
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -2031,7 +2033,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, ui
{
CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
}
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/* Check if a conversion is on going on ADC group injected */
if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
@ -2100,7 +2102,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, ui
/* Process unlocked */
__HAL_UNLOCK(hadc);
}
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
}
else
{
@ -2209,7 +2211,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
* @param hadc ADC handle
* @retval ADC group regular conversion data
*/
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc)
uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc)
{
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -2237,7 +2239,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
#if defined(ADC_MULTIMODE_SUPPORT)
const ADC_TypeDef *tmpADC_Master;
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -2301,7 +2303,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
}
#else
tmp_cfgr = READ_REG(hadc->Instance->CFGR);
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/* Carry on if continuous mode is disabled */
if (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT)
@ -2391,7 +2393,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
}
#else
tmp_cfgr = READ_REG(hadc->Instance->CFGR);
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/* Disable interruption if no further conversion upcoming by injected */
/* external trigger or by automatic injected conversion with regular */
@ -2537,7 +2539,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
}
}
else
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
{
/* Multimode not set or feature not available or ADC independent */
if ((hadc->Instance->CFGR & ADC_CFGR_DMAEN) != 0UL)
@ -2693,10 +2695,10 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
* The setting of these parameters is conditioned to ADC state:
* Refer to comments of structure "ADC_ChannelConfTypeDef".
* @param hadc ADC handle
* @param sConfig Structure of ADC channel assigned to ADC group regular.
* @param pConfig Structure of ADC channel assigned to ADC group regular.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmpOffsetShifted;
@ -2707,24 +2709,24 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff));
assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber));
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset));
assert_param(IS_ADC_REGULAR_RANK(pConfig->Rank));
assert_param(IS_ADC_SAMPLE_TIME(pConfig->SamplingTime));
assert_param(IS_ADC_SINGLE_DIFFERENTIAL(pConfig->SingleDiff));
assert_param(IS_ADC_OFFSET_NUMBER(pConfig->OffsetNumber));
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfig->Offset));
/* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
ignored (considered as reset) */
assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));
assert_param(!((pConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));
/* Verification of channel number */
if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
if (pConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
{
assert_param(IS_ADC_CHANNEL(hadc, sConfig->Channel));
assert_param(IS_ADC_CHANNEL(hadc, pConfig->Channel));
}
else
{
assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfig->Channel));
assert_param(IS_ADC_DIFF_CHANNEL(hadc, pConfig->Channel));
}
/* Process locked */
@ -2738,37 +2740,40 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
{
#if !defined (USE_FULL_ASSERT)
uint32_t config_rank = pConfig->Rank;
/* Correspondence for compatibility with legacy definition of */
/* sequencer ranks in direct number format. This correspondence can */
/* be done only on ranks 1 to 5 due to literal values. */
/* Note: Sequencer ranks in direct number format are no more used */
/* and are detected by activating USE_FULL_ASSERT feature. */
if (sConfig->Rank <= 5U)
if (pConfig->Rank <= 5U)
{
switch (sConfig->Rank)
switch (pConfig->Rank)
{
case 2U:
sConfig->Rank = ADC_REGULAR_RANK_2;
config_rank = ADC_REGULAR_RANK_2;
break;
case 3U:
sConfig->Rank = ADC_REGULAR_RANK_3;
config_rank = ADC_REGULAR_RANK_3;
break;
case 4U:
sConfig->Rank = ADC_REGULAR_RANK_4;
config_rank = ADC_REGULAR_RANK_4;
break;
case 5U:
sConfig->Rank = ADC_REGULAR_RANK_5;
config_rank = ADC_REGULAR_RANK_5;
break;
/* case 1U */
default:
sConfig->Rank = ADC_REGULAR_RANK_1;
config_rank = ADC_REGULAR_RANK_1;
break;
}
}
#endif
/* Set ADC group regular sequence: channel on the selected scan sequence rank */
LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel);
LL_ADC_REG_SetSequencerRanks(hadc->Instance, config_rank, pConfig->Channel);
#else
/* Set ADC group regular sequence: channel on the selected scan sequence rank */
LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, pConfig->Channel);
#endif/* USE_FULL_ASSERT */
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
@ -2783,10 +2788,10 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
{
#if defined(ADC_SMPR1_SMPPLUS)
/* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */
if (sConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5)
if (pConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5)
{
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES_5);
LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES_5);
/* Set ADC sampling time common configuration */
LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5);
@ -2794,26 +2799,26 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
else
{
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime);
/* Set ADC sampling time common configuration */
LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
}
#else
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
#endif
LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime);
#endif /* ADC_SMPR1_SMPPLUS */
/* Configure the offset: offset enable/disable, channel, offset value */
/* Shift the offset with respect to the selected ADC resolution. */
/* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset);
tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)pConfig->Offset);
if (sConfig->OffsetNumber != ADC_OFFSET_NONE)
if (pConfig->OffsetNumber != ADC_OFFSET_NONE)
{
/* Set ADC selected offset number */
LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted);
LL_ADC_SetOffset(hadc->Instance, pConfig->OffsetNumber, pConfig->Channel, tmpOffsetShifted);
}
else
@ -2821,22 +2826,22 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
/* Scan each offset register to check if the selected channel is targeted. */
/* If this is the case, the corresponding offset number is disabled. */
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
}
@ -2849,16 +2854,18 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
{
/* Set mode single-ended or differential input of the selected ADC channel */
LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff);
LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfig->Channel, pConfig->SingleDiff);
/* Configuration of differential mode */
if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
if (pConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
{
/* Set sampling time of the selected ADC channel */
/* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
LL_ADC_SetChannelSamplingTime(hadc->Instance,
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
sConfig->SamplingTime);
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
(__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)pConfig->Channel)
+ 1UL) & 0x1FUL)),
pConfig->SamplingTime);
}
}
@ -2869,13 +2876,13 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
/* Note: these internal measurement paths can be disabled using */
/* HAL_ADC_DeInit(). */
if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel))
{
tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
/* If the requested internal measurement path has already been enabled, */
/* bypass the configuration processing. */
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
if ((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
{
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
@ -2895,7 +2902,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
}
}
}
else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
else if ((pConfig->Channel == ADC_CHANNEL_VBAT)
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
{
if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
{
@ -2903,7 +2911,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
}
}
else if ((sConfig->Channel == ADC_CHANNEL_VREFINT)
else if ((pConfig->Channel == ADC_CHANNEL_VREFINT)
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
{
if (ADC_VREFINT_INSTANCE(hadc))
@ -2950,28 +2958,28 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
* @note On this STM32 series, analog watchdog thresholds cannot be modified
* while ADC conversion is on going.
* @param hadc ADC handle
* @param AnalogWDGConfig Structure of ADC analog watchdog configuration
* @param pAnalogWDGConfig Structure of ADC analog watchdog configuration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmpAWDHighThresholdShifted;
uint32_t tmpAWDLowThresholdShifted;
uint32_t tmp_awd_high_threshold_shifted;
uint32_t tmp_awd_low_threshold_shifted;
uint32_t tmp_adc_is_conversion_on_going_regular;
uint32_t tmp_adc_is_conversion_on_going_injected;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(pAnalogWDGConfig->WatchdogNumber));
assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(pAnalogWDGConfig->WatchdogMode));
assert_param(IS_FUNCTIONAL_STATE(pAnalogWDGConfig->ITMode));
if ((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC))
if ((pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
(pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
(pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC))
{
assert_param(IS_ADC_CHANNEL(hadc, AnalogWDGConfig->Channel));
assert_param(IS_ADC_CHANNEL(hadc, pAnalogWDGConfig->Channel));
}
/* Verify thresholds range */
@ -2980,14 +2988,14 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
/* Case of oversampling enabled: depending on ratio and shift configuration,
analog watchdog thresholds can be higher than ADC resolution.
Verify if thresholds are within maximum thresholds range. */
assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->HighThreshold));
assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->LowThreshold));
assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, pAnalogWDGConfig->HighThreshold));
assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, pAnalogWDGConfig->LowThreshold));
}
else
{
/* Verify if thresholds are within the selected ADC resolution */
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->HighThreshold));
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->LowThreshold));
}
/* Process locked */
@ -3005,26 +3013,29 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
)
{
/* Analog watchdog configuration */
if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
{
/* Configuration of analog watchdog: */
/* - Set the analog watchdog enable mode: one or overall group of */
/* channels, on groups regular and-or injected. */
switch (AnalogWDGConfig->WatchdogMode)
switch (pAnalogWDGConfig->WatchdogMode)
{
case ADC_ANALOGWATCHDOG_SINGLE_REG:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
LL_ADC_GROUP_REGULAR));
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
__LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
LL_ADC_GROUP_REGULAR));
break;
case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
LL_ADC_GROUP_INJECTED));
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
__LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
LL_ADC_GROUP_INJECTED));
break;
case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
LL_ADC_GROUP_REGULAR_INJECTED));
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
__LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
LL_ADC_GROUP_REGULAR_INJECTED));
break;
case ADC_ANALOGWATCHDOG_ALL_REG:
@ -3047,12 +3058,12 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
/* Shift the offset in function of the selected ADC resolution: */
/* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */
/* are set to 0 */
tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
tmp_awd_high_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->HighThreshold);
tmp_awd_low_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->LowThreshold);
/* Set ADC analog watchdog thresholds value of both thresholds high and low */
LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted,
tmpAWDLowThresholdShifted);
LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, tmp_awd_high_threshold_shifted,
tmp_awd_low_threshold_shifted);
/* Update state, clear previous result related to AWD1 */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
@ -3064,7 +3075,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
LL_ADC_ClearFlag_AWD1(hadc->Instance);
/* Configure ADC analog watchdog interrupt */
if (AnalogWDGConfig->ITMode == ENABLE)
if (pAnalogWDGConfig->ITMode == ENABLE)
{
LL_ADC_EnableIT_AWD1(hadc->Instance);
}
@ -3076,44 +3087,47 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
/* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */
else
{
switch (AnalogWDGConfig->WatchdogMode)
switch (pAnalogWDGConfig->WatchdogMode)
{
case ADC_ANALOGWATCHDOG_SINGLE_REG:
case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
/* Update AWD by bitfield to keep the possibility to monitor */
/* several channels by successive calls of this function. */
if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
{
SET_BIT(hadc->Instance->AWD2CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
SET_BIT(hadc->Instance->AWD2CR,
(1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL)));
}
else
{
SET_BIT(hadc->Instance->AWD3CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
SET_BIT(hadc->Instance->AWD3CR,
(1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL)));
}
break;
case ADC_ANALOGWATCHDOG_ALL_REG:
case ADC_ANALOGWATCHDOG_ALL_INJEC:
case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance,
pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
break;
default: /* ADC_ANALOGWATCHDOG_NONE */
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE);
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE);
break;
}
/* Shift the thresholds in function of the selected ADC resolution */
/* have to be left-aligned on bit 7, the LSB (right bits) are set to 0 */
tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
tmp_awd_high_threshold_shifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->HighThreshold);
tmp_awd_low_threshold_shifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->LowThreshold);
/* Set ADC analog watchdog thresholds value of both thresholds high and low */
LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted,
tmpAWDLowThresholdShifted);
LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, tmp_awd_high_threshold_shifted,
tmp_awd_low_threshold_shifted);
if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
{
/* Update state, clear previous result related to AWD2 */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
@ -3125,7 +3139,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
LL_ADC_ClearFlag_AWD2(hadc->Instance);
/* Configure ADC analog watchdog interrupt */
if (AnalogWDGConfig->ITMode == ENABLE)
if (pAnalogWDGConfig->ITMode == ENABLE)
{
LL_ADC_EnableIT_AWD2(hadc->Instance);
}
@ -3134,7 +3148,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
LL_ADC_DisableIT_AWD2(hadc->Instance);
}
}
/* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
/* (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
else
{
/* Update state, clear previous result related to AWD3 */
@ -3147,7 +3161,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
LL_ADC_ClearFlag_AWD3(hadc->Instance);
/* Configure ADC analog watchdog interrupt */
if (AnalogWDGConfig->ITMode == ENABLE)
if (pAnalogWDGConfig->ITMode == ENABLE)
{
LL_ADC_EnableIT_AWD3(hadc->Instance);
}
@ -3207,7 +3221,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
* @param hadc ADC handle
* @retval ADC handle state (bitfield on 32 bits)
*/
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc)
uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc)
{
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -3221,7 +3235,7 @@ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc)
* @param hadc ADC handle
* @retval ADC error code (bitfield on 32 bits)
*/
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc)
{
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -3410,7 +3424,8 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
/* Enable the ADC peripheral */
LL_ADC_Enable(hadc->Instance);
if((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) != 0UL)
if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))
& LL_ADC_PATH_INTERNAL_TEMPSENSOR) != 0UL)
{
/* Delay for temperature sensor buffer stabilization time */
/* Note: Value LL_ADC_DELAY_TEMPSENSOR_STAB_US used instead of */
@ -3423,7 +3438,7 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
while(wait_loop_index != 0UL)
while (wait_loop_index != 0UL)
{
wait_loop_index--;
}

319
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c
View File

@ -50,9 +50,10 @@
* @{
*/
#define ADC_JSQR_FIELDS ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\
ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime once the ADC is enabled */
#define ADC_JSQR_FIELDS ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\
ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can
be updated anytime once the ADC is enabled */
/* Fixed timeout value for ADC calibration. */
/* Values defined to be higher than worst cases: maximum ratio between ADC */
@ -189,7 +190,7 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t
* @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
* @retval Calibration value.
*/
uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
{
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -272,7 +273,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc)
uint32_t tmp_config_injected_queue;
#if defined(ADC_MULTIMODE_SUPPORT)
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -338,7 +339,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc)
{
CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
}
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/* Clear ADC group injected group conversion flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
@ -385,7 +386,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc)
/* Start ADC group injected conversion */
LL_ADC_INJ_StartConversion(hadc->Instance);
}
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
}
else
@ -473,14 +474,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc)
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
{
uint32_t tickstart;
uint32_t tmp_Flag_End;
uint32_t tmp_flag_end;
uint32_t tmp_adc_inj_is_trigger_source_sw_start;
uint32_t tmp_adc_reg_is_trigger_source_sw_start;
uint32_t tmp_cfgr;
#if defined(ADC_MULTIMODE_SUPPORT)
const ADC_TypeDef *tmpADC_Master;
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -488,18 +489,18 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, u
/* If end of sequence selected */
if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
{
tmp_Flag_End = ADC_FLAG_JEOS;
tmp_flag_end = ADC_FLAG_JEOS;
}
else /* end of conversion selected */
{
tmp_Flag_End = ADC_FLAG_JEOC;
tmp_flag_end = ADC_FLAG_JEOC;
}
/* Get timeout */
tickstart = HAL_GetTick();
/* Wait until End of Conversion or Sequence flag is raised */
while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
while ((hadc->Instance->ISR & tmp_flag_end) == 0UL)
{
/* Check if timeout is disabled (set to infinite wait) */
if (Timeout != HAL_MAX_DELAY)
@ -507,7 +508,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, u
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
{
/* New check to avoid false timeout detection in case of preemption */
if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
if ((hadc->Instance->ISR & tmp_flag_end) == 0UL)
{
/* Update ADC state machine to timeout */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
@ -543,7 +544,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, u
}
#else
tmp_cfgr = READ_REG(hadc->Instance->CFGR);
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/* Update ADC state machine */
SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
@ -579,7 +580,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, u
}
/* Clear polled flag */
if (tmp_Flag_End == ADC_FLAG_JEOS)
if (tmp_flag_end == ADC_FLAG_JEOS)
{
/* Clear end of sequence JEOS flag of injected group if low power feature */
/* "LowPowerAutoWait " is disabled, to not interfere with this feature. */
@ -617,7 +618,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc)
uint32_t tmp_config_injected_queue;
#if defined(ADC_MULTIMODE_SUPPORT)
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -683,7 +684,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc)
{
CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
}
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/* Clear ADC group injected group conversion flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
@ -751,7 +752,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc)
/* Start ADC group injected conversion */
LL_ADC_INJ_StartConversion(hadc->Instance);
}
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
}
else
@ -854,7 +855,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc)
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
{
HAL_StatusTypeDef tmp_hal_status;
ADC_HandleTypeDef tmphadcSlave;
ADC_HandleTypeDef tmp_hadc_slave;
ADC_Common_TypeDef *tmpADC_Common;
/* Check the parameters */
@ -873,13 +874,13 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t
__HAL_LOCK(hadc);
/* Temporary handle minimum initialization */
__HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
ADC_CLEAR_ERRORCODE(&tmphadcSlave);
__HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
/* Set a temporary handle of the ADC slave associated to the ADC master */
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
if (tmphadcSlave.Instance == NULL)
if (tmp_hadc_slave.Instance == NULL)
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
@ -895,7 +896,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t
tmp_hal_status = ADC_Enable(hadc);
if (tmp_hal_status == HAL_OK)
{
tmp_hal_status = ADC_Enable(&tmphadcSlave);
tmp_hal_status = ADC_Enable(&tmp_hadc_slave);
}
/* Start multimode conversion of ADCs pair */
@ -974,9 +975,9 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef tmp_hal_status;
uint32_t tickstart;
ADC_HandleTypeDef tmphadcSlave;
uint32_t tmphadcSlave_conversion_on_going;
HAL_StatusTypeDef tmphadcSlave_disable_status;
ADC_HandleTypeDef tmp_hadc_slave;
uint32_t tmp_hadc_slave_conversion_on_going;
HAL_StatusTypeDef tmp_hadc_slave_disable_status;
/* Check the parameters */
assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
@ -984,7 +985,6 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
/* Process locked */
__HAL_LOCK(hadc);
/* 1. Stop potential multimode conversion on going, on regular and injected groups */
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
@ -992,13 +992,13 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
if (tmp_hal_status == HAL_OK)
{
/* Temporary handle minimum initialization */
__HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
ADC_CLEAR_ERRORCODE(&tmphadcSlave);
__HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
/* Set a temporary handle of the ADC slave associated to the ADC master */
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
if (tmphadcSlave.Instance == NULL)
if (tmp_hadc_slave.Instance == NULL)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
@ -1015,17 +1015,17 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
/* 1. Wait for ADC conversion completion for ADC master and ADC slave */
tickstart = HAL_GetTick();
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
|| (tmphadcSlave_conversion_on_going == 1UL)
|| (tmp_hadc_slave_conversion_on_going == 1UL)
)
{
if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
{
/* New check to avoid false timeout detection in case of preemption */
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
|| (tmphadcSlave_conversion_on_going == 1UL)
|| (tmp_hadc_slave_conversion_on_going == 1UL)
)
{
/* Update ADC state machine to error */
@ -1038,7 +1038,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
}
}
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
}
/* Disable the DMA channel (in case of DMA in circular mode or stop */
@ -1062,9 +1062,9 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
/* memory a potential failing status. */
if (tmp_hal_status == HAL_OK)
{
tmphadcSlave_disable_status = ADC_Disable(&tmphadcSlave);
tmp_hadc_slave_disable_status = ADC_Disable(&tmp_hadc_slave);
if ((ADC_Disable(hadc) == HAL_OK) &&
(tmphadcSlave_disable_status == HAL_OK))
(tmp_hadc_slave_disable_status == HAL_OK))
{
tmp_hal_status = HAL_OK;
}
@ -1073,7 +1073,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
{
/* In case of error, attempt to disable ADC master and slave without status assert */
(void) ADC_Disable(hadc);
(void) ADC_Disable(&tmphadcSlave);
(void) ADC_Disable(&tmp_hadc_slave);
}
/* Set ADC state (ADC master) */
@ -1094,7 +1094,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
* @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used)
* @retval The converted data values.
*/
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc)
uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc)
{
const ADC_Common_TypeDef *tmpADC_Common;
@ -1127,7 +1127,7 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc)
* both flags JEOC and EOS are raised.
* Flag JEOS must not be cleared by this function because
* it would not be compliant with low power features
* (feature low power auto-wait, not available on all STM32 families).
* (feature low power auto-wait, not available on all STM32 series).
* To clear this flag, either use function:
* in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
* model polling: @ref HAL_ADCEx_InjectedPollForConversion()
@ -1141,7 +1141,7 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc)
* @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4
* @retval ADC group injected conversion data
*/
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
{
uint32_t tmp_jdr;
@ -1451,7 +1451,8 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc)
#if defined(ADC_MULTIMODE_SUPPORT)
/**
* @brief Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
* @brief Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected
* conversion is on-going.
* @note Multimode is kept enabled after this function. Multimode DMA bits
* (MDMA and DMACFG bits of common CCR register) are maintained. To disable
* multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
@ -1467,8 +1468,8 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef tmp_hal_status;
uint32_t tickstart;
ADC_HandleTypeDef tmphadcSlave;
uint32_t tmphadcSlave_conversion_on_going;
ADC_HandleTypeDef tmp_hadc_slave;
uint32_t tmp_hadc_slave_conversion_on_going;
/* Check the parameters */
assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
@ -1487,13 +1488,13 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
/* Temporary handle minimum initialization */
__HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
ADC_CLEAR_ERRORCODE(&tmphadcSlave);
__HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
/* Set a temporary handle of the ADC slave associated to the ADC master */
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
if (tmphadcSlave.Instance == NULL)
if (tmp_hadc_slave.Instance == NULL)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
@ -1510,17 +1511,17 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
/* 1. Wait for ADC conversion completion for ADC master and ADC slave */
tickstart = HAL_GetTick();
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
|| (tmphadcSlave_conversion_on_going == 1UL)
|| (tmp_hadc_slave_conversion_on_going == 1UL)
)
{
if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
{
/* New check to avoid false timeout detection in case of preemption */
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
|| (tmphadcSlave_conversion_on_going == 1UL)
|| (tmp_hadc_slave_conversion_on_going == 1UL)
)
{
/* Update ADC state machine to error */
@ -1533,7 +1534,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
}
}
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
}
/* Disable the DMA channel (in case of DMA in circular mode or stop */
@ -1563,9 +1564,9 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
tmp_hal_status = ADC_Disable(hadc);
if (tmp_hal_status == HAL_OK)
{
if (LL_ADC_INJ_IsConversionOngoing((&tmphadcSlave)->Instance) == 0UL)
if (LL_ADC_INJ_IsConversionOngoing((&tmp_hadc_slave)->Instance) == 0UL)
{
tmp_hal_status = ADC_Disable(&tmphadcSlave);
tmp_hal_status = ADC_Disable(&tmp_hadc_slave);
}
}
}
@ -1644,59 +1645,62 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
* start once the 1st context is set, that is after the first three
* HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly.
* @param hadc ADC handle
* @param sConfigInjected Structure of ADC injected group and ADC channel for
* @param pConfigInjected Structure of ADC injected group and ADC channel for
* injected group.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,
const ADC_InjectionConfTypeDef *pConfigInjected)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmpOffsetShifted;
uint32_t tmp_offset_shifted;
uint32_t tmp_config_internal_channel;
uint32_t tmp_adc_is_conversion_on_going_regular;
uint32_t tmp_adc_is_conversion_on_going_injected;
__IO uint32_t wait_loop_index = 0;
uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0U;
uint32_t tmp_jsqr_context_queue_being_built = 0U;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfigInjected->InjectedSingleDiff));
assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext));
assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
assert_param(IS_ADC_EXTTRIGINJEC(hadc, sConfigInjected->ExternalTrigInjecConv));
assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber));
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjecOversamplingMode));
assert_param(IS_ADC_SAMPLE_TIME(pConfigInjected->InjectedSamplingTime));
assert_param(IS_ADC_SINGLE_DIFFERENTIAL(pConfigInjected->InjectedSingleDiff));
assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->AutoInjectedConv));
assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->QueueInjectedContext));
assert_param(IS_ADC_EXTTRIGINJEC_EDGE(pConfigInjected->ExternalTrigInjecConvEdge));
assert_param(IS_ADC_EXTTRIGINJEC(hadc, pConfigInjected->ExternalTrigInjecConv));
assert_param(IS_ADC_OFFSET_NUMBER(pConfigInjected->InjectedOffsetNumber));
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfigInjected->InjectedOffset));
assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjecOversamplingMode));
if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
{
assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
assert_param(IS_ADC_INJECTED_RANK(pConfigInjected->InjectedRank));
assert_param(IS_ADC_INJECTED_NB_CONV(pConfigInjected->InjectedNbrOfConversion));
assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjectedDiscontinuousConvMode));
}
/* if JOVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
ignored (considered as reset) */
assert_param(!((sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) && (sConfigInjected->InjecOversamplingMode == ENABLE)));
assert_param(!((pConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
&& (pConfigInjected->InjecOversamplingMode == ENABLE)));
/* JDISCEN and JAUTO bits can't be set at the same time */
assert_param(!((sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));
assert_param(!((pConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
&& (pConfigInjected->AutoInjectedConv == ENABLE)));
/* DISCEN and JAUTO bits can't be set at the same time */
assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));
assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (pConfigInjected->AutoInjectedConv == ENABLE)));
/* Verification of channel number */
if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
if (pConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
{
assert_param(IS_ADC_CHANNEL(hadc, sConfigInjected->InjectedChannel));
assert_param(IS_ADC_CHANNEL(hadc, pConfigInjected->InjectedChannel));
}
else
{
assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfigInjected->InjectedChannel));
assert_param(IS_ADC_DIFF_CHANNEL(hadc, pConfigInjected->InjectedChannel));
}
/* Process locked */
@ -1724,7 +1728,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
/* by software for alignment over all STM32 devices. */
if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) ||
(sConfigInjected->InjectedNbrOfConversion == 1U))
(pConfigInjected->InjectedNbrOfConversion == 1U))
{
/* Configuration of context register JSQR: */
/* - number of ranks in injected group sequencer: fixed to 1st rank */
@ -1733,28 +1737,28 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
/* - external trigger polarity */
/* - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */
if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
if (pConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
{
/* Enable external trigger if trigger selection is different of */
/* software start. */
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
/* software start. */
if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
if (pConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
{
tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)
| (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
| sConfigInjected->ExternalTrigInjecConvEdge
);
tmp_jsqr_context_queue_being_built = (ADC_JSQR_RK(pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)
| (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
| pConfigInjected->ExternalTrigInjecConvEdge
);
}
else
{
tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1));
tmp_jsqr_context_queue_being_built = (ADC_JSQR_RK(pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1));
}
MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_JSQR_ContextQueueBeingBuilt);
MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_jsqr_context_queue_being_built);
/* For debug and informative reasons, hadc handle saves JSQR setting */
hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt;
hadc->InjectionConfig.ContextQueue = tmp_jsqr_context_queue_being_built;
}
}
@ -1774,7 +1778,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
{
/* Initialize number of channels that will be configured on the context */
/* being built */
hadc->InjectionConfig.ChannelCount = sConfigInjected->InjectedNbrOfConversion;
hadc->InjectionConfig.ChannelCount = pConfigInjected->InjectedNbrOfConversion;
/* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel()
call, this context will be written in JSQR register at the last call.
At this point, the context is merely reset */
@ -1790,16 +1794,16 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
/* software start. */
if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
if (pConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
{
tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U)
| (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
| sConfigInjected->ExternalTrigInjecConvEdge
);
tmp_jsqr_context_queue_being_built = ((pConfigInjected->InjectedNbrOfConversion - 1U)
| (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
| pConfigInjected->ExternalTrigInjecConvEdge
);
}
else
{
tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U));
tmp_jsqr_context_queue_being_built = ((pConfigInjected->InjectedNbrOfConversion - 1U));
}
}
@ -1807,18 +1811,18 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
/* 2. Continue setting of context under definition with parameter */
/* related to each channel: channel rank sequence */
/* Clear the old JSQx bits for the selected rank */
tmp_JSQR_ContextQueueBeingBuilt &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank);
tmp_jsqr_context_queue_being_built &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, pConfigInjected->InjectedRank);
/* Set the JSQx bits for the selected rank */
tmp_JSQR_ContextQueueBeingBuilt |= ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank);
tmp_jsqr_context_queue_being_built |= ADC_JSQR_RK(pConfigInjected->InjectedChannel, pConfigInjected->InjectedRank);
/* Decrease channel count */
hadc->InjectionConfig.ChannelCount--;
/* 3. tmp_JSQR_ContextQueueBeingBuilt is fully built for this HAL_ADCEx_InjectedConfigChannel()
/* 3. tmp_jsqr_context_queue_being_built is fully built for this HAL_ADCEx_InjectedConfigChannel()
call, aggregate the setting to those already built during the previous
HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course) */
hadc->InjectionConfig.ContextQueue |= tmp_JSQR_ContextQueueBeingBuilt;
hadc->InjectionConfig.ContextQueue |= tmp_jsqr_context_queue_being_built;
/* 4. End of context setting: if this is the last channel set, then write context
into register JSQR and make it enter into queue */
@ -1838,12 +1842,12 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
{
/* If auto-injected mode is disabled: no constraint */
if (sConfigInjected->AutoInjectedConv == DISABLE)
if (pConfigInjected->AutoInjectedConv == DISABLE)
{
MODIFY_REG(hadc->Instance->CFGR,
ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext) |
ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)sConfigInjected->InjectedDiscontinuousConvMode));
ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)pConfigInjected->QueueInjectedContext) |
ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)pConfigInjected->InjectedDiscontinuousConvMode));
}
/* If auto-injected mode is enabled: Injected discontinuous setting is */
/* discarded. */
@ -1851,7 +1855,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
{
MODIFY_REG(hadc->Instance->CFGR,
ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext));
ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)pConfigInjected->QueueInjectedContext));
}
}
@ -1872,10 +1876,10 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
{
/* If injected group external triggers are disabled (set to injected */
/* software start): no constraint */
if ((sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
|| (sConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
if ((pConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
|| (pConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
{
if (sConfigInjected->AutoInjectedConv == ENABLE)
if (pConfigInjected->AutoInjectedConv == ENABLE)
{
SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
}
@ -1888,7 +1892,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
/* due to injected group external triggers enabled, error is reported. */
else
{
if (sConfigInjected->AutoInjectedConv == ENABLE)
if (pConfigInjected->AutoInjectedConv == ENABLE)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
@ -1901,13 +1905,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
}
}
if (sConfigInjected->InjecOversamplingMode == ENABLE)
if (pConfigInjected->InjecOversamplingMode == ENABLE)
{
assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio));
assert_param(IS_ADC_RIGHT_BIT_SHIFT(sConfigInjected->InjecOversampling.RightBitShift));
assert_param(IS_ADC_OVERSAMPLING_RATIO(pConfigInjected->InjecOversampling.Ratio));
assert_param(IS_ADC_RIGHT_BIT_SHIFT(pConfigInjected->InjecOversampling.RightBitShift));
/* JOVSE must be reset in case of triggered regular mode */
assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS) == (ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS)));
assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS)
== (ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS)));
/* Configuration of Injected Oversampler: */
/* - Oversampling Ratio */
@ -1919,8 +1924,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
ADC_CFGR2_OVSR |
ADC_CFGR2_OVSS,
ADC_CFGR2_JOVSE |
sConfigInjected->InjecOversampling.Ratio |
sConfigInjected->InjecOversampling.RightBitShift
pConfigInjected->InjecOversampling.Ratio |
pConfigInjected->InjecOversampling.RightBitShift
);
}
else
@ -1931,10 +1936,10 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
#if defined(ADC_SMPR1_SMPPLUS)
/* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */
if (sConfigInjected->InjectedSamplingTime == ADC_SAMPLETIME_3CYCLES_5)
if (pConfigInjected->InjectedSamplingTime == ADC_SAMPLETIME_3CYCLES_5)
{
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, LL_ADC_SAMPLINGTIME_2CYCLES_5);
LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfigInjected->InjectedChannel, LL_ADC_SAMPLINGTIME_2CYCLES_5);
/* Set ADC sampling time common configuration */
LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5);
@ -1942,27 +1947,29 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
else
{
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSamplingTime);
LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfigInjected->InjectedChannel,
pConfigInjected->InjectedSamplingTime);
/* Set ADC sampling time common configuration */
LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
}
#else
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSamplingTime);
#endif
LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfigInjected->InjectedChannel,
pConfigInjected->InjectedSamplingTime);
#endif /* ADC_SMPR1_SMPPLUS */
/* Configure the offset: offset enable/disable, channel, offset value */
/* Shift the offset with respect to the selected ADC resolution. */
/* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
tmp_offset_shifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, pConfigInjected->InjectedOffset);
if (sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
if (pConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
{
/* Set ADC selected offset number */
LL_ADC_SetOffset(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedChannel,
tmpOffsetShifted);
LL_ADC_SetOffset(hadc->Instance, pConfigInjected->InjectedOffsetNumber, pConfigInjected->InjectedChannel,
tmp_offset_shifted);
}
else
@ -1970,22 +1977,22 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
/* Scan each offset register to check if the selected channel is targeted. */
/* If this is the case, the corresponding offset number is disabled. */
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
}
@ -1999,16 +2006,19 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
{
/* Set mode single-ended or differential input of the selected ADC channel */
LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSingleDiff);
LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfigInjected->InjectedChannel, pConfigInjected->InjectedSingleDiff);
/* Configuration of differential mode */
/* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
if (sConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED)
if (pConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED)
{
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance,
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfigInjected->InjectedChannel)
+ 1UL) & 0x1FUL)), sConfigInjected->InjectedSamplingTime);
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
(__LL_ADC_CHANNEL_TO_DECIMAL_NB(
(uint32_t)pConfigInjected->InjectedChannel)
+ 1UL) & 0x1FUL)),
pConfigInjected->InjectedSamplingTime);
}
}
@ -2019,13 +2029,13 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
/* Note: these internal measurement paths can be disabled using */
/* HAL_ADC_DeInit(). */
if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfigInjected->InjectedChannel))
if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfigInjected->InjectedChannel))
{
tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
/* If the requested internal measurement path has already been enabled, */
/* bypass the configuration processing. */
if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR)
if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR)
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
{
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
@ -2038,14 +2048,15 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (((SystemCoreClock / (100000UL * 2UL)) + 1UL) + 1UL));
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL)
* (((SystemCoreClock / (100000UL * 2UL)) + 1UL) + 1UL));
while (wait_loop_index != 0UL)
{
wait_loop_index--;
}
}
}
else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)
else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
{
if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
@ -2054,7 +2065,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
}
}
else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)
else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
{
if (ADC_VREFINT_INSTANCE(hadc))
@ -2090,35 +2101,35 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
* @note To move back configuration from multimode to single mode, ADC must
* be reset (using function HAL_ADC_Init() ).
* @param hadc Master ADC handle
* @param multimode Structure of ADC multimode configuration
* @param pMultimode Structure of ADC multimode configuration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode)
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, const ADC_MultiModeTypeDef *pMultimode)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
ADC_Common_TypeDef *tmpADC_Common;
ADC_HandleTypeDef tmphadcSlave;
uint32_t tmphadcSlave_conversion_on_going;
ADC_HandleTypeDef tmp_hadc_slave;
uint32_t tmp_hadc_slave_conversion_on_going;
/* Check the parameters */
assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
assert_param(IS_ADC_MULTIMODE(multimode->Mode));
if (multimode->Mode != ADC_MODE_INDEPENDENT)
assert_param(IS_ADC_MULTIMODE(pMultimode->Mode));
if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
{
assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(multimode->DMAAccessMode));
assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(pMultimode->DMAAccessMode));
assert_param(IS_ADC_SAMPLING_DELAY(pMultimode->TwoSamplingDelay));
}
/* Process locked */
__HAL_LOCK(hadc);
/* Temporary handle minimum initialization */
__HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
ADC_CLEAR_ERRORCODE(&tmphadcSlave);
__HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
if (tmphadcSlave.Instance == NULL)
if (tmp_hadc_slave.Instance == NULL)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
@ -2134,9 +2145,9 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_
/* conversion on going on regular group: */
/* - Multimode DMA configuration */
/* - Multimode DMA mode */
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
&& (tmphadcSlave_conversion_on_going == 0UL))
&& (tmp_hadc_slave_conversion_on_going == 0UL))
{
/* Pointer to the common control register */
tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
@ -2144,10 +2155,10 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_
/* If multimode is selected, configure all multimode parameters. */
/* Otherwise, reset multimode parameters (can be used in case of */
/* transition from multimode to independent mode). */
if (multimode->Mode != ADC_MODE_INDEPENDENT)
if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
{
MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG,
multimode->DMAAccessMode |
pMultimode->DMAAccessMode |
ADC_CCR_MULTI_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
/* Parameters that can be updated only when ADC is disabled: */
@ -2165,8 +2176,8 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_
MODIFY_REG(tmpADC_Common->CCR,
ADC_CCR_DUAL |
ADC_CCR_DELAY,
multimode->Mode |
multimode->TwoSamplingDelay
pMultimode->Mode |
pMultimode->TwoSamplingDelay
);
}
}

51
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_can.c
View File

@ -33,7 +33,7 @@
(++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE()
(++) Configure CAN pins
(+++) Enable the clock for the CAN GPIOs
(+++) Configure CAN pins as alternate function open-drain
(+++) Configure CAN pins as alternate function
(++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification())
(+++) Configure the CAN interrupt priority using
HAL_NVIC_SetPriority()
@ -235,6 +235,7 @@
* @{
*/
#define CAN_TIMEOUT_VALUE 10U
#define CAN_WAKEUP_TIMEOUT_COUNTER 1000000U
/**
* @}
*/
@ -248,8 +249,8 @@
*/
/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
@ -328,7 +329,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
/* Init the low level hardware: CLOCK, NVIC */
HAL_CAN_MspInit(hcan);
}
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
/* Request initialisation */
SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
@ -482,7 +483,7 @@ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan)
#else
/* DeInit the low level hardware: CLOCK, NVIC */
HAL_CAN_MspDeInit(hcan);
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
/* Reset the CAN peripheral */
SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET);
@ -814,8 +815,8 @@ HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_Ca
*/
/** @defgroup CAN_Exported_Functions_Group2 Configuration functions
* @brief Configuration functions.
*
* @brief Configuration functions.
*
@verbatim
==============================================================================
##### Configuration functions #####
@ -868,7 +869,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_Filter
/* Check the parameters */
assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));
#endif
#endif /* CAN3 */
/* Initialisation mode for the filter */
SET_BIT(can_ip->FMR, CAN_FMR_FINIT);
@ -878,7 +879,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_Filter
CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB);
SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);
#endif
#endif /* CAN3 */
/* Convert filter number into bit position */
filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU);
@ -970,8 +971,8 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_Filter
*/
/** @defgroup CAN_Exported_Functions_Group3 Control functions
* @brief Control functions
*
* @brief Control functions
*
@verbatim
==============================================================================
##### Control functions #####
@ -1143,7 +1144,6 @@ HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan)
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
{
__IO uint32_t count = 0;
uint32_t timeout = 1000000U;
HAL_CAN_StateTypeDef state = hcan->State;
if ((state == HAL_CAN_STATE_READY) ||
@ -1159,15 +1159,14 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
count++;
/* Check if timeout is reached */
if (count > timeout)
if (count > CAN_WAKEUP_TIMEOUT_COUNTER)
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
return HAL_ERROR;
}
}
while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U);
} while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U);
/* Return function status */
return HAL_OK;
@ -1524,7 +1523,15 @@ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo,
hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;
}
pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR);
pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U)
{
/* Truncate DLC to 8 if received field is over range */
pHeader->DLC = 8U;
}
else
{
pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
}
pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos;
pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos;
@ -1600,8 +1607,8 @@ uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFi
*/
/** @defgroup CAN_Exported_Functions_Group4 Interrupts management
* @brief Interrupts management
*
* @brief Interrupts management
*
@verbatim
==============================================================================
##### Interrupts management #####
@ -2066,8 +2073,8 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
*/
/** @defgroup CAN_Exported_Functions_Group5 Callback functions
* @brief CAN Callback functions
*
* @brief CAN Callback functions
*
@verbatim
==============================================================================
##### Callback functions #####
@ -2316,8 +2323,8 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
*/
/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions
* @brief CAN Peripheral State functions
*
* @brief CAN Peripheral State functions
*
@verbatim
==============================================================================
##### Peripheral State and Error functions #####

80
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c
View File

@ -451,6 +451,37 @@ void HAL_MPU_Disable(void)
MPU->CTRL = 0;
}
/**
* @brief Enable the MPU Region.
* @retval None
*/
void HAL_MPU_EnableRegion(uint32_t RegionNumber)
{
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
/* Set the Region number */
MPU->RNR = RegionNumber;
/* Enable the Region */
SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
}
/**
* @brief Disable the MPU Region.
* @retval None
*/
void HAL_MPU_DisableRegion(uint32_t RegionNumber)
{
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
/* Set the Region number */
MPU->RNR = RegionNumber;
/* Disable the Region */
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
}
/**
* @brief Initialize and configure the Region and the memory to be protected.
@ -463,38 +494,31 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
/* Set the Region number */
MPU->RNR = MPU_Init->Number;
if ((MPU_Init->Enable) != RESET)
{
/* Check the parameters */
assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
/* Disable the Region */
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
MPU->RBAR = MPU_Init->BaseAddress;
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
}
else
{
MPU->RBAR = 0x00;
MPU->RASR = 0x00;
}
/* Apply configuration */
MPU->RBAR = MPU_Init->BaseAddress;
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
}
#endif /* __MPU_PRESENT */

10
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc.c
View File

@ -199,9 +199,15 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
/* Reset CRC calculation unit */
__HAL_CRC_DR_RESET(hcrc);
#if defined(CRC_IDR32BITSLENGTH_SUPPORT)
/* Reset IDR register content */
CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
__HAL_CRC_SET_IDR(hcrc, 0);
#else
/* Reset IDR register content */
CLEAR_REG(hcrc->Instance->IDR);
#endif /* CRC_IDR32BITSLENGTH_SUPPORT */
/* DeInit the low level hardware */
HAL_CRC_MspDeInit(hcrc);
@ -403,7 +409,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t
* @param hcrc CRC handle
* @retval HAL state
*/
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc)
{
/* Return CRC handle state */
return hcrc->State;

79
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc_ex.c
View File

@ -94,44 +94,53 @@ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol
/* Check the parameters */
assert_param(IS_CRC_POL_LENGTH(PolyLength));
/* check polynomial definition vs polynomial size:
* polynomial length must be aligned with polynomial
* definition. HAL_ERROR is reported if Pol degree is
* larger than that indicated by PolyLength.
* Look for MSB position: msb will contain the degree of
* the second to the largest polynomial member. E.g., for
* X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
/* Ensure that the generating polynomial is odd */
if ((Pol & (uint32_t)(0x1U)) == 0U)
{
status = HAL_ERROR;
}
switch (PolyLength)
else
{
case CRC_POLYLENGTH_7B:
if (msb >= HAL_CRC_LENGTH_7B)
{
status = HAL_ERROR;
}
break;
case CRC_POLYLENGTH_8B:
if (msb >= HAL_CRC_LENGTH_8B)
{
status = HAL_ERROR;
}
break;
case CRC_POLYLENGTH_16B:
if (msb >= HAL_CRC_LENGTH_16B)
{
status = HAL_ERROR;
}
break;
/* check polynomial definition vs polynomial size:
* polynomial length must be aligned with polynomial
* definition. HAL_ERROR is reported if Pol degree is
* larger than that indicated by PolyLength.
* Look for MSB position: msb will contain the degree of
* the second to the largest polynomial member. E.g., for
* X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
{
}
case CRC_POLYLENGTH_32B:
/* no polynomial definition vs. polynomial length issue possible */
break;
default:
status = HAL_ERROR;
break;
switch (PolyLength)
{
case CRC_POLYLENGTH_7B:
if (msb >= HAL_CRC_LENGTH_7B)
{
status = HAL_ERROR;
}
break;
case CRC_POLYLENGTH_8B:
if (msb >= HAL_CRC_LENGTH_8B)
{
status = HAL_ERROR;
}
break;
case CRC_POLYLENGTH_16B:
if (msb >= HAL_CRC_LENGTH_16B)
{
status = HAL_ERROR;
}
break;
case CRC_POLYLENGTH_32B:
/* no polynomial definition vs. polynomial length issue possible */
break;
default:
status = HAL_ERROR;
break;
}
}
if (status == HAL_OK)
{
@ -201,8 +210,6 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_
}
/**
* @}
*/

48
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac.c
View File

@ -171,14 +171,14 @@
A DMA1 request can be generated when an external trigger (but not a software trigger)
occurs if DMA1 requests are enabled using HAL_DAC_Start_DMA().
DMA requests are mapped as following:
(#) When DMAMUX is NOT present:
(#) When DMAMUX is NOT present:
DMA1 requests are mapped as following:
(+) DAC channel1 mapped on DMA1 request 6 / channel3
(+) DAC channel2 mapped on DMA1 request 5 / channel4
DMA2 requests are mapped as following:
(+) DAC channel1 mapped on DMA2 request 3 / channel4
(+) DAC channel2 mapped on DMA2 request 3 / channel5
(#) When DMAMUX is present:
(#) When DMAMUX is present:
(+) DAC channel1 mapped on DMA1/DMA2 request 6 (can be any DMA channel)
(+) DAC channel2 mapped on DMA1/DMA2 request 7 (can be any DMA channel)
@ -264,7 +264,7 @@
and a pointer to the user callback function.
Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
weak (overridden) function. It allows to reset following callbacks:
(+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
(+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
(+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
@ -279,9 +279,9 @@
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
all callbacks are reset to the corresponding legacy weak (overridden) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the HAL_DAC_Init
reset to the legacy weak (overridden) functions in the HAL_DAC_Init
and HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
@ -296,7 +296,7 @@
When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
and weak (overridden) callbacks are used.
*** DAC HAL driver macros list ***
=============================================
@ -396,7 +396,7 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \
defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx)
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx)
hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
@ -405,7 +405,7 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
/* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
/* STM32L4P5xx STM32L4Q5xx */
/* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */
if (hdac->MspInitCallback == NULL)
{
hdac->MspInitCallback = HAL_DAC_MspInit;
@ -1249,13 +1249,17 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
{
/* Update error code */
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
/* New check to avoid false timeout detection in case of preemption */
if(((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
{
/* Update error code */
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
/* Change the DMA state */
hdac->State = HAL_DAC_STATE_TIMEOUT;
/* Change the DMA state */
hdac->State = HAL_DAC_STATE_TIMEOUT;
return HAL_TIMEOUT;
return HAL_TIMEOUT;
}
}
}
HAL_Delay(1);
@ -1271,13 +1275,17 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
{
/* Update error code */
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
/* New check to avoid false timeout detection in case of preemption */
if(((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
{
/* Update error code */
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
/* Change the DMA state */
hdac->State = HAL_DAC_STATE_TIMEOUT;
/* Change the DMA state */
hdac->State = HAL_DAC_STATE_TIMEOUT;
return HAL_TIMEOUT;
return HAL_TIMEOUT;
}
}
}
HAL_Delay(1U);
@ -1437,7 +1445,7 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User DAC Callback
* To be used instead of the weak (surcharged) predefined callback
* To be used instead of the weak (overridden) predefined callback
* @param hdac DAC handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
@ -1546,7 +1554,7 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call
/**
* @brief Unregister a User DAC Callback
* DAC Callback is redirected to the weak (surcharged) predefined callback
* DAC Callback is redirected to the weak (overridden) predefined callback
* @param hdac DAC handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:

13
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac_ex.c
View File

@ -425,10 +425,15 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo
if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL)
{
/* OPAMP_CSR_OUTCAL is actually one value more */
trimmingvalue++;
/* Set right trimming */
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
/* Check trimming value below maximum */
if (trimmingvalue < 0x1FU)
{
/* Trimming is actually one value more */
trimmingvalue++;
/* Set right trimming */
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
}
}
/* Disable the selected DAC channel calibration */

186
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c
View File

@ -156,7 +156,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
uint32_t tmp;
/* Check the DMA handle allocation */
if(hdma == NULL)
if (hdma == NULL)
{
return HAL_ERROR;
}
@ -213,7 +213,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
*/
DMA_CalcDMAMUXChannelBaseAndMask(hdma);
if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
{
/* if memory to memory force the request to 0*/
hdma->Init.Request = DMA_REQUEST_MEM2MEM;
@ -225,7 +225,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
if (((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
{
/* Initialize parameters for DMAMUX request generator :
DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
@ -249,7 +249,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
#if !defined (DMAMUX1)
/* Set request selection */
if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)
if (hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)
{
/* Write to DMA channel selection register */
if (DMA1 == hdma->DmaBaseAddress)
@ -258,7 +258,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));
/* Configure request selection for DMA1 Channelx */
DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex & 0x1cU));
DMA1_CSELR->CSELR |= (uint32_t)(hdma->Init.Request << (hdma->ChannelIndex & 0x1cU));
}
else /* DMA2 */
{
@ -266,13 +266,13 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));
/* Configure request selection for DMA2 Channelx */
DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex & 0x1cU));
DMA2_CSELR->CSELR |= (uint32_t)(hdma->Init.Request << (hdma->ChannelIndex & 0x1cU));
}
}
#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */
/* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */
/* STM32L496xx || STM32L4A6xx */
/* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */
/* STM32L496xx || STM32L4A6xx */
/* Initialise the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
@ -296,7 +296,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
{
/* Check the DMA handle allocation */
if (NULL == hdma )
if (NULL == hdma)
{
return HAL_ERROR;
}
@ -341,8 +341,8 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));
}
#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */
/* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */
/* STM32L496xx || STM32L4A6xx */
/* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */
/* STM32L496xx || STM32L4A6xx */
#if defined(DMAMUX1)
@ -358,7 +358,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
/* Reset Request generator parameters if any */
if(((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
if (((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
{
/* Initialize parameters for DMAMUX request generator :
DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
@ -438,7 +438,7 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui
/* Process locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State)
if (HAL_DMA_STATE_READY == hdma->State)
{
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
@ -481,7 +481,7 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
/* Process locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State)
if (HAL_DMA_STATE_READY == hdma->State)
{
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
@ -495,7 +495,7 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
/* Enable the transfer complete interrupt */
/* Enable the transfer Error interrupt */
if(NULL != hdma->XferHalfCpltCallback )
if (NULL != hdma->XferHalfCpltCallback)
{
/* Enable the Half transfer complete interrupt as well */
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
@ -509,13 +509,13 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
#ifdef DMAMUX1
/* Check if DMAMUX Synchronization is enabled*/
if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
{
/* Enable DMAMUX sync overrun IT*/
hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
}
if(hdma->DMAmuxRequestGen != 0U)
if (hdma->DMAmuxRequestGen != 0U)
{
/* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
/* enable the request gen overrun IT*/
@ -549,7 +549,7 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef status = HAL_OK;
/* Check the DMA peripheral state */
if(hdma->State != HAL_DMA_STATE_BUSY)
if (hdma->State != HAL_DMA_STATE_BUSY)
{
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
@ -578,7 +578,7 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(hdma->DMAmuxRequestGen != 0U)
if (hdma->DMAmuxRequestGen != 0U)
{
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
/* disable the request gen overrun IT*/
@ -610,7 +610,7 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{
HAL_StatusTypeDef status = HAL_OK;
if(HAL_DMA_STATE_BUSY != hdma->State)
if (HAL_DMA_STATE_BUSY != hdma->State)
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
@ -635,7 +635,7 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(hdma->DMAmuxRequestGen != 0U)
if (hdma->DMAmuxRequestGen != 0U)
{
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
/* disable the request gen overrun IT*/
@ -657,7 +657,7 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
__HAL_UNLOCK(hdma);
/* Call User Abort callback */
if(hdma->XferAbortCallback != NULL)
if (hdma->XferAbortCallback != NULL)
{
hdma->XferAbortCallback(hdma);
}
@ -678,7 +678,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
uint32_t temp;
uint32_t tickstart;
if(HAL_DMA_STATE_BUSY != hdma->State)
if (HAL_DMA_STATE_BUSY != hdma->State)
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
@ -708,9 +708,9 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
/* Get tick */
tickstart = HAL_GetTick();
while((hdma->DmaBaseAddress->ISR & temp) == 0U)
while ((hdma->DmaBaseAddress->ISR & temp) == 0U)
{
if((hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex& 0x1CU))) != 0U)
if ((hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U)
{
/* When a DMA transfer error occurs */
/* A hardware clear of its EN bits is performed */
@ -721,7 +721,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
hdma->ErrorCode = HAL_DMA_ERROR_TE;
/* Change the DMA state */
hdma->State= HAL_DMA_STATE_READY;
hdma->State = HAL_DMA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
@ -729,9 +729,9 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
return HAL_ERROR;
}
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
if (Timeout != HAL_MAX_DELAY)
{
if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
@ -749,10 +749,10 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
#if defined(DMAMUX1)
/*Check for DMAMUX Request generator (if used) overrun status */
if(hdma->DMAmuxRequestGen != 0U)
if (hdma->DMAmuxRequestGen != 0U)
{
/* if using DMAMUX request generator Check for DMAMUX request generator overrun */
if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
{
/* Disable the request gen overrun interrupt */
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
@ -766,7 +766,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
}
/* Check for DMAMUX Synchronization overrun */
if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
{
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
@ -776,10 +776,10 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
}
#endif /* DMAMUX1 */
if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
{
/* Clear the transfer complete flag */
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex& 0x1CU));
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU));
/* Process unlocked */
__HAL_UNLOCK(hdma);
@ -811,29 +811,29 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
/* Half Transfer Complete Interrupt management ******************************/
if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U))
{
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{
/* Disable the half transfer interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
}
/* Clear the half transfer complete flag */
hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU);
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{
/* Disable the half transfer interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
}
/* Clear the half transfer complete flag */
hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU);
/* DMA peripheral state is not updated in Half Transfer */
/* but in Transfer Complete case */
/* DMA peripheral state is not updated in Half Transfer */
/* but in Transfer Complete case */
if(hdma->XferHalfCpltCallback != NULL)
{
/* Half transfer callback */
hdma->XferHalfCpltCallback(hdma);
}
if (hdma->XferHalfCpltCallback != NULL)
{
/* Half transfer callback */
hdma->XferHalfCpltCallback(hdma);
}
}
/* Transfer Complete Interrupt management ***********************************/
else if (((flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TC) != 0U))
{
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{
/* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
/* Disable the transfer complete and error interrupt */
@ -849,7 +849,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
/* Process Unlocked */
__HAL_UNLOCK(hdma);
if(hdma->XferCpltCallback != NULL)
if (hdma->XferCpltCallback != NULL)
{
/* Transfer complete callback */
hdma->XferCpltCallback(hdma);
@ -895,40 +895,40 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
* the configuration information for the specified DMA Channel.
* @param CallbackID User Callback identifier
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
* @param pCallback pointer to private callbacsk function which has pointer to
* @param pCallback pointer to private callback function which has pointer to
* a DMA_HandleTypeDef structure as parameter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State)
if (HAL_DMA_STATE_READY == hdma->State)
{
switch (CallbackID)
{
case HAL_DMA_XFER_CPLT_CB_ID:
hdma->XferCpltCallback = pCallback;
break;
case HAL_DMA_XFER_CPLT_CB_ID:
hdma->XferCpltCallback = pCallback;
break;
case HAL_DMA_XFER_HALFCPLT_CB_ID:
hdma->XferHalfCpltCallback = pCallback;
break;
case HAL_DMA_XFER_HALFCPLT_CB_ID:
hdma->XferHalfCpltCallback = pCallback;
break;
case HAL_DMA_XFER_ERROR_CB_ID:
hdma->XferErrorCallback = pCallback;
break;
case HAL_DMA_XFER_ERROR_CB_ID:
hdma->XferErrorCallback = pCallback;
break;
case HAL_DMA_XFER_ABORT_CB_ID:
hdma->XferAbortCallback = pCallback;
break;
case HAL_DMA_XFER_ABORT_CB_ID:
hdma->XferAbortCallback = pCallback;
break;
default:
status = HAL_ERROR;
break;
default:
status = HAL_ERROR;
break;
}
}
else
@ -954,39 +954,39 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
/* Process locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State)
if (HAL_DMA_STATE_READY == hdma->State)
{
switch (CallbackID)
{
case HAL_DMA_XFER_CPLT_CB_ID:
hdma->XferCpltCallback = NULL;
break;
case HAL_DMA_XFER_CPLT_CB_ID:
hdma->XferCpltCallback = NULL;
break;
case HAL_DMA_XFER_HALFCPLT_CB_ID:
hdma->XferHalfCpltCallback = NULL;
break;
case HAL_DMA_XFER_HALFCPLT_CB_ID:
hdma->XferHalfCpltCallback = NULL;
break;
case HAL_DMA_XFER_ERROR_CB_ID:
hdma->XferErrorCallback = NULL;
break;
case HAL_DMA_XFER_ERROR_CB_ID:
hdma->XferErrorCallback = NULL;
break;
case HAL_DMA_XFER_ABORT_CB_ID:
hdma->XferAbortCallback = NULL;
break;
case HAL_DMA_XFER_ABORT_CB_ID:
hdma->XferAbortCallback = NULL;
break;
case HAL_DMA_XFER_ALL_CB_ID:
hdma->XferCpltCallback = NULL;
hdma->XferHalfCpltCallback = NULL;
hdma->XferErrorCallback = NULL;
hdma->XferAbortCallback = NULL;
break;
case HAL_DMA_XFER_ALL_CB_ID:
hdma->XferCpltCallback = NULL;
hdma->XferHalfCpltCallback = NULL;
hdma->XferErrorCallback = NULL;
hdma->XferAbortCallback = NULL;
break;
default:
status = HAL_ERROR;
break;
default:
status = HAL_ERROR;
break;
}
}
else
@ -1072,7 +1072,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(hdma->DMAmuxRequestGen != 0U)
if (hdma->DMAmuxRequestGen != 0U)
{
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
@ -1086,7 +1086,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
hdma->Instance->CNDTR = DataLength;
/* Memory to Peripheral */
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
{
/* Configure DMA Channel destination address */
hdma->Instance->CPAR = DstAddress;

64
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c
View File

@ -114,17 +114,17 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSy
assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));
/*Check if the DMA state is ready */
if(hdma->State == HAL_DMA_STATE_READY)
if (hdma->State == HAL_DMA_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hdma);
/* Set the new synchronization parameters (and keep the request ID filled during the Init)*/
MODIFY_REG( hdma->DMAmuxChannel->CCR, \
(~DMAMUX_CxCR_DMAREQ_ID) , \
MODIFY_REG(hdma->DMAmuxChannel->CCR, \
(~DMAMUX_CxCR_DMAREQ_ID), \
((pSyncConfig->SyncSignalID) << DMAMUX_CxCR_SYNC_ID_Pos) | ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \
pSyncConfig->SyncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \
((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos));
((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos));
/* Process UnLocked */
__HAL_UNLOCK(hdma);
@ -147,7 +147,7 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSy
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
@ -160,24 +160,24 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma,
/* check if the DMA state is ready
and DMA is using a DMAMUX request generator block
*/
if((hdma->State == HAL_DMA_STATE_READY) && (hdma->DMAmuxRequestGen != 0U))
if ((hdma->State == HAL_DMA_STATE_READY) && (hdma->DMAmuxRequestGen != 0U))
{
/* Process Locked */
__HAL_LOCK(hdma);
/* Set the request generator new parameters */
hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \
((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos)| \
pRequestGeneratorConfig->Polarity;
/* Process UnLocked */
__HAL_UNLOCK(hdma);
((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos) | \
pRequestGeneratorConfig->Polarity;
/* Process UnLocked */
__HAL_UNLOCK(hdma);
return HAL_OK;
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
@ -186,7 +186,7 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma,
* the configuration information for the specified DMA channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
@ -194,18 +194,18 @@ HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
/* check if the DMA state is ready
and DMA is using a DMAMUX request generator block
*/
if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
{
/* Enable the request generator*/
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE;
return HAL_OK;
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
@ -214,7 +214,7 @@ HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
* the configuration information for the specified DMA channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
@ -222,7 +222,7 @@ HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
/* check if the DMA state is ready
and DMA is using a DMAMUX request generator block
*/
if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
{
/* Disable the request generator*/
@ -245,7 +245,7 @@ HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
{
/* Check for DMAMUX Synchronization overrun */
if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
{
/* Disable the synchro overrun interrupt */
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
@ -256,17 +256,17 @@ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
if(hdma->XferErrorCallback != NULL)
if (hdma->XferErrorCallback != NULL)
{
/* Transfer error callback */
hdma->XferErrorCallback(hdma);
}
}
if(hdma->DMAmuxRequestGen != 0)
if (hdma->DMAmuxRequestGen != 0)
{
/* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */
if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
/* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */
if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
{
/* Disable the request gen overrun interrupt */
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
@ -277,7 +277,7 @@ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
if(hdma->XferErrorCallback != NULL)
if (hdma->XferErrorCallback != NULL)
{
/* Transfer error callback */
hdma->XferErrorCallback(hdma);

12
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c
View File

@ -64,7 +64,7 @@
(++) Provide exiting handle as parameter.
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine().
(++) Provide exiting handle as parameter.
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
@ -75,7 +75,7 @@
(#) Get interrupt pending bit using HAL_EXTI_GetPending().
(#) Clear interrupt pending bit using HAL_EXTI_GetPending().
(#) Clear interrupt pending bit using HAL_EXTI_ClearPending().
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
@ -346,7 +346,7 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[linepos >> 2u];
pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);
pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EXTICR1_EXTI0;
}
}
@ -538,6 +538,9 @@ uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
uint32_t maskline;
uint32_t offset;
/* Prevent unused argument(s) compilation warning */
UNUSED(Edge);
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
@ -572,6 +575,9 @@ void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
uint32_t maskline;
uint32_t offset;
/* Prevent unused argument(s) compilation warning */
UNUSED(Edge);
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));

8
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c
View File

@ -301,7 +301,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
* @brief De-initialize the GPIOx peripheral registers to their default reset values.
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
* @param GPIO_Pin specifies the port bit to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval None
*/
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
@ -387,7 +387,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
* @brief Read the specified input port pin.
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
* @param GPIO_Pin specifies the port bit to read.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
@ -417,7 +417,7 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
*
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
* @param GPIO_Pin specifies the port bit to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @param PinState specifies the value to be written to the selected bit.
* This parameter can be one of the GPIO_PinState enum values:
* @arg GPIO_PIN_RESET: to clear the port pin
@ -468,7 +468,7 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
* until the next reset.
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
* @param GPIO_Pin specifies the port bits to be locked.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval None
*/
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)

874
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c
View File

File diff suppressed because it is too large Load Diff

3
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c
View File

@ -126,7 +126,8 @@
The timeout value is multiplied by 1000 to be converted in milliseconds.
LSI startup time is also considered here by adding LSI_STARTUP_TIME
converted in milliseconds. */
#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL))
#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / (LSI_VALUE / 128U)) + \
((LSI_STARTUP_TIME / 1000UL) + 1UL))
#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)
/**
* @}

8
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c
View File

@ -187,7 +187,7 @@ void HAL_PWR_DisableBkUpAccess(void)
=========================================
[..]
(+) Entry:
The Sleep mode / Low-power Sleep mode is entered thru HAL_PWR_EnterSLEEPMode() API
The Sleep mode / Low-power Sleep mode is entered through HAL_PWR_EnterSLEEPMode() API
in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered.
(++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
(++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
@ -209,7 +209,7 @@ void HAL_PWR_DisableBkUpAccess(void)
===============================
[..]
(+) Entry:
The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's:
The Stop 0, Stop 1 or Stop 2 modes are entered through the following API's:
(++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode().
(++) HAL_PWREx_EnterSTOP2Mode() for mode 2.
(+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
@ -243,7 +243,7 @@ void HAL_PWR_DisableBkUpAccess(void)
and Standby circuitry.
(++) Entry:
(+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API.
(+++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API.
SRAM1 and register contents are lost except for registers in the Backup domain and
Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
@ -264,7 +264,7 @@ void HAL_PWR_DisableBkUpAccess(void)
SRAM and registers contents are lost except for backup domain registers.
(+) Entry:
The Shutdown mode is entered thru HAL_PWREx_EnterSHUTDOWNMode() API.
The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API.
(+) Exit:
(++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,

4
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c
View File

@ -272,7 +272,7 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
/**
* @brief Enable battery charging.
* When VDD is present, charge the external battery on VBAT thru an internal resistor.
* When VDD is present, charge the external battery on VBAT through an internal resistor.
* @param ResistorSelection specifies the resistor impedance.
* This parameter can be one of the following values:
* @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor
@ -974,7 +974,7 @@ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
/* Configure EXTI 35 to 38 interrupts if so required:
scan thru PVMType to detect which PVMx is set and
scan through PVMType to detect which PVMx is set and
configure the corresponding EXTI line accordingly. */
switch (sConfigPVM->PVMType)
{

10
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c
View File

@ -398,6 +398,8 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @note If HSE failed to start, HSE should be disabled before recalling
HAL_RCC_OscConfig().
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
@ -1318,7 +1320,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
* @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
* @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_PLLCLK main PLL clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
@ -1852,7 +1854,11 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
/* MSI 8Mhz */
latency = FLASH_LATENCY_1; /* 1WS */
}
/* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
else
{
/* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
/* nothing to do */
}
}
#endif
}

6
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c
View File

@ -675,6 +675,10 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
status = ret;
}
}
else
{
/* nothing to do */
}
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
@ -2542,7 +2546,7 @@ void HAL_RCCEx_OCTOSPIDelayConfig(uint32_t Delay1, uint32_t Delay2)
(+++) Default values can be set for frequency Error Measurement (reload and error limit)
and also HSI48 oscillator smooth trimming.
(+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
directly reload value with target and sychronization frequencies values
directly reload value with target and synchronization frequencies values
(##) Call function HAL_RCCEx_CRSConfig which
(+++) Resets CRS registers to their default values.
(+++) Configures CRS registers with synchronization configuration

484
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c
View File

File diff suppressed because it is too large Load Diff

2
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c
View File

@ -76,7 +76,7 @@
* the configuration information for the specified SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)
HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi)
{
__IO uint32_t tmpreg;
uint8_t count = 0U;

7896
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c
View File

File diff suppressed because it is too large Load Diff

2841
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c
View File

File diff suppressed because it is too large Load Diff