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AEK_8220_Libraries
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firmware_vhdl_psi_multi_stream_daq
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firmware_vhdl_psi_multi_str…
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hdl
History
Oliver Bruendler
df29e19f6d
TIMING: Optimized timing on critical path between input FIFO and DMA
...
Added pipeline stage after FIFO to reduce requirements of fall-through interface
2019-11-07 07:46:37 +01:00
..
psi_ms_daq_axi_if.vhd
DEVEL: First open source release
2019-08-02 10:03:58 +02:00
psi_ms_daq_axi.vhd
DEVEL: First open source release
2019-08-02 10:03:58 +02:00
psi_ms_daq_daq_dma.vhd
BUGFIX: Made design working for 1 stream
2019-10-30 11:02:11 +01:00
psi_ms_daq_daq_sm.vhd
BUGFIX: Made design working for 1 stream
2019-10-30 11:02:11 +01:00
psi_ms_daq_input.vhd
TIMING: Optimized timing on critical path between input FIFO and DMA
2019-11-07 07:46:37 +01:00
psi_ms_daq_pkg.vhd
DEVEL: First open source release
2019-08-02 10:03:58 +02:00
psi_ms_daq_reg_axi.vhd
BUGFIX: Made design working for 1 stream
2019-10-30 11:02:11 +01:00
