firmware_vhdl_psi_multi_stream_daq

Files

T

History

Oliver Bruendler df29e19f6d TIMING: Optimized timing on critical path between input FIFO and DMA

Added pipeline stage after FIFO to reduce requirements of fall-through interface

2019-11-07 07:46:37 +01:00

psi_ms_daq_axi_if.vhd

2019-08-02 10:03:58 +02:00

psi_ms_daq_axi.vhd

2019-08-02 10:03:58 +02:00

psi_ms_daq_daq_dma.vhd

2019-10-30 11:02:11 +01:00

psi_ms_daq_daq_sm.vhd

2019-10-30 11:02:11 +01:00

psi_ms_daq_input.vhd

2019-11-07 07:46:37 +01:00

psi_ms_daq_pkg.vhd

2019-08-02 10:03:58 +02:00

psi_ms_daq_reg_axi.vhd

2019-10-30 11:02:11 +01:00