Adapt interrupt generation logic to solve problem with missing interrupts.

Adaptions in timeout handling at the stream input stage

hdl/psi_ms_daq_daq_sm.vhd

@@ -576,11 +576,12 @@ begin
     if (unsigned(r.TfDoneCnt) /= 0) and (IrqFifoEmpty = '0') then
       v.IrqFifoRead := '1';
       v.TfDoneCnt   := std_logic_vector(unsigned(v.TfDoneCnt) - 1);
-      -- Generate IRQ if required
-      if IrqFifoGenIrq = '1' then
-        v.StrIrq(to_integer(unsigned(IrqFifoStream)))     := '1';
-        v.StrLastWin(to_integer(unsigned(IrqFifoStream))) := std_logic_vector(resize(unsigned(IrqLastWinNr), 5));
-      end if;
+    end if;
+
+    -- Generate IRQ if required
+    if IrqFifoGenIrq = '1' and r.IrqFifoRead = '1' then
+      v.StrIrq(to_integer(unsigned(IrqFifoStream)))     := '1';
+      v.StrLastWin(to_integer(unsigned(IrqFifoStream))) := std_logic_vector(resize(unsigned(IrqLastWinNr), 5));
     end if;
 
     -- *** Assign to signal ***

hdl/psi_ms_daq_input.vhd

@@ -508,7 +508,7 @@ begin
       in_rdy_o  => DataFifo_InRdy,
       out_dat_o => DataFifo_PlData,
       out_vld_o => DataFifo_PlVld,
-      out_rdy_o => DataFifo_PlRdy,
+      out_rdy_i => DataFifo_PlRdy,
       out_lvl_o => DataFifo_Level
     );
 
@@ -563,7 +563,7 @@ begin
         in_empty_o => TsFifo_Empty,
         out_dat_o  => TsFifo_RdData,
         out_vld_o  => Ts_Vld_I,
-        out_rdy_o  => Ts_Rdy
+        out_rdy_i  => Ts_Rdy
       );
     Ts_Vld  <= Ts_Vld_I;
     -- Replace data by 0xFF... if no valid timestamp is available