DEVEL: Use AXI slave from psi_common instead of legacy version

Changelog.md

@@ -1,3 +1,9 @@
+## 1.1.0
+* Features
+  * Added deependency resolution script
+* Changes
+  * Use AXI slave from *psi\_common* instead of legacy version
+
 ## 1.0.0
 * First release, tested on HW
 

README.md

@@ -16,21 +16,25 @@ The rules that apply for working in this directory are described in:
 ## Changelog
 See [Changelog](Changelog.md)
 
+<!-- DO NOT CHANGE FORMAT: this section is parsed to resolve dependencies -->
+
 # Dependencies
-## Library
 Directory structure as given below
-* Firmware
-  * TCL
-    * [PsiSim](https://github.com/paulscherrerinstitute/PsiSim) (2.1.0 or higher, for development only)
-  * VHDL
-    * [psi\_common](https://github.com/paulscherrerinstitute/psi_common) (2.4.0 or higher)
-    * [psi\_tb](https://github.com/paulscherrerinstitute/psi_tb) (2.2.2 or higher, for development only)
-    * [**psi\_multi\_stream\_daq**](https://git.psi.ch/GFA/Libraries/Firmware/VHDL/psi_multi_stream_daq)
-  * VivadoIp
-    * [axi\_slave\_ipif\_package](https://git.psi.ch/GFA/Libraries/Firmware/VivadoIp/axi_slave_ipif_package) (1.0.2 or higher)
-
-## External
-None
+* TCL
+  * [PsiSim](https://github.com/paulscherrerinstitute/PsiSim) (2.1.0 or higher, for development only)
+* VHDL
+  * [psi\_common](https://github.com/paulscherrerinstitute/psi_common) (2.5.0 or higher)
+  * [psi\_tb](https://github.com/paulscherrerinstitute/psi_tb) (2.2.2 or higher, for development only)
+  * [**psi\_multi\_stream\_daq**](https://git.psi.ch/GFA/Libraries/Firmware/VHDL/psi_multi_stream_daq)
 
+<!-- END OF PARSED SECTION -->
+
+Dependencies can also be checked out using the python script *scripts/dependencies.py*. For details, refer to the help of the script:
+
+```
+python dependencies.py -help
+```
+
+Note that the [dependencies package](https://github.com/paulscherrerinstitute/PsiFpgaLibDependencies) must be installed in order to run the script.
 
 

hdl/psi_ms_daq_reg_axi.vhd

@@ -10,7 +10,6 @@ library work;
 	use work.psi_common_array_pkg.all;
 	use work.psi_common_logic_pkg.all;
 	use work.psi_ms_daq_pkg.all;
-	use work.axi_slave_ipif_package.all;
 
 ------------------------------------------------------------------------------
 -- Entity Declaration
@@ -147,8 +146,8 @@ architecture rtl of psi_ms_daq_reg_axi is
 	signal AccWr				: std_logic_vector(3 downto 0);
 	signal AccWrData			: std_logic_vector(31 downto 0);
 	signal AccRdData			: std_logic_vector(31 downto 0);
-	signal RegWrVal				: slv_reg_type(0 to 15);
-	signal RegRdVal				: slv_reg_type(0 to 15)	:= (others => (others => '0'));
+	signal RegWrVal				: t_aslv32(0 to 15);
+	signal RegRdVal				: t_aslv32(0 to 15)	:= (others => (others => '0'));
 	signal RegWr				: std_logic_vector(15 downto 0);
 begin
 	A_Axi_Areset <= not S_Axi_Aresetn;
@@ -334,21 +333,16 @@ begin
 	--------------------------------------------	
 	
 	-- *** AXI Interface ***
-	i_axi : entity work.axi_slave_ipif_reg_mem
+	i_axi : entity work.psi_common_axi_slave_ipif
 		generic map (
-			C_NUM_REG				=> 16,
-			C_RESET_VAL				=> (0 => (others => '0'), 	 1 => (others => '0'), 	 2 => (others => '0'), 	 3 => (others => '0'),
+			NumReg_g				=> 16,
+			ResetVal_g				=> (0 => (others => '0'), 	 1 => (others => '0'), 	 2 => (others => '0'), 	 3 => (others => '0'),
 										4 => (others => '0'), 	 5 => (others => '0'), 	 6 => (others => '0'), 	 7 => (others => '0'),
 										8 => (others => '0'), 	 9 => (others => '0'), 	10 => (others => '0'),	11 => (others => '0'),
 										12 => (others => '0'), 	13 => (others => '0'), 	14 => (others => '0'), 	15 => (others => '0')),
-			C_S_AXI_ID_WIDTH		=> AxiSlaveIdWidth_g,
-			C_S_AXI_DATA_WIDTH		=> 32,
-			C_S_AXI_ADDR_WIDTH		=> 16,
-			C_S_AXI_ARUSER_WIDTH	=> 0,
-			C_S_AXI_RUSER_WIDTH		=> 0,
-			C_S_AXI_AWUSER_WIDTH	=> 0,
-			C_S_AXI_WUSER_WIDTH		=> 0,
-			C_S_AXI_BUSER_WIDTH		=> 0
+			UseMem_g				=> true,
+			AxiIdWidth_g			=> AxiSlaveIdWidth_g,
+			AxiAddrWidth_g			=> 16
 		)
 		port map (
 			s_axi_aclk				=> S_Axi_Aclk,
@@ -361,16 +355,12 @@ begin
 			s_axi_arlock			=> S_Axi_ArLock,
 			s_axi_arcache			=> S_Axi_ArCache,
 			s_axi_arprot			=> S_Axi_ArProt,
-			s_axi_arqos				=> (others => '0'),
-			s_axi_arregion			=> (others => '0'),
-			s_axi_aruser			=> (others => '0'),
 			s_axi_arvalid			=> S_Axi_ArValid,
 			s_axi_arready			=> S_Axi_ArReady,
 			s_axi_rid				=> S_Axi_RId,
 			s_axi_rdata				=> S_Axi_RData,
 			s_axi_rresp				=> S_Axi_RResp,
 			s_axi_rlast				=> S_Axi_RLast,
-			s_axi_ruser				=> open,
 			s_axi_rvalid			=> S_Axi_RValid,
 			s_axi_rready			=> S_Axi_RReady,
 			s_axi_awid				=> S_Axi_AwId,
@@ -381,20 +371,15 @@ begin
 			s_axi_awlock			=> S_Axi_AwLock,
 			s_axi_awcache			=> S_Axi_AwCache,
 			s_axi_awprot			=> S_Axi_AwProt,
-			s_axi_awqos				=> (others => '0'),
-			s_axi_awregion			=> (others => '0'),
-			s_axi_awuser			=> (others => '0'),
 			s_axi_awvalid			=> S_Axi_AwValid,
 			s_axi_awready			=> S_Axi_AwReady,
 			s_axi_wdata				=> S_Axi_WData,
 			s_axi_wstrb				=> S_Axi_WStrb,
 			s_axi_wlast				=> S_Axi_WLast,
-			s_axi_wuser				=> (others => '0'),
 			s_axi_wvalid 			=> S_Axi_WValid,
 			s_axi_wready			=> S_Axi_WReady,
 			s_axi_bid				=> S_Axi_BId,
 			s_axi_bresp				=> S_Axi_BResp,
-			s_axi_buser				=> open,
 			s_axi_bvalid			=> S_Axi_BValid,
 			s_axi_bready			=> S_Axi_BReady,
 			o_reg_rd				=> open,

scripts/ciFlow.py

@@ -0,0 +1,26 @@
+##############################################################################
+#  Copyright (c) 2018 by Paul Scherrer Institute, Switzerland
+#  All rights reserved.
+#  Authors: Oliver Bruendler
+##############################################################################
+import os
+
+THIS_DIR = os.path.dirname(os.path.abspath(__file__))
+
+os.chdir(THIS_DIR + "/../sim")
+
+os.system("vsim -batch -do ci.do -logfile Transcript.transcript")
+
+with open("Transcript.transcript") as f:
+	content = f.read()
+	
+#Expected Errors
+if "###ERROR###" in content:
+	exit(-1)
+#Unexpected Errors
+if "SIMULATIONS COMPLETED SUCCESSFULLY" not in content:
+	exit(-2)
+	
+	
+#Success
+exit(0)

scripts/dependencies.py

@@ -0,0 +1,10 @@
+from PsiFpgaLibDependencies import *
+import sys
+import os
+
+THIS_DIR = os.path.dirname(os.path.abspath(__file__))
+
+dependencies = Parse.FromReadme(THIS_DIR + "/../README.md")
+repo = os.path.abspath(THIS_DIR + "/..")
+
+Actions.ExecMain(repo, dependencies)

sim/.gitignore

@@ -12,3 +12,4 @@
 #Ignore transcripts
 *.transcript
 *.wlf
+transcript

sim/ci.do

@@ -0,0 +1,9 @@
+##############################################################################
+#  Copyright (c) 2018 by Paul Scherrer Institute, Switzerland
+#  All rights reserved.
+#  Authors: Oliver Bruendler
+##############################################################################
+
+onerror {exit}
+source run.tcl
+quit

sim/config.tcl

@@ -32,7 +32,8 @@ add_sources $LibPath {
 	psi_common/hdl/psi_common_axi_master_simple.vhd \
 	psi_common/hdl/psi_common_wconv_n2xn.vhd \
 	psi_common/hdl/psi_common_axi_master_full.vhd \
-	../VivadoIp/axi_slave_ipif_package/hdl/axi_slave_ipif_package.vhd \
+	psi_common/hdl/psi_common_pl_stage.vhd \
+	psi_common/hdl/psi_common_axi_slave_ipif.vhd \
 } -tag lib
 
 # project sources

tb/psi_ms_daq_axi/psi_ms_daq_axi_tb_str0_pkg.vhd

@@ -119,6 +119,7 @@ package body psi_ms_daq_axi_tb_str0_pkg is
 							signal	rsp			: in	axi_sm_r) is
 		variable v : integer;
 		variable curwin : integer;
+		variable lastwin : integer;
 		variable wincnt : integer;
 		variable winstart, winend : integer;
 		variable winlast : integer;
@@ -132,14 +133,16 @@ package body psi_ms_daq_axi_tb_str0_pkg is
 		print("MAXLVL: " & to_string(v), PrintStr0_c);
 		HlGetCurWin(0, clk, rqst, rsp, curwin);
 		print("CURWIN: " & to_string(curwin), PrintStr0_c);
+		HlGetLastWin(0, clk, rqst, rsp, lastwin);
+		print("LASTWIN: " & to_string(lastwin), PrintStr0_c);
 		print("", PrintStr0_c);
 		if Str0Disabled then
 			print("Skipped, stream disabled", PrintStr0_c);
 			print("", PrintStr0_c);
 		else
 			HlIsTrigWin(0, Str0NextWin, clk, rqst, rsp, HasTrigger);
-			-- curwin = nextwin can occur if al lwindows are filled. In all cases we only interpret windows containing triggers.
-			while ((Str0NextWin /= curwin) or firstLoop) and HasTrigger loop
+			-- lastwin = nextwin can occur if al lwindows are filled. In all cases we only interpret windows containing triggers.
+			while ((Str0NextWin /= ((lastwin+1) mod 3)) or firstLoop) and HasTrigger loop
 				firstLoop := false;
 				print("*** Window " & to_string(Str0NextWin) & " / Number: " & to_string(Str0WinCheck) & " ***", PrintStr0_c);	
 				HlGetWinCnt(0, Str0NextWin, clk, rqst, rsp, wincnt);