121 lines
5.0 KiB
VHDL
121 lines
5.0 KiB
VHDL
--------------------------------------------------------------------------------
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-- Paul Scherrer Institute (PSI)
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--------------------------------------------------------------------------------
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-- Unit : evr320_dpram.vhd
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-- Author : Waldemar Koprek, Section Diagnostic
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-- Goran Marinkovic, Section Diagnostic
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--------------------------------------------------------------------------------
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-- Copyright© PSI, Section Diagnostic
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--------------------------------------------------------------------------------
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-- Comment :
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity evr320_dpram is
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generic
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(
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MEM_SIZE_BYTE : integer := 2048;
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MEM_DOB_WIDTH : integer := 32
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);
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port
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(
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-- port a
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clka : in std_logic;
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ena : in std_logic;
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wea : in std_logic;
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addra : in std_logic_vector(integer(ceil(log2(real(MEM_SIZE_BYTE))))-1 downto 0);
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dia : in std_logic_vector( 7 downto 0);
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-- port b
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clkb : in std_logic;
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enb : in std_logic;
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addrb : in std_logic_vector(integer(ceil(log2(real(MEM_SIZE_BYTE/(MEM_DOB_WIDTH/8)))))-1 downto 0);
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dob : out std_logic_vector(MEM_DOB_WIDTH-1 downto 0)
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);
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attribute ram_style : string;
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attribute ram_style of evr320_dpram : entity is "block";
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end evr320_dpram;
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architecture behavioral of evr320_dpram is
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type ram_type_d32 is array (MEM_SIZE_BYTE-1 downto 0) of std_logic_vector(7 downto 0);
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shared variable RAM : ram_type_d32;
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type ram_type_d64 is array ((MEM_SIZE_BYTE/2)-1 downto 0) of std_logic_vector(7 downto 0);
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shared variable RAM_ODD : ram_type_d64;
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shared variable RAM_EVEN : ram_type_d64;
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begin
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-----------------------------------------------------------------------------
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dob_32bit: if MEM_DOB_WIDTH = 32 generate
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-----------------------------------------------------------------------------
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process (clka)
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begin
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if rising_edge(clka) then
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if (ena = '1') then
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if (wea = '1') then
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RAM(to_integer(unsigned(addra))) := dia;
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end if;
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end if;
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end if;
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end process;
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process (clkb)
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begin
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if rising_edge(clkb) then
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if (enb = '1') then
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dob( 7 downto 0) <= RAM(to_integer(unsigned(std_logic_vector'(addrb & "00"))));
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dob(15 downto 8) <= RAM(to_integer(unsigned(std_logic_vector'(addrb & "01"))));
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dob(23 downto 16) <= RAM(to_integer(unsigned(std_logic_vector'(addrb & "10"))));
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dob(31 downto 24) <= RAM(to_integer(unsigned(std_logic_vector'(addrb & "11"))));
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end if;
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end if;
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end process;
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end generate dob_32bit;
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-----------------------------------------------------------------------------
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dob_64bit: if MEM_DOB_WIDTH = 64 generate
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-----------------------------------------------------------------------------
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process (clka)
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begin
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if rising_edge(clka) then
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if (ena = '1') then
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if (wea = '1') then
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if (addra(0) = '1') then
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RAM_ODD (to_integer(unsigned(addra(addra'high downto 1)))) := dia;
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else
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RAM_EVEN(to_integer(unsigned(addra(addra'high downto 1)))) := dia;
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end if;
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end if;
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end if;
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end if;
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end process;
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process (clkb)
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begin
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if rising_edge(clkb) then
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if (enb = '1') then
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dob( 7 downto 0) <= RAM_EVEN(to_integer(unsigned(std_logic_vector'(addrb & "00"))));
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dob(15 downto 8) <= RAM_ODD (to_integer(unsigned(std_logic_vector'(addrb & "00"))));
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dob(23 downto 16) <= RAM_EVEN(to_integer(unsigned(std_logic_vector'(addrb & "01"))));
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dob(31 downto 24) <= RAM_ODD (to_integer(unsigned(std_logic_vector'(addrb & "01"))));
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dob(39 downto 32) <= RAM_EVEN(to_integer(unsigned(std_logic_vector'(addrb & "10"))));
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dob(47 downto 40) <= RAM_ODD (to_integer(unsigned(std_logic_vector'(addrb & "10"))));
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dob(55 downto 48) <= RAM_EVEN(to_integer(unsigned(std_logic_vector'(addrb & "11"))));
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dob(63 downto 56) <= RAM_ODD (to_integer(unsigned(std_logic_vector'(addrb & "11"))));
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end if;
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end if;
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end process;
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end generate dob_64bit;
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end behavioral;
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--------------------------------------------------------------------------------
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-- End of file
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