hdl/evr320_ifc1210_wrapper.vhd

@@ -341,13 +341,21 @@ begin
     signal usr_evt_shaped_s    : std_logic_vector(4 downto 0);
     signal usr_events_adj_s    : std_logic_vector(4 downto 0);
     signal usr_events_concat_s : std_logic_vector(4 downto 0);
+    signal mmcm_locked         : std_logic;
+    signal rxpll_locked        : std_logic;
+    signal evr_rst_in          : std_logic;
 
   begin
+
+    rxpll_locked <= mgt_status(1);
+    mmcm_locked  <= mgt_status(2);
+    evr_rst_in   <= xuser_RESET or (not rxpll_locked) or (not mmcm_locked);
+
     --*** double stage sync for reset ***--
     proc_rst : process(clk_evr)
     begin
       if rising_edge(clk_evr) then
-        rst0_s <= xuser_RESET;
+        rst0_s <= evr_rst_in;
         rst1_s <= rst0_s;
       end if;
     end process;

hdl/v6vlx_gtxe1_wrapper.vhd

@@ -260,7 +260,7 @@ begin
       else
         case s_align_fsm is
           when align_idle =>
-            if o_mgt.rx.RXLOSSOFSYNC( 1) = '1' then
+            if o_mgt.rx.RXLOSSOFSYNC( 1) = '1' or o_mgt.rx.RXBYTEISALIGNED = '0' then
               s_align_fsm   <= align_slide;
             end if;
           when align_slide =>