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base: AEK_8220_Libraries:hipa_debug
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AEK_8220_Libraries:master AEK_8220_Libraries:latency_measure AEK_8220_Libraries:hipa_debug AEK_8220_Libraries:latfix AEK_8220_Libraries:develop AEK_8220_Libraries:version3
AEK_8220_Libraries:2.3 AEK_8220_Libraries:2.2 AEK_8220_Libraries:2.1
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compare: AEK_8220_Libraries:develop
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AEK_8220_Libraries:master AEK_8220_Libraries:latency_measure AEK_8220_Libraries:hipa_debug AEK_8220_Libraries:latfix AEK_8220_Libraries:develop AEK_8220_Libraries:version3
AEK_8220_Libraries:2.3 AEK_8220_Libraries:2.2 AEK_8220_Libraries:2.1

4 Commits
hipa_debug ... develop

Author SHA1 Message Date
stef_b
a482d8dc31 BUGFIX: for ISE 2019-10-02 16:49:53 +02:00
stef_b
b0c2476978 CLEANUP: getting rid of std_logic_unsigned library when unnecessary + sigasi project added 2019-10-02 16:24:19 +02:00
stef_b
7a1d49eb2f LIB: use only necessary libraries 2019-10-02 09:20:12 +02:00
stef_b
36a4dcb761 BUGFIX: UVVM adaptations pkg removed & unused library from wrapper, MTI_SE 10.6... 2019-10-01 16:45:10 +02:00
26 changed files with 1917 additions and 15299 deletions
Expand all files Collapse all files

4
Changelog.md
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@@ -1,7 +1,3 @@
## 2.3
* Added Features
* IFC1210 wrapper includes block to adjust pulse length of individual event and also its delay, both in recovery clock cycles. Set by constant parameter under array format.
## 2.2 ## 2.2
* Added Features * Added Features

4
sigasi/.library_mapping.xml → Sigasi/.library_mapping.xml
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@@ -1,14 +1,14 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<com.sigasi.hdt.shared.librarymapping.model:LibraryMappings xmlns:com.sigasi.hdt.shared.librarymapping.model="com.sigasi.hdt.vhdl.scoping.librarymapping" Version="2"> <com.sigasi.hdt.shared.librarymapping.model:LibraryMappings xmlns:com.sigasi.hdt.shared.librarymapping.model="com.sigasi.hdt.vhdl.scoping.librarymapping" Version="2">
<Mappings Location="Common Libraries/IEEE" Library="ieee"/> <Mappings Location="Common Libraries/IEEE" Library="ieee"/>
<Mappings Location="Common Libraries/IEEE Synopsys" Library="ieee"/>
<Mappings Location="Common Libraries" Library="not mapped"/> <Mappings Location="Common Libraries" Library="not mapped"/>
<Mappings Location="Common Libraries/psi_common/generators" Library="not mapped"/>
<Mappings Location="Common Libraries/unisim/primitive" Library="not mapped"/> <Mappings Location="Common Libraries/unisim/primitive" Library="not mapped"/>
<Mappings Location="Common Libraries/unisim/secureip" Library="not mapped"/> <Mappings Location="Common Libraries/unisim/secureip" Library="not mapped"/>
<Mappings Location="Common Libraries/STD" Library="std"/> <Mappings Location="Common Libraries/STD" Library="std"/>
<Mappings Location="Common Libraries/tosca2" Library="tosca2"/> <Mappings Location="Common Libraries/tosca2" Library="tosca2"/>
<Mappings Location="Common Libraries/unisim" Library="unisim"/> <Mappings Location="Common Libraries/unisim" Library="unisim"/>
<Mappings Location="Common Libraries/uvvm_util" Library="uvvm_util"/> <Mappings Location="Common Libraries/UVVM" Library="uvvm_util"/>
<Mappings Location="" Library="work"/> <Mappings Location="" Library="work"/>
<Mappings Location="Common Libraries/psi_common" Library="work"/> <Mappings Location="Common Libraries/psi_common" Library="work"/>
</com.sigasi.hdt.shared.librarymapping.model:LibraryMappings> </com.sigasi.hdt.shared.librarymapping.model:LibraryMappings>

18
sigasi/.project → Sigasi/.project
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@@ -34,23 +34,23 @@
<link> <link>
<name>Common Libraries/DRAG_REUSABLE_LIBRARIES_HERE.txt</name> <name>Common Libraries/DRAG_REUSABLE_LIBRARIES_HERE.txt</name>
<type>1</type> <type>1</type>
<locationURI>sigasiresource:/vhdl/readme.txt</locationURI> <locationURI>sigasiresource:/vhdl/readme2.txt</locationURI>
</link> </link>
<link> <link>
<name>Common Libraries/IEEE</name> <name>Common Libraries/IEEE</name>
<type>2</type> <type>2</type>
<locationURI>sigasiresource:/vhdl/2008/IEEE</locationURI> <locationURI>sigasiresource:/vhdl/2008/IEEE</locationURI>
</link> </link>
<link>
<name>Common Libraries/IEEE Synopsys</name>
<type>2</type>
<locationURI>sigasiresource:/vhdl/2008/IEEE%20Synopsys</locationURI>
</link>
<link> <link>
<name>Common Libraries/STD</name> <name>Common Libraries/STD</name>
<type>2</type> <type>2</type>
<locationURI>sigasiresource:/vhdl/2008/STD</locationURI> <locationURI>sigasiresource:/vhdl/2008/STD</locationURI>
</link> </link>
<link>
<name>Common Libraries/UVVM</name>
<type>2</type>
<locationURI>PARENT-2-PROJECT_LOC/UVVM</locationURI>
</link>
<link> <link>
<name>Common Libraries/psi_common</name> <name>Common Libraries/psi_common</name>
<type>2</type> <type>2</type>
@@ -59,7 +59,7 @@
<link> <link>
<name>Common Libraries/tosca2</name> <name>Common Libraries/tosca2</name>
<type>2</type> <type>2</type>
<locationURI>PARENT-4-PROJECT_LOC/BoardSupport/ifc1210/tosca2</locationURI> <locationURI>PARENT-4-PROJECT_LOC/BoardSupport/IFC1210/tosca2</locationURI>
</link> </link>
<link> <link>
<name>Common Libraries/unisim</name> <name>Common Libraries/unisim</name>
@@ -67,9 +67,9 @@
<locationURI>SIGASI_TOOLCHAIN_XILINX_ISE/vhdl/src/unisims</locationURI> <locationURI>SIGASI_TOOLCHAIN_XILINX_ISE/vhdl/src/unisims</locationURI>
</link> </link>
<link> <link>
<name>Common Libraries/uvvm_util</name> <name>Common Libraries/IEEE/Synopsys</name>
<type>2</type> <type>2</type>
<locationURI>PARENT-2-PROJECT_LOC/UVVM/uvvm_util</locationURI> <locationURI>sigasiresource:/vhdl/2008/IEEE%20Synopsys</locationURI>
</link> </link>
</linkedResources> </linkedResources>
</projectDescription> </projectDescription>

0
sigasi/.settings/com.sigasi.hdt.vhdl.version.prefs → Sigasi/.settings/com.sigasi.hdt.vhdl.version.prefs
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2
sigasi/.settings/org.eclipse.core.resources.prefs → Sigasi/.settings/org.eclipse.core.resources.prefs
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@@ -1,5 +1,5 @@
eclipse.preferences.version=1 eclipse.preferences.version=1
encoding//Common\ Libraries/IEEE=utf-8 encoding//Common\ Libraries/IEEE=utf-8
encoding//Common\ Libraries/IEEE\ Synopsys=utf-8 encoding//Common\ Libraries/IEEE/Synopsys=utf-8
encoding//Common\ Libraries/STD=utf-8 encoding//Common\ Libraries/STD=utf-8
encoding/Common\ Libraries=utf-8 encoding/Common\ Libraries=utf-8

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doc/evr320.pdf
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doc/evr320.rtf
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doc/evr320.vsd
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61
hdl/evr320_buffer.vhd
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@@ -4,10 +4,11 @@
-- Unit : evr320_buffer.vhd -- Unit : evr320_buffer.vhd
-- Author : Waldemar Koprek, Section Diagnostic -- Author : Waldemar Koprek, Section Diagnostic
-- Goran Marinkovic, Section Diagnostic -- Goran Marinkovic, Section Diagnostic
-- Benoît Stef, Section DSP
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Copyright© PSI, Section Diagnostic -- Copyright© PSI, Section Diagnostic
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Comment : -- Comment : modif 02.10.2019 - numeric_std instead of std_logic_unsigned
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
@@ -89,20 +90,28 @@ begin
if rising_edge(clka) then if rising_edge(clka) then
if (ena = '1') then if (ena = '1') then
if (wea = '1') then if (wea = '1') then
RAM(to_integer(unsigned(std_logic_vector'(page_addr_clka & addra)))) := dia; RAM(to_integer(unsigned(page_addr_clka & addra))) := dia;
end if; end if;
end if; end if;
end if; end if;
end process; end process;
process (clkb) process (clkb)
variable concat7to0_v : std_logic_vector(addrb'high+3 downto 0);
variable concat15to8_v : std_logic_vector(addrb'high+3 downto 0);
variable concat23to16_v : std_logic_vector(addrb'high+3 downto 0);
variable concat31to24_v : std_logic_vector(addrb'high+3 downto 0);
begin begin
if rising_edge(clkb) then if rising_edge(clkb) then
if (enb = '1') then if (enb = '1') then
dob( 7 downto 0) <= RAM(to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "00")))); concat7to0_v := page_addr_clkb( 3) & addrb & "00";
dob(15 downto 8) <= RAM(to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "01")))); concat15to8_v := page_addr_clkb( 3) & addrb & "01";
dob(23 downto 16) <= RAM(to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "10")))); concat23to16_v := page_addr_clkb( 3) & addrb & "10";
dob(31 downto 24) <= RAM(to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "11")))); concat31to24_v := page_addr_clkb( 3) & addrb & "11";
dob( 7 downto 0) <= RAM(to_integer(unsigned( concat7to0_v)));
dob(15 downto 8) <= RAM(to_integer(unsigned( concat15to8_v)));
dob(23 downto 16) <= RAM(to_integer(unsigned(concat23to16_v)));
dob(31 downto 24) <= RAM(to_integer(unsigned(concat31to24_v)));
end if; end if;
end if; end if;
end process; end process;
@@ -117,9 +126,9 @@ begin
if (ena = '1') then if (ena = '1') then
if (wea = '1') then if (wea = '1') then
if (addra(0) = '1') then if (addra(0) = '1') then
RAM_ODD (to_integer(unsigned(std_logic_vector'(page_addr_clka & addra(addra'high downto 1))))) := dia; RAM_ODD (to_integer(unsigned(page_addr_clka & addra(addra'high downto 1)))) := dia;
else else
RAM_EVEN(to_integer(unsigned(std_logic_vector'(page_addr_clka & addra(addra'high downto 1))))) := dia; RAM_EVEN(to_integer(unsigned((page_addr_clka & addra(addra'high downto 1))))) := dia;
end if; end if;
end if; end if;
end if; end if;
@@ -127,17 +136,33 @@ begin
end process; end process;
process (clkb) process (clkb)
variable concat7to0_v : std_logic_vector(addrb'high+3 downto 0);
variable concat15to8_v : std_logic_vector(addrb'high+3 downto 0);
variable concat23to16_v : std_logic_vector(addrb'high+3 downto 0);
variable concat31to24_v : std_logic_vector(addrb'high+3 downto 0);
variable concat39to32_v : std_logic_vector(addrb'high+3 downto 0);
variable concat47to40_v : std_logic_vector(addrb'high+3 downto 0);
variable concat55to48_v : std_logic_vector(addrb'high+3 downto 0);
variable concat63to56_v : std_logic_vector(addrb'high+3 downto 0);
begin begin
if rising_edge(clkb) then if rising_edge(clkb) then
if (enb = '1') then if (enb = '1') then
dob( 7 downto 0) <= RAM_EVEN(to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "00")))); concat7to0_v := page_addr_clkb( 3) & addrb & "00";
dob(15 downto 8) <= RAM_ODD (to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "00")))); concat15to8_v := page_addr_clkb( 3) & addrb & "00";
dob(23 downto 16) <= RAM_EVEN(to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "01")))); concat23to16_v := page_addr_clkb( 3) & addrb & "01";
dob(31 downto 24) <= RAM_ODD (to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "01")))); concat31to24_v := page_addr_clkb( 3) & addrb & "01";
dob(39 downto 32) <= RAM_EVEN(to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "10")))); concat39to32_v := page_addr_clkb( 3) & addrb & "10";
dob(47 downto 40) <= RAM_ODD (to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "10")))); concat47to40_v := page_addr_clkb( 3) & addrb & "10";
dob(55 downto 48) <= RAM_EVEN(to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "11")))); concat55to48_v := page_addr_clkb( 3) & addrb & "11";
dob(63 downto 56) <= RAM_ODD (to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "11")))); concat63to56_v := page_addr_clkb( 3) & addrb & "11";
dob( 7 downto 0) <= RAM_EVEN(to_integer(unsigned(concat7to0_v )));
dob(15 downto 8) <= RAM_ODD (to_integer(unsigned(concat15to8_v )));
dob(23 downto 16) <= RAM_EVEN(to_integer(unsigned(concat23to16_v )));
dob(31 downto 24) <= RAM_ODD (to_integer(unsigned(concat31to24_v )));
dob(39 downto 32) <= RAM_EVEN(to_integer(unsigned(concat39to32_v )));
dob(47 downto 40) <= RAM_ODD (to_integer(unsigned(concat47to40_v )));
dob(55 downto 48) <= RAM_EVEN(to_integer(unsigned(concat55to48_v )));
dob(63 downto 56) <= RAM_ODD (to_integer(unsigned(concat63to56_v )));
end if; end if;
end if; end if;
end process; end process;

119
hdl/evr320_data_filter.vhd
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@@ -4,89 +4,62 @@
-- Project: evr320 -- Project: evr320
-- Authors: Jonas Purtschert -- Authors: Jonas Purtschert
-- Description: Filter a specific data field from data buffer stream of the decoder: -- Description: Filter a specific data field from data buffer stream of the decoder:
-- Modif: Benoit Stef
-- not based on counter anymore but map to LSB into a generic array
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
use work.psi_common_math_pkg.all;
entity evr320_data_filter is entity evr320_data_filter is
generic (NUM_BYTES : integer := 8; generic (
SWAP : boolean := false ); -- if true byte are swpped at output ADDRESS : std_logic_vector(11 downto 0);
port ( -- User stream interface NUM_BYTES : integer := 8
i_stream_clk : in std_logic; -- user clock );
i_stream_data : in std_logic_vector(7 downto 0); port (
i_stream_addr : in std_logic_vector(10 downto 0); -- User stream interface
i_stream_valid : in std_logic; i_stream_clk : in std_logic; -- user clock
i_address : in std_logic_vector(11 downto 0); i_stream_data : in std_logic_vector(7 downto 0);
-- filter output: i_stream_addr : in std_logic_vector(10 downto 0);
o_data : out std_logic_vector(NUM_BYTES*8-1 downto 0) := (others=>'0'); i_stream_valid : in std_logic;
o_valid : out std_logic := '0' -- filter output:
); o_data : out std_logic_vector(NUM_BYTES*8-1 downto 0) := (others=>'0');
end entity; o_valid : out std_logic := '0'
);
end evr320_data_filter;
architecture behavioral of evr320_data_filter is architecture behavioral of evr320_data_filter is
-- array to store data value prior to map to output
type byte_array_t is array (NUM_BYTES-1 downto 0) of std_logic_vector(i_stream_data'range); signal data_shift : std_logic_vector(NUM_BYTES*8-1 downto 0) := (others=>'0');
signal table_s : byte_array_t; signal match : std_logic := '0';
--pipe help signal shift_cnt : integer range 0 to NUM_BYTES;
signal addr_dff_s : std_logic_vector(10 downto 0) := (others=>'0');
signal data_dff_s : std_logic_vector(i_stream_data'range) := (others=>'0');
signal filt_dff_s : std_logic_vector(i_address'range);
--helper
constant low_bd_c : integer := log2ceil(NUM_BYTES); --compute LSB for address decoding
signal ena_s : std_logic_vector(1 downto 0); --clock enable vector
begin begin
process(i_stream_clk)
p : process(i_stream_clk) variable addr : std_logic_vector(10 downto 0) := (others=>'0');
variable data : std_logic_vector(7 downto 0) := (others=>'0');
begin begin
if (rising_edge(i_stream_clk)) then if (rising_edge(i_stream_clk)) then
o_valid <= '0';
--*** 1st pipe stage ***
ena_s(0) <= i_stream_valid;
filt_dff_s <= i_address;
if (i_stream_valid = '1') then if (i_stream_valid = '1') then
addr_dff_s <= i_stream_addr; addr := i_stream_addr;
data_dff_s <= i_stream_data; data := i_stream_data;
end if;
if (addr = ADDRESS(10 downto 0) or match = '1') then
--*** filling the array *** match <= '1';
if ena_s(0) = '1' then if (shift_cnt < NUM_BYTES) then
if addr_dff_s(10 downto low_bd_c) = filt_dff_s(10 downto low_bd_c) then data_shift <= data_shift((data_shift'high - data'length) downto 0) & data;
--*** spatial loop *** shift_cnt <= shift_cnt + 1;
ena_s(1) <= '1'; else -- all data fetched, send to out
for i in 0 to NUM_BYTES-1 loop match <= '0';
if addr_dff_s(low_bd_c-1 downto 0) = to_uslv(i,low_bd_c) then shift_cnt <= 0;
table_s(i) <= data_dff_s ; o_valid <= '1';
end if; o_data <= data_shift;
end loop; end if;
end if; end if; -- if addr match
else end if; -- if valid
ena_s(1) <= '0';
end if;
--*** set the output & valid accordingly***
if ena_s(1) = '1' then
if (from_uslv(addr_dff_s) = (from_uslv(filt_dff_s) + NUM_BYTES -1)) then
o_valid <= '1';
--*** spatial loop map output ***
for i in 0 to NUM_BYTES-1 loop
if SWAP then
o_data(NUM_BYTES+i*NUM_BYTES-1 downto 0+i*NUM_BYTES) <= table_s(NUM_BYTES-1-i);
else
o_data(NUM_BYTES+i*NUM_BYTES-1 downto 0+i*NUM_BYTES) <= table_s(i);
end if;
end loop;
else
o_valid <= '0';
end if;
end if;
end if; end if;
end process; end process;
end architecture; end behavioral;

203
hdl/evr320_decoder.vhd
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@@ -5,29 +5,26 @@
-- Author : Waldemar Koprek, Section Diagnostic -- Author : Waldemar Koprek, Section Diagnostic
-- Goran Marinkovic, Section Diagnostic -- Goran Marinkovic, Section Diagnostic
-- Patric Bucher, Section DSV -- Patric Bucher, Section DSV
-- Benoît Stef, Section DSP
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Copyright© PSI, Section Diagnostic -- Copyright© PSI, Section Diagnostic
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Comment : -- Comment : Rewrite code to be complient with numeric_std
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim; library unisim;
use unisim.vcomponents.all; use unisim.vcomponents.all;
library work;
use work.evr320_pkg.all; use work.evr320_pkg.all;
entity evr320_decoder is entity evr320_decoder is
generic generic
( (
FACILITY : string := "SFEL"; -- "HIPA" | "SFEL"
EVENT_RECORDER : boolean := false; EVENT_RECORDER : boolean := false;
MEM_DATA_WIDTH : integer := 32; MEM_DATA_WIDTH : integer := 32
EXP_REC_CLK_FREQ : natural := 142_800_000 -- in Hz
); );
port port
( (
@@ -64,9 +61,7 @@ entity evr320_decoder is
-------------------------------------------------------------------------- --------------------------------------------------------------------------
o_usr_events : out std_logic_vector( 3 downto 0); o_usr_events : out std_logic_vector( 3 downto 0);
o_usr_events_ext : out std_logic_vector( 3 downto 0); o_usr_events_ext : out std_logic_vector( 3 downto 0);
o_sos_event : out std_logic; o_sos_event : out std_logic
o_event : out std_logic_vector( 7 downto 0);
o_event_valid : out std_logic
); );
end evr320_decoder; end evr320_decoder;
@@ -75,7 +70,6 @@ architecture behavioral of evr320_decoder is
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- Constant -- Constant
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
--
constant HIGH : std_logic := '1'; constant HIGH : std_logic := '1';
constant LOW : std_logic := '0'; constant LOW : std_logic := '0';
constant LOW_slv : std_logic_vector(15 downto 0) := (others => '0'); constant LOW_slv : std_logic_vector(15 downto 0) := (others => '0');
@@ -85,17 +79,6 @@ architecture behavioral of evr320_decoder is
-- Framing -- Framing
constant C_KCHAR_START : std_logic_vector( 7 downto 0) := X"5C"; constant C_KCHAR_START : std_logic_vector( 7 downto 0) := X"5C";
constant C_KCHAR_END : std_logic_vector( 7 downto 0) := X"3C"; constant C_KCHAR_END : std_logic_vector( 7 downto 0) := X"3C";
-- system events
constant C_EVENT_NULL : std_logic_vector( 7 downto 0) := X"00";
constant C_EVENT_SEC_0 : std_logic_vector( 7 downto 0) := X"70";
constant C_EVENT_SEC_1 : std_logic_vector( 7 downto 0) := X"71";
constant C_EVENT_STOP_LOG : std_logic_vector( 7 downto 0) := X"79";
constant C_EVENT_HEARTBEAT : std_logic_vector( 7 downto 0) := X"7A";
constant C_EVENT_SYNC_PRESCA : std_logic_vector( 7 downto 0) := X"7B";
constant C_EVENT_TIM_CNT_INC : std_logic_vector( 7 downto 0) := X"7C";
constant C_EVENT_TIM_CNT_RST : std_logic_vector( 7 downto 0) := X"7D";
constant C_EVENT_BEACON : std_logic_vector( 7 downto 0) := X"7E";
constant C_EVENT_END_OF_SEQ : std_logic_vector( 7 downto 0) := X"7F";
-- Events received -- Events received
type usr_events_type is array (0 to 3) of std_logic_vector( 3 downto 0); type usr_events_type is array (0 to 3) of std_logic_vector( 3 downto 0);
signal usr_events : usr_events_type := (others => (others => '0')); signal usr_events : usr_events_type := (others => (others => '0'));
@@ -103,21 +86,7 @@ architecture behavioral of evr320_decoder is
signal cs_min_cnt : unsigned(31 downto 0) := (others => '0'); signal cs_min_cnt : unsigned(31 downto 0) := (others => '0');
signal cs_min_time : unsigned(31 downto 0) := (others => '0'); signal cs_min_time : unsigned(31 downto 0) := (others => '0');
signal evr_stable : std_logic := '0'; signal evr_stable : std_logic := '0';
-- signal frame_fsm : frame_fsm_type;
-- Frame fsm
-- type frame_fsm_type is
-- (
-- frame_idle,
-- frame_addr_gap,
-- frame_addr,
-- frame_data_gap,
-- frame_data,
-- frame_chk1_gap,
-- frame_chk1,
-- frame_chk2_gap,
-- frame_chk2
-- );
-- signal frame_fsm : frame_fsm_type;
constant frame_idle : std_logic_vector( 3 downto 0) := "0000"; constant frame_idle : std_logic_vector( 3 downto 0) := "0000";
constant frame_addr_gap : std_logic_vector( 3 downto 0) := "0001"; constant frame_addr_gap : std_logic_vector( 3 downto 0) := "0001";
constant frame_addr : std_logic_vector( 3 downto 0) := "0010"; constant frame_addr : std_logic_vector( 3 downto 0) := "0010";
@@ -129,7 +98,7 @@ architecture behavioral of evr320_decoder is
constant frame_chk2 : std_logic_vector( 3 downto 0) := "1000"; constant frame_chk2 : std_logic_vector( 3 downto 0) := "1000";
signal frame_fsm : std_logic_vector( 3 downto 0) := "0000"; signal frame_fsm : std_logic_vector( 3 downto 0) := "0000";
-- Frame checksum -- Frame checksum
signal frame_chk : unsigned(15 downto 0) := X"FFFF"; signal frame_chk : std_logic_vector(15 downto 0) := X"FFFF";
signal frame_chk_ok : std_logic := '0'; signal frame_chk_ok : std_logic := '0';
signal frame_chk1_ok : std_logic := '0'; signal frame_chk1_ok : std_logic := '0';
signal frame_chk2_ok : std_logic := '0'; signal frame_chk2_ok : std_logic := '0';
@@ -154,8 +123,8 @@ architecture behavioral of evr320_decoder is
signal frame_data_rden : std_logic := '0'; signal frame_data_rden : std_logic := '0';
signal frame_data_do : std_logic_vector(63 downto 0) := (others => '0'); signal frame_data_do : std_logic_vector(63 downto 0) := (others => '0');
-- Frame data FIFO write port -- Frame data FIFO write port
signal frame_data_wr_id : unsigned( 7 downto 0) := (others => '0'); signal frame_data_wr_id : std_logic_vector( 7 downto 0) := (others => '0');
signal frame_data_wr_addr_cnt: unsigned(15 downto 0) := (others => '0'); signal frame_data_wr_addr_cnt: std_logic_vector(15 downto 0) := (others => '0');
signal frame_data_wr_addr : std_logic_vector(10 downto 0) := (others => '0'); signal frame_data_wr_addr : std_logic_vector(10 downto 0) := (others => '0');
signal frame_data_wr_byte : std_logic_vector( 7 downto 0) := (others => '0'); signal frame_data_wr_byte : std_logic_vector( 7 downto 0) := (others => '0');
-- Frame data FIFO read port -- Frame data FIFO read port
@@ -178,7 +147,6 @@ architecture behavioral of evr320_decoder is
signal mem_fsm : std_logic_vector( 1 downto 0) := "00"; signal mem_fsm : std_logic_vector( 1 downto 0) := "00";
-- Data memory address -- Data memory address
signal mem_addr : std_logic_vector(11 downto 0); signal mem_addr : std_logic_vector(11 downto 0);
signal mem_addr_dly : std_logic_vector(11 downto 0);
-- Data memory write -- Data memory write
signal mem_data_wren : std_logic := '0'; signal mem_data_wren : std_logic := '0';
signal mem_data_wr_addr : std_logic_vector(10 downto 0) := (others => '0'); signal mem_data_wr_addr : std_logic_vector(10 downto 0) := (others => '0');
@@ -195,16 +163,16 @@ architecture behavioral of evr320_decoder is
signal usr_events_save_dly : std_logic := '0'; signal usr_events_save_dly : std_logic := '0';
signal usr_events_nr : std_logic_vector( 7 downto 0) := (others => '0'); signal usr_events_nr : std_logic_vector( 7 downto 0) := (others => '0');
signal usr_events_nr_dly : std_logic_vector( 7 downto 0) := (others => '0'); signal usr_events_nr_dly : std_logic_vector( 7 downto 0) := (others => '0');
signal usr_events_addr : unsigned( 7 downto 0) := (others => '0'); signal usr_events_addr : std_logic_vector( 7 downto 0) := (others => '0');
signal usr_events_addr_dly : std_logic_vector( 7 downto 0) := (others => '0'); signal usr_events_addr_dly : std_logic_vector( 7 downto 0) := (others => '0');
signal usr_events_cnt : unsigned( 31 downto 0) := (others => '0'); signal usr_events_cnt : std_logic_vector( 31 downto 0) := (others => '0');
signal usr_events_cnt_d : unsigned( 31 downto 0) := (others => '0'); signal usr_events_cnt_d : std_logic_vector( 31 downto 0) := (others => '0');
signal all_events_flags : std_logic_vector(255 downto 0) := (others => '0'); signal all_events_flags : std_logic_vector(255 downto 0) := (others => '0');
signal all_events_flags_d : std_logic_vector(255 downto 0) := (others => '0'); signal all_events_flags_d : std_logic_vector(255 downto 0) := (others => '0');
signal all_events_flags_sync1 : std_logic_vector(255 downto 0) := (others => '0'); signal all_events_flags_sync1 : std_logic_vector(255 downto 0) := (others => '0');
signal all_events_flags_sync2 : std_logic_vector(255 downto 0) := (others => '0'); signal all_events_flags_sync2 : std_logic_vector(255 downto 0) := (others => '0');
signal timestamp_cnt : unsigned( 31 downto 0) := (others => '0'); signal timestamp_cnt : std_logic_vector( 31 downto 0) := (others => '0');
signal timestamp_cnt_dly : unsigned( 31 downto 0) := (others => '0'); signal timestamp_cnt_dly : std_logic_vector( 31 downto 0) := (others => '0');
signal segment_addr_wren : std_logic; signal segment_addr_wren : std_logic;
signal mem_data_valid : std_logic; signal mem_data_valid : std_logic;
signal mem_data_error : std_logic; signal mem_data_error : std_logic;
@@ -224,9 +192,7 @@ architecture behavioral of evr320_decoder is
-- attribute fsm_safe_state : string; -- attribute fsm_safe_state : string;
-- attribute fsm_safe_state of frame_fsm : signal is "default_state"; -- attribute fsm_safe_state of frame_fsm : signal is "default_state";
-- attribute fsm_safe_state of mem_fsm : signal is "default_state"; -- attribute fsm_safe_state of mem_fsm : signal is "default_state";
constant evr_stable_time_int_c : natural := EXP_REC_CLK_FREQ/100;
constant evr_stable_time_slv_c : std_logic_vector(cs_timeout_cnt'range):= std_logic_vector(to_unsigned(evr_stable_time_int_c, cs_timeout_cnt'length));
begin begin
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
@@ -235,10 +201,9 @@ begin
debug_clk <= i_mgt_rx_clk; debug_clk <= i_mgt_rx_clk;
debug( 15 downto 0) <= i_mgt_rx_data; debug( 15 downto 0) <= i_mgt_rx_data;
debug( 17 downto 16) <= i_mgt_rx_charisk; debug( 17 downto 16) <= i_mgt_rx_charisk;
debug(18) <= evr_stable;--new debug( 23 downto 18) <= (others=>'0');
debug(26 downto 19) <= i_evr_params.event_numbers(1); debug( 31 downto 24) <= (others => '0');
debug(34 downto 27) <= i_evr_params.event_numbers(2); debug( 35 downto 32) <= "0001" when (frame_fsm = frame_idle ) else
debug(38 downto 35) <= "0001" when (frame_fsm = frame_idle ) else
"0010" when (frame_fsm = frame_addr_gap) else "0010" when (frame_fsm = frame_addr_gap) else
"0011" when (frame_fsm = frame_addr ) else "0011" when (frame_fsm = frame_addr ) else
"0100" when (frame_fsm = frame_data_gap) else "0100" when (frame_fsm = frame_data_gap) else
@@ -248,7 +213,7 @@ begin
"1000" when (frame_fsm = frame_chk2_gap) else "1000" when (frame_fsm = frame_chk2_gap) else
"1001" when (frame_fsm = frame_chk2 ) else "1001" when (frame_fsm = frame_chk2 ) else
"0000"; "0000";
debug( 39) <= '0'; debug( 39 downto 36) <= (others => '0');
debug( 40) <= usr_events( 0)( 3); debug( 40) <= usr_events( 0)( 3);
debug( 41) <= usr_events( 1)( 3); debug( 41) <= usr_events( 1)( 3);
debug( 42) <= usr_events( 2)( 3); debug( 42) <= usr_events( 2)( 3);
@@ -262,18 +227,18 @@ begin
debug( 65) <= usr_events_save_dly; debug( 65) <= usr_events_save_dly;
debug( 73 downto 66) <= usr_events_nr_dly; debug( 73 downto 66) <= usr_events_nr_dly;
debug( 81 downto 74) <= usr_events_addr_dly; debug( 81 downto 74) <= usr_events_addr_dly;
debug(113 downto 82) <= std_logic_vector(timestamp_cnt_dly); debug(113 downto 82) <= timestamp_cnt_dly;
debug(114) <= segment_addr_wren; debug(114) <= segment_addr_wren;
debug(115) <= mem_data_valid; debug(115) <= mem_data_valid;
debug(116) <= mem_data_error; debug(116) <= mem_data_error;
debug(117) <= mem_data_read_ack(0); debug(117) <= mem_data_read_ack(0);
debug(118) <= mem_data_error_ack(0); debug(118) <= mem_data_error_ack(0);
debug(119) <= all_events_flags(27); -- event code 27 (photonics) debug(119) <= all_events_flags(27); -- event code 27 (photonics)
debug(127 downto 120) <= std_logic_vector(usr_events_cnt(7 downto 0)); debug(127 downto 120) <= usr_events_cnt(7 downto 0);
end generate dbg_evt_rec; end generate dbg_evt_rec;
dbg_no_evt_rec: if not(EVENT_RECORDER) generate dbg_no_evt_rec: if not(EVENT_RECORDER) generate
debug(127 downto 64) <= (others => '0');
end generate dbg_no_evt_rec; end generate dbg_no_evt_rec;
@@ -295,7 +260,6 @@ begin
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- evr stable state -- evr stable state
-- TODO: Perform the sync according to k28.5
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
prc_evr_stable : process(i_mgt_rx_clk) prc_evr_stable : process(i_mgt_rx_clk)
begin begin
@@ -303,9 +267,7 @@ begin
if (i_mgt_rst = '1') then if (i_mgt_rst = '1') then
evr_stable <= '0'; evr_stable <= '0';
else else
if ((std_logic_vector(cs_min_cnt) > i_evr_params.cs_min_cnt) and if ((cs_min_cnt > unsigned(i_evr_params.cs_min_cnt)) and (cs_min_time > unsigned(i_evr_params.cs_min_time)) and (cs_timeout_cnt < X"15CA20")) then
(std_logic_vector(cs_min_time) > i_evr_params.cs_min_time) and
(std_logic_vector(cs_timeout_cnt) < evr_stable_time_slv_c)) then -- make generics depending on recovery_clock
evr_stable <= '1'; evr_stable <= '1';
else else
evr_stable <= '0'; evr_stable <= '0';
@@ -324,21 +286,13 @@ begin
if (i_mgt_rst = '1') then if (i_mgt_rst = '1') then
usr_events <= (others => (others => '0')); usr_events <= (others => (others => '0'));
else else
for i in 0 to 3 loop for i in 0 to 3 loop
if FACILITY = "HIPA" then if ((i_evr_params.event_enable(i) = '1') and (i_mgt_rx_charisk( 0) = '0') and (i_mgt_rx_data( 7 downto 0) = i_evr_params.event_numbers(i)) and (evr_stable = '1')) then
if ((i_evr_params.event_enable(i) = '1') and (i_mgt_rx_charisk( 0) = '0') and (i_mgt_rx_data( 7 downto 0) = i_evr_params.event_numbers(i))) then
usr_events(i) <= "1111"; usr_events(i) <= "1111";
else else
usr_events(i) <= usr_events(i)( 2 downto 0) & '0'; usr_events(i) <= usr_events(i)( 2 downto 0) & '0';
end if; end if;
else end loop;
if ((i_evr_params.event_enable(i) = '1') and (i_mgt_rx_charisk( 0) = '0') and (i_mgt_rx_data( 7 downto 0) = i_evr_params.event_numbers(i))and (evr_stable = '1')) then
usr_events(i) <= "1111";
else
usr_events(i) <= usr_events(i)( 2 downto 0) & '0';
end if;
end if;
end loop;
end if; end if;
end if; end if;
end process; end process;
@@ -361,7 +315,7 @@ begin
cs_timeout_cnt <= X"000000"; cs_timeout_cnt <= X"000000";
else else
if (cs_timeout_cnt /= X"FFFFFF") then if (cs_timeout_cnt /= X"FFFFFF") then
cs_timeout_cnt <= cs_timeout_cnt + X"000001"; cs_timeout_cnt <= cs_timeout_cnt + 1;--X"000001";
end if; end if;
end if; end if;
end if; end if;
@@ -380,7 +334,7 @@ begin
if (frame_ctrl_wren = '1') then if (frame_ctrl_wren = '1') then
if (frame_chk_ok = '1') then if (frame_chk_ok = '1') then
if (cs_min_cnt /= X"FFFFFFFF") then if (cs_min_cnt /= X"FFFFFFFF") then
cs_min_cnt <= cs_min_cnt + X"00000001"; cs_min_cnt <= cs_min_cnt + 1;--X"00000001";
end if; end if;
else else
cs_min_cnt <= X"00000000"; cs_min_cnt <= X"00000000";
@@ -474,8 +428,8 @@ begin
when frame_idle => when frame_idle =>
frame_data_wr_addr_cnt <= (others => '0'); frame_data_wr_addr_cnt <= (others => '0');
when frame_addr => when frame_addr =>
frame_data_wr_id <= frame_data_wr_id + X"01"; frame_data_wr_id <= std_logic_vector(unsigned(frame_data_wr_id) + 1);
frame_data_wr_addr_cnt <= "0000" & unsigned(i_mgt_rx_data(15 downto 8)) & "0000"; frame_data_wr_addr_cnt <= "0000" & i_mgt_rx_data(15 downto 8) & "0000";
segment_addr_wren <= '1'; segment_addr_wren <= '1';
when frame_data => when frame_data =>
if (((i_mgt_rx_charisk( 1) = '1') and (i_mgt_rx_data(15 downto 8) = C_KCHAR_END)) or if (((i_mgt_rx_charisk( 1) = '1') and (i_mgt_rx_data(15 downto 8) = C_KCHAR_END)) or
@@ -483,8 +437,8 @@ begin
frame_data_wren <= '0'; frame_data_wren <= '0';
else else
frame_data_wren <= not frame_data_full; frame_data_wren <= not frame_data_full;
frame_data_wr_addr_cnt <= frame_data_wr_addr_cnt + X"0001"; frame_data_wr_addr_cnt <= std_logic_vector(unsigned(frame_data_wr_addr_cnt) + 1);
frame_data_wr_addr <= std_logic_vector(frame_data_wr_addr_cnt(10 downto 0)); frame_data_wr_addr <= frame_data_wr_addr_cnt(10 downto 0);
frame_data_wr_byte <= i_mgt_rx_data(15 downto 8); frame_data_wr_byte <= i_mgt_rx_data(15 downto 8);
end if; end if;
when others => when others =>
@@ -505,7 +459,7 @@ begin
frame_chk <= X"FFFF"; frame_chk <= X"FFFF";
when frame_addr | frame_data => when frame_addr | frame_data =>
if (i_mgt_rx_charisk = "00") then if (i_mgt_rx_charisk = "00") then
frame_chk <= frame_chk - (X"00" & unsigned(i_mgt_rx_data(15 downto 8))); frame_chk <= std_logic_vector(unsigned(frame_chk) - unsigned(i_mgt_rx_data(15 downto 8)));
end if; end if;
when others => when others =>
null; null;
@@ -521,11 +475,11 @@ begin
frame_chk1_ok <= '0'; frame_chk1_ok <= '0';
frame_chk2_ok <= '0'; frame_chk2_ok <= '0';
when frame_chk1 => when frame_chk1 =>
if (frame_chk(15 downto 8) = unsigned(i_mgt_rx_data(15 downto 8))) then if (frame_chk(15 downto 8) = i_mgt_rx_data(15 downto 8)) then
frame_chk1_ok <= '1'; frame_chk1_ok <= '1';
end if; end if;
when frame_chk2 => when frame_chk2 =>
if (frame_chk( 7 downto 0) = unsigned(i_mgt_rx_data(15 downto 8))) then if (frame_chk( 7 downto 0) = i_mgt_rx_data(15 downto 8)) then
frame_chk2_ok <= '1'; frame_chk2_ok <= '1';
end if; end if;
when others => when others =>
@@ -551,7 +505,7 @@ begin
end if; end if;
end process; end process;
frame_ctrl_wr_id <= std_logic_vector(frame_data_wr_id); frame_ctrl_wr_id <= frame_data_wr_id;
frame_ctrl_wr_ok <= frame_chk_ok; frame_ctrl_wr_ok <= frame_chk_ok;
frame_ctrl_di( 7 downto 0) <= frame_ctrl_wr_id; frame_ctrl_di( 7 downto 0) <= frame_ctrl_wr_id;
@@ -613,7 +567,7 @@ begin
frame_ctrl_rd_ok <= frame_ctrl_do( 8); frame_ctrl_rd_ok <= frame_ctrl_do( 8);
-- Frame data received -- Frame data received
frame_data_di( 7 downto 0) <= std_logic_vector(frame_data_wr_id); frame_data_di( 7 downto 0) <= frame_data_wr_id;
frame_data_di(18 downto 8) <= frame_data_wr_addr; frame_data_di(18 downto 8) <= frame_data_wr_addr;
frame_data_di(23 downto 19) <= "00000"; frame_data_di(23 downto 19) <= "00000";
frame_data_di(31 downto 24) <= frame_data_wr_byte; frame_data_di(31 downto 24) <= frame_data_wr_byte;
@@ -724,24 +678,14 @@ begin
mem_data_wr_addr <= frame_data_rd_addr; mem_data_wr_addr <= frame_data_rd_addr;
mem_data_wr_byte <= frame_data_rd_byte; mem_data_wr_byte <= frame_data_rd_byte;
-----------------------------------------------------------------------------
-- Address delay for read data mux
-----------------------------------------------------------------------------
process(i_usr_clk)
begin
if (i_usr_clk'event and (i_usr_clk = '1')) then
mem_addr_dly <= mem_addr;
end if;
end process;
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- Data memory selector -- Data memory selector
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
o_mem_data <= mem_data_dpram when (mem_addr_dly(11 downto 9) = "000") else o_mem_data <= mem_data_dpram when (mem_addr(11 downto 9) = "000") else
mem_data_event0 when (mem_addr_dly(11 downto 9) = "001") else mem_data_event0 when (mem_addr(11 downto 9) = "001") else
mem_data_event1 when (mem_addr_dly(11 downto 9) = "010") else mem_data_event1 when (mem_addr(11 downto 9) = "010") else
mem_data_event2 when (mem_addr_dly(11 downto 9) = "011") else mem_data_event2 when (mem_addr(11 downto 9) = "011") else
mem_data_event3 when (mem_addr_dly(11 downto 9) = "100") else mem_data_event3 when (mem_addr(11 downto 9) = "100") else
mem_data_event_recorder; mem_data_event_recorder;
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
@@ -911,23 +855,6 @@ begin
o_stream_data <= stream_raw(7 downto 0); o_stream_data <= stream_raw(7 downto 0);
o_stream_addr <= stream_raw(18 downto 8); o_stream_addr <= stream_raw(18 downto 8);
-----------------------------------------------------------------------------
-- Raw Event Output
-----------------------------------------------------------------------------
raw_event_output_proc : process(i_mgt_rx_clk)
begin
if (rising_edge(i_mgt_rx_clk)) then
o_event_valid <= '0';
o_event <= (others=>'0');
if ((i_mgt_rx_charisk(0) = '0') and (evr_stable = '1')) then
o_event_valid <= '1';
o_event <= i_mgt_rx_data(7 downto 0);
end if;
end if;
end process;
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- EVENT RECORDER -- EVENT RECORDER
@@ -961,36 +888,25 @@ begin
-- timestamp for event and segement tagging -- timestamp for event and segement tagging
if (timestamp_cnt /= X"FFFF_FFFF") then if (timestamp_cnt /= X"FFFF_FFFF") then
timestamp_cnt <= timestamp_cnt + X"0000_0001"; timestamp_cnt <= std_logic_vector(unsigned(timestamp_cnt) + 1);
end if; end if;
-- only run event recorder when stable operation -- only run event recorder when stable operation
if ( (i_event_recorder_ctrl.event_enable = '1') and (i_mgt_rx_charisk( 0) = '0') and (evr_stable = '1')) then if ( (i_event_recorder_ctrl.event_enable = '1') and (i_mgt_rx_charisk( 0) = '0') and (evr_stable = '1')) then
-- filter standard events (user events = 0x01-0x6F, 0x72-0x78, 0x80-0xFF) -- filter standard events (user events = 0x01-0x6F, 0x72-0x78, 0x80-0xFF)
if ( or_reduce(i_mgt_rx_data(7 downto 0)) = '1' and (i_mgt_rx_data(7 downto 4) /= X"7")) then if unsigned(i_mgt_rx_data(7 downto 0)) /= 0 and i_mgt_rx_data(7 downto 4) /= X"7" then
-- if ( i_mgt_rx_data(7 downto 0) /= C_EVENT_NULL and
-- i_mgt_rx_data(7 downto 0) /= C_EVENT_SEC_0 and
-- i_mgt_rx_data(7 downto 0) /= C_EVENT_SEC_1 and
-- i_mgt_rx_data(7 downto 0) /= C_EVENT_STOP_LOG and
-- i_mgt_rx_data(7 downto 0) /= C_EVENT_HEARTBEAT and
-- i_mgt_rx_data(7 downto 0) /= C_EVENT_SYNC_PRESCA and
-- i_mgt_rx_data(7 downto 0) /= C_EVENT_TIM_CNT_INC and
-- i_mgt_rx_data(7 downto 0) /= C_EVENT_TIM_CNT_RST and
-- i_mgt_rx_data(7 downto 0) /= C_EVENT_BEACON and
-- i_mgt_rx_data(7 downto 0) /= C_EVENT_END_OF_SEQ ) then
usr_events_nr <= i_mgt_rx_data(7 downto 0); usr_events_nr <= i_mgt_rx_data(7 downto 0);
-- write event nr memory -- write event nr memory
if (usr_events_addr /= X"FF") then if (usr_events_addr /= X"FF") then
usr_events_save <= '1'; usr_events_save <= '1';
usr_events_addr <= usr_events_addr + X"01"; usr_events_addr <= std_logic_vector(unsigned(usr_events_addr) + 1);
end if; end if;
-- count all user events -- count all user events
if (usr_events_cnt /= X"FFFF_FFFF") then if (usr_events_cnt /= X"FFFF_FFFF") then
usr_events_cnt <= usr_events_cnt + X"0000_0001"; usr_events_cnt <= std_logic_vector(unsigned(usr_events_cnt) + 1);
end if; end if;
-- start-of-sequence, trigger event for event recorder -- start-of-sequence, trigger event for event recorder
@@ -1024,7 +940,7 @@ begin
timestamp_cnt_dly <= timestamp_cnt; timestamp_cnt_dly <= timestamp_cnt;
usr_events_save_dly <= usr_events_save; usr_events_save_dly <= usr_events_save;
usr_events_nr_dly <= usr_events_nr; usr_events_nr_dly <= usr_events_nr;
usr_events_addr_dly <= std_logic_vector(usr_events_addr); usr_events_addr_dly <= usr_events_addr;
end if; end if;
end process; end process;
@@ -1071,11 +987,11 @@ begin
-------------------------------------------------------------------------- --------------------------------------------------------------------------
-- Memory Selector Event Recorder -- Memory Selector Event Recorder
-------------------------------------------------------------------------- --------------------------------------------------------------------------
mem_data_event_recorder <= mem_data_dpram_sos when (mem_addr_dly(11 downto 9) = B"101") else -- 2K mem_data_event_recorder <= mem_data_dpram_sos when (mem_addr(11 downto 9) = B"101") else -- 2K
mem_data_event_nr_timestamp when (mem_addr_dly(11 downto 8) = B"1100") else -- 1K mem_data_event_nr_timestamp when (mem_addr(11 downto 8) = B"1100") else -- 1K
mem_data_segment_timestamp when (mem_addr_dly(11 downto 7) = B"1101_0") else -- 512B mem_data_segment_timestamp when (mem_addr(11 downto 7) = B"1101_0") else -- 512B
mem_data_event_nr when (mem_addr_dly(11 downto 6) = B"1101_10") else -- 256B mem_data_event_nr when (mem_addr(11 downto 6) = B"1101_10") else -- 256B
mem_data_event_flag when (mem_addr_dly(11 downto 6) = B"1101_11") else -- 256B mem_data_event_flag when (mem_addr(11 downto 6) = B"1101_11") else -- 256B
(others => '0'); (others => '0');
@@ -1122,8 +1038,8 @@ begin
clka => i_mgt_rx_clk, clka => i_mgt_rx_clk,
ena => HIGH, ena => HIGH,
wea => segment_addr_wren, wea => segment_addr_wren,
addra => std_logic_vector(frame_data_wr_addr_cnt(10 downto 4)), addra => frame_data_wr_addr_cnt(10 downto 4),
dia => std_logic_vector(timestamp_cnt), dia => timestamp_cnt,
page => sos_event(3), page => sos_event(3),
-- port b -- port b
clkb => i_usr_clk, clkb => i_usr_clk,
@@ -1148,7 +1064,7 @@ begin
ena => HIGH, ena => HIGH,
wea => usr_events_save_dly, wea => usr_events_save_dly,
addra => usr_events_addr_dly, addra => usr_events_addr_dly,
dia => std_logic_vector(timestamp_cnt_dly), dia => timestamp_cnt_dly,
page => sos_event(3), page => sos_event(3),
-- port b -- port b
clkb => i_usr_clk, clkb => i_usr_clk,
@@ -1186,7 +1102,8 @@ begin
-- Event Flags of all Events -- Event Flags of all Events
-------------------------------------------------------------------------- --------------------------------------------------------------------------
prc_event_flags: process(i_usr_clk) prc_event_flags: process(i_usr_clk)
variable v_addr : integer range 0 to 255; variable v_addr : integer range 0 to 255;
variable v_addr_slv : std_logic_vector(7 downto 0);
begin begin
if (i_usr_clk'event and (i_usr_clk = '1')) then if (i_usr_clk'event and (i_usr_clk = '1')) then
-- sync to usr clk -- sync to usr clk
@@ -1194,9 +1111,11 @@ begin
all_events_flags_sync2 <= all_events_flags_sync1; all_events_flags_sync2 <= all_events_flags_sync1;
-- address fragment of vector / expand bit to bytes for data read -- address fragment of vector / expand bit to bytes for data read
v_addr := to_integer(unsigned(std_logic_vector'(mem_addr(5 downto MEM_ADDR_LSB) & LOW_slv(1 + MEM_ADDR_LSB downto 0)))); v_addr_slv := mem_addr(5 downto MEM_ADDR_LSB) & LOW_slv(1 + MEM_ADDR_LSB downto 0);
v_addr := to_integer(unsigned(v_addr_slv));
mem_data_event_flag <= bit2byte(all_events_flags_sync2(v_addr + MEM_DATA_BYTES - 1 downto v_addr)); mem_data_event_flag <= bit2byte(all_events_flags_sync2(v_addr + MEM_DATA_BYTES - 1 downto v_addr));
end if; end if;
end process; end process;
@@ -1204,7 +1123,7 @@ begin
-- port mapping -- port mapping
-------------------------------------------------------------------------- --------------------------------------------------------------------------
o_sos_event <= sos_event(3); o_sos_event <= sos_event(3);
o_event_recorder_stat.usr_events_counter <= std_logic_vector(usr_events_cnt_d); o_event_recorder_stat.usr_events_counter <= usr_events_cnt_d;
o_event_recorder_stat.data_valid <= mem_data_valid; o_event_recorder_stat.data_valid <= mem_data_valid;
o_event_recorder_stat.data_error <= mem_data_error; o_event_recorder_stat.data_error <= mem_data_error;

57
hdl/evr320_dpram.vhd
View File

@@ -4,10 +4,11 @@
-- Unit : evr320_dpram.vhd -- Unit : evr320_dpram.vhd
-- Author : Waldemar Koprek, Section Diagnostic -- Author : Waldemar Koprek, Section Diagnostic
-- Goran Marinkovic, Section Diagnostic -- Goran Marinkovic, Section Diagnostic
-- Benoit Stef, Section DSP
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Copyright© PSI, Section Diagnostic -- Copyright© PSI, Section Diagnostic
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Comment : -- Comment : modif 02.10.2019 - numeric_std instead std_logic_unsigned
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
@@ -66,13 +67,22 @@ begin
end process; end process;
process (clkb) process (clkb)
variable concat7to0_v : std_logic_vector(addrb'high+2 downto 0);
variable concat15to8_v : std_logic_vector(addrb'high+2 downto 0);
variable concat23to16_v : std_logic_vector(addrb'high+2 downto 0);
variable concat31to24_v : std_logic_vector(addrb'high+2 downto 0);
begin begin
if rising_edge(clkb) then if rising_edge(clkb) then
if (enb = '1') then if (enb = '1') then
dob( 7 downto 0) <= RAM(to_integer(unsigned(std_logic_vector'(addrb & "00")))); concat7to0_v := addrb & "00";
dob(15 downto 8) <= RAM(to_integer(unsigned(std_logic_vector'(addrb & "01")))); concat15to8_v := addrb & "01";
dob(23 downto 16) <= RAM(to_integer(unsigned(std_logic_vector'(addrb & "10")))); concat23to16_v := addrb & "10";
dob(31 downto 24) <= RAM(to_integer(unsigned(std_logic_vector'(addrb & "11")))); concat31to24_v := addrb & "11";
--
dob( 7 downto 0) <= RAM(to_integer(unsigned( concat7to0_v)));
dob(15 downto 8) <= RAM(to_integer(unsigned( concat15to8_v)));
dob(23 downto 16) <= RAM(to_integer(unsigned(concat23to16_v)));
dob(31 downto 24) <= RAM(to_integer(unsigned(concat31to24_v)));
end if; end if;
end if; end if;
end process; end process;
@@ -97,17 +107,34 @@ begin
end process; end process;
process (clkb) process (clkb)
variable concat7to0_v : std_logic_vector(addrb'high+2 downto 0);
variable concat15to8_v : std_logic_vector(addrb'high+2 downto 0);
variable concat23to16_v : std_logic_vector(addrb'high+2 downto 0);
variable concat31to24_v : std_logic_vector(addrb'high+2 downto 0);
variable concat39to32_v : std_logic_vector(addrb'high+2 downto 0);
variable concat47to40_v : std_logic_vector(addrb'high+2 downto 0);
variable concat55to48_v : std_logic_vector(addrb'high+2 downto 0);
variable concat63to56_v : std_logic_vector(addrb'high+2 downto 0);
begin begin
if rising_edge(clkb) then if rising_edge(clkb) then
if (enb = '1') then if (enb = '1') then
dob( 7 downto 0) <= RAM_EVEN(to_integer(unsigned(std_logic_vector'(addrb & "00")))); concat7to0_v :=addrb & "00";
dob(15 downto 8) <= RAM_ODD (to_integer(unsigned(std_logic_vector'(addrb & "00")))); concat15to8_v :=addrb & "00";
dob(23 downto 16) <= RAM_EVEN(to_integer(unsigned(std_logic_vector'(addrb & "01")))); concat23to16_v :=addrb & "01";
dob(31 downto 24) <= RAM_ODD (to_integer(unsigned(std_logic_vector'(addrb & "01")))); concat31to24_v :=addrb & "01";
dob(39 downto 32) <= RAM_EVEN(to_integer(unsigned(std_logic_vector'(addrb & "10")))); concat39to32_v :=addrb & "10";
dob(47 downto 40) <= RAM_ODD (to_integer(unsigned(std_logic_vector'(addrb & "10")))); concat47to40_v :=addrb & "10";
dob(55 downto 48) <= RAM_EVEN(to_integer(unsigned(std_logic_vector'(addrb & "11")))); concat55to48_v :=addrb & "11";
dob(63 downto 56) <= RAM_ODD (to_integer(unsigned(std_logic_vector'(addrb & "11")))); concat63to56_v :=addrb & "11";
--
dob( 7 downto 0) <= RAM_EVEN(to_integer(unsigned(concat7to0_v )));
dob(15 downto 8) <= RAM_ODD (to_integer(unsigned(concat15to8_v )));
dob(23 downto 16) <= RAM_EVEN(to_integer(unsigned(concat23to16_v)));
dob(31 downto 24) <= RAM_ODD (to_integer(unsigned(concat31to24_v)));
dob(39 downto 32) <= RAM_EVEN(to_integer(unsigned(concat39to32_v)));
dob(47 downto 40) <= RAM_ODD (to_integer(unsigned(concat47to40_v)));
dob(55 downto 48) <= RAM_EVEN(to_integer(unsigned(concat55to48_v)));
dob(63 downto 56) <= RAM_ODD (to_integer(unsigned(concat63to56_v)));
end if; end if;
end if; end if;
end process; end process;

468
hdl/evr320_ifc1210_wrapper.vhd
View File

@@ -2,7 +2,7 @@
-- Paul Scherrer Institute (PSI) -- Paul Scherrer Institute (PSI)
-- --------------------------------------------------------------------------- -- ---------------------------------------------------------------------------
-- Unit : evr320_ifc1210_wrapper.vhd -- Unit : evr320_ifc1210_wrapper.vhd
-- Author : Patric Bucher, Benoit Stef -- Author : Patric Bucher
-- --------------------------------------------------------------------------- -- ---------------------------------------------------------------------------
-- Copyright© PSI, Section DSV -- Copyright© PSI, Section DSV
-- --------------------------------------------------------------------------- -- ---------------------------------------------------------------------------
@@ -11,7 +11,6 @@
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
use ieee.math_real.all;
library tosca2; library tosca2;
use tosca2.tosca2_glb_pkg.all; use tosca2.tosca2_glb_pkg.all;
@@ -19,381 +18,256 @@ use tosca2.tosca2_glb_pkg.all;
use work.evr320_pkg.all; use work.evr320_pkg.all;
use work.v6vlx_gtxe1_pkg.all; use work.v6vlx_gtxe1_pkg.all;
entity evr320_ifc1210_wrapper is entity evr320_ifc1210_wrapper is
generic( generic(
g_MGT_LOCATION : string := "GTXE1_X0Y16"; -- "GTXE1_X0Y0" to "GTXE1_X0Y11" | "GTXE1_X0Y16" to "GTXE1_X0Y19" g_MGT_LOCATION : string := "GTXE1_X0Y16"; -- "GTXE1_X0Y0" to "GTXE1_X0Y11" | "GTXE1_X0Y16" to "GTXE1_X0Y19"
g_FACILITY : string := "SFEL"; -- "HIPA" | "SFEL" g_FACILITY : string := "SFEL"; -- "HIPA" | "SFEL"
g_EVENT_RECORDER : boolean := false; -- enable/disable Event Recorder functionality g_EVENT_RECORDER : boolean := false; -- enable/disable Event Recorder functionality
g_XUSER_CLK_FREQ : natural := 125000000 -- Xuser Clk Frequency in Hz g_XUSER_CLK_FREQ : natural := 125000000 -- Xuser Clk Frequency in Hz
); );
port( port(
-- ------------------------------------------------------------------------ -- ------------------------------------------------------------------------
-- Debug interface -- Debug interface
-- ------------------------------------------------------------------------ -- ------------------------------------------------------------------------
debug_clk : out std_logic; debug_clk : out std_logic;
debug : out std_logic_vector(127 downto 0); debug : out std_logic_vector(127 downto 0);
-- ------------------------------------------------------------------------ -- ------------------------------------------------------------------------
-- TOSCA2 TMEM Interface (xuser clock domain, 100-250MHz) -- TOSCA2 TMEM Interface (xuser clock domain, 100-250MHz)
-- ------------------------------------------------------------------------ -- ------------------------------------------------------------------------
xuser_CLK : in std_logic; xuser_CLK : in std_logic;
xuser_RESET : in std_logic; xuser_RESET : in std_logic;
xuser_TMEM_ENA : in std_logic; xuser_TMEM_ENA : in std_logic;
xuser_TMEM_WE : in std_logic_vector(7 downto 0); xuser_TMEM_WE : in std_logic_vector( 7 downto 0);
xuser_TMEM_ADD : in std_logic_vector(13 downto 3); xuser_TMEM_ADD : in std_logic_vector(13 downto 3);
xuser_TMEM_DATW : in std_logic_vector(63 downto 0); xuser_TMEM_DATW : in std_logic_vector(63 downto 0);
xuser_TMEM_DATR : out std_logic_vector(63 downto 0); xuser_TMEM_DATR : out std_logic_vector(63 downto 0);
-- ------------------------------------------------------------------------ -- ------------------------------------------------------------------------
-- MGT Interface -- MGT Interface
-- ------------------------------------------------------------------------ -- ------------------------------------------------------------------------
mgt_refclk_i : in std_logic; -- MGT Reference Clock mgt_refclk_i : in std_logic; -- MGT Reference Clock
mgt_sfp_los_i : in std_logic; -- SFP Loss of Signal (light on receiver) mgt_sfp_los_i : in std_logic; -- SFP Loss of Signal (light on receiver)
mgt_rx_n : in std_logic; -- MGT RX N mgt_rx_n : in std_logic; -- MGT RX N
mgt_rx_p : in std_logic; -- MGT RX P mgt_rx_p : in std_logic; -- MGT RX P
mgt_tx_n : out std_logic; -- MGT TX N mgt_tx_n : out std_logic; -- MGT TX N
mgt_tx_p : out std_logic; -- MGT TX P mgt_tx_p : out std_logic; -- MGT TX P
mgt_status_o : out std_logic_vector(31 downto 0); -- MGT Status mgt_status_o : out std_logic_vector(31 downto 0); -- MGT Status
mgt_control_i : in std_logic_vector(31 downto 0); -- MGT Control mgt_control_i : in std_logic_vector(31 downto 0); -- MGT Control
mgt_rx_data_o : out std_logic_Vector(15 downto 0); -- for debug purpose
mgt_rx_charisk_o : out std_logic_vector(1 downto 0); -- for debug purpose
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
-- User interface MGT clock -- User interface MGT clock
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
clk_evr_o : out std_logic; -- Recovered parallel clock from MGT clk_evr_o : out std_logic; -- Recovered parallel clock from MGT
rst_evr_o : out std_logic; -- reset according to RX Loss of sync usr_events_o : out std_logic_vector( 3 downto 0); -- User defined event pulses with one clock cycle length
usr_events_o : out std_logic_vector(3 downto 0); -- User defined event pulses with one clock cycles length & no delay usr_events_ext_o : out std_logic_vector( 3 downto 0); -- User defined event pulses with four clock cycle length
sos_event_o : out std_logic; -- Start-of-Sequence Event sos_event_o : out std_logic; -- Start-of-Sequence Event
usr_events_adj_o : out std_logic_vector(3 downto 0); -- User defined event pulses adjusted in delay & length
sos_events_adj_o : out std_logic; -- Start-of-Sequence adjusted in delay & length
-------------------------------------------------------------------------- --------------------------------------------------------------------------
-- Decoder axi stream interface, User clock -- Decoder axi stream interface, User clock
-------------------------------------------------------------------------- --------------------------------------------------------------------------
stream_clk_i : in std_logic := '0'; stream_clk_i : in std_logic := '0';
stream_data_o : out std_logic_vector(7 downto 0); stream_data_o : out std_logic_vector(7 downto 0);
stream_addr_o : out std_logic_vector(10 downto 0); stream_addr_o : out std_logic_vector(10 downto 0);
stream_valid_o : out std_logic stream_valid_o : out std_logic
); );
end evr320_ifc1210_wrapper; end evr320_ifc1210_wrapper;
architecture rtl of evr320_ifc1210_wrapper is architecture rtl of evr320_ifc1210_wrapper is
-- -------------------------------------------------------------------------- -- --------------------------------------------------------------------------
-- Parameters -- Parameters
-- -------------------------------------------------------------------------- -- --------------------------------------------------------------------------
constant c_TOSCA2_DATA_WIDTH : integer := 64; constant c_TOSCA2_DATA_WIDTH : integer := 64;
constant c_EVR_REG64_COUNT : integer := 16; -- unused, only documentation -- constant c_EVR_REG64_COUNT : integer := 16; -- unused, only documentation
constant c_EVR_MEM_SIZE : integer := 16384; -- unused, only documentation -- constant c_EVR_MEM_SIZE : integer := 16384; -- unused, only documentation
-- -------------------------------------------------------------------------- -- --------------------------------------------------------------------------
-- Signal definitions -- Signal definitions
-- -------------------------------------------------------------------------- -- --------------------------------------------------------------------------
signal clk_evr : std_logic; signal clk_evr : std_logic;
--signal clk_evr_monitor : std_logic; -- for debugging --signal clk_evr_monitor : std_logic; -- for debugging
signal rst_evr : std_logic; signal rst_evr : std_logic;
signal mgt_control : std_logic_vector(31 downto 0) := (others => '0');
signal mgt_status : std_logic_vector(31 downto 0); signal mgt_control : std_logic_vector(31 downto 0) := (others => '0');
signal mgt_rx_data : std_logic_vector(15 downto 0); signal mgt_status : std_logic_vector(31 downto 0);
signal mgt_rx_charisk : std_logic_vector(1 downto 0);
signal mgt_lossofsync : std_logic; signal mgt_rx_data : std_logic_vector(15 downto 0);
signal mgt_reset_tmem_evr : std_logic; -- for legacy reasons, ifc1210 mgt control is in tmem_psi_generic part signal mgt_rx_charisk : std_logic_vector( 1 downto 0);
signal mem_clk : std_logic; signal mgt_lossofsync : std_logic;
signal mem_addr_evr : std_logic_vector(11 downto 0); signal mgt_reset_tmem_evr : std_logic; -- for legacy reasons, ifc1210 mgt control is in tmem_psi_generic part
signal mem_addr_tosca : std_logic_vector(10 downto 0);
signal mem_data : std_logic_vector(c_TOSCA2_DATA_WIDTH - 1 downto 0); signal mem_clk : std_logic;
signal evr_params : typ_evr320_params; signal mem_addr_evr : std_logic_vector(11 downto 0);
signal evr_params_sync : typ_evr320_params; signal mem_addr_tosca : std_logic_vector(10 downto 0);
signal evr_params_xuser : typ_evr320_params; signal mem_data : std_logic_vector(c_TOSCA2_DATA_WIDTH-1 downto 0);
signal event_recorder_status : typ_evt_rec_status;
signal event_recorder_control : typ_evt_rec_ctrl; signal evr_params : typ_evr320_params;
signal event_recorder_control_sync : typ_evt_rec_ctrl; signal evr_params_sync : typ_evr320_params;
signal event_recorder_control_xuser : typ_evt_rec_ctrl; signal evr_params_xuser : typ_evr320_params;
signal evr_latency_measure_stat : typ_rec_latency_measure_stat; signal event_recorder_status : typ_evt_rec_status;
signal evr_latency_measure_ctrl : typ_rec_latency_measure_ctrl; signal event_recorder_control : typ_evt_rec_ctrl;
signal evr_frequency : std_logic_vector(31 downto 0) := (others => '0'); signal event_recorder_control_sync : typ_evt_rec_ctrl;
signal debug_data : std_logic_vector(127 downto 0); signal event_recorder_control_xuser : typ_evt_rec_ctrl;
signal decoder_event_valid : std_logic;
signal decoder_event : std_logic_vector(7 downto 0); signal evr_frequency : std_logic_vector(31 downto 0) := (others => '0');
signal debug_data : std_logic_vector(127 downto 0);
-- -------------------------------------------------------------------------- -- --------------------------------------------------------------------------
-- Attribute definitions -- Attribute definitions
-- -------------------------------------------------------------------------- -- --------------------------------------------------------------------------
attribute keep : string; attribute keep : string;
attribute keep of clk_evr : signal is "TRUE"; attribute keep of clk_evr : signal is "TRUE";
attribute keep of debug_data : signal is "TRUE"; attribute keep of debug_data : signal is "TRUE";
signal usr_events_s : std_logic_vector(3 downto 0);
signal sos_event_s : std_logic;
signal evr_rst_s : std_logic;
signal usr_event_delay_s : typ_arr_delay; -- ----------------------------------------------------------------------------
signal usr_event_width_s : typ_arr_width; -- ----------------------------------------------------------------------------
-- //////////////////// Main Body /////////////////////////
-- ---------------------------------------------------------------------------- -- ----------------------------------------------------------------------------
-- ---------------------------------------------------------------------------- -- ----------------------------------------------------------------------------
-- //////////////////// Main Body /////////////////////////
-- ----------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
begin begin
-- -------------------------------------------------------------------------- -- --------------------------------------------------------------------------
-- static signal assignments -- static signal assignments
-- -------------------------------------------------------------------------- -- --------------------------------------------------------------------------
mgt_lossofsync <= mgt_status(15); mgt_lossofsync <= mgt_status(15);
rst_evr_o <= mgt_status(15); rst_evr <= mgt_status(15);
mem_addr_evr <= '0' & mem_addr_tosca; mem_addr_evr <= '0' & mem_addr_tosca;
mgt_control(c_GTXRESET) <= mgt_control_i(c_GTXRESET) or mgt_sfp_los_i or mgt_reset_tmem_evr;
mgt_control( 4 downto 1) <= mgt_control_i( 4 downto 1);
mgt_control(c_RXCDRRESET) <= mgt_control_i(c_RXCDRRESET);
mgt_control(31 downto 6) <= mgt_control_i(31 downto 6);
mgt_control(c_GTXRESET) <= mgt_control_i(c_GTXRESET) or mgt_sfp_los_i or mgt_reset_tmem_evr;
mgt_control(4 downto 1) <= mgt_control_i(4 downto 1);
mgt_control(c_RXCDRRESET) <= mgt_control_i(c_RXCDRRESET);
mgt_control(31 downto 6) <= mgt_control_i(31 downto 6);
-- -------------------------------------------------------------------------- -- --------------------------------------------------------------------------
-- Synchronisation to EVR Clock -- Synchronisation to EVR Clock
-- -------------------------------------------------------------------------- -- --------------------------------------------------------------------------
prc_sync_evr : process(clk_evr) prc_sync_evr: process(clk_evr)
begin begin
if rising_edge(clk_evr) then if rising_edge(clk_evr) then
--- ---
evr_params_sync <= evr_params_xuser; evr_params_sync <= evr_params_xuser;
evr_params <= evr_params_sync; evr_params <= evr_params_sync;
--- ---
event_recorder_control_sync <= event_recorder_control_xuser; event_recorder_control_sync <= event_recorder_control_xuser;
event_recorder_control <= event_recorder_control_sync; event_recorder_control <= event_recorder_control_sync;
--- ---
end if; end if;
end process; end process;
-- -------------------------------------------------------------------------- -- --------------------------------------------------------------------------
-- EVR320 Decoder -- EVR320 Decoder
-- -------------------------------------------------------------------------- -- --------------------------------------------------------------------------
evr320_decoder_inst : entity work.evr320_decoder evr320_decoder_inst: entity work.evr320_decoder
generic map( generic map(
FACILITY => g_FACILITY, EVENT_RECORDER => g_EVENT_RECORDER,
EVENT_RECORDER => g_EVENT_RECORDER, MEM_DATA_WIDTH => c_TOSCA2_DATA_WIDTH )
MEM_DATA_WIDTH => c_TOSCA2_DATA_WIDTH,
EXP_REC_CLK_FREQ => 50_632_820)
port map( port map(
-- Debug interface -- Debug interface
debug_clk => debug_clk, debug_clk => debug_clk,
debug => debug_data, debug => debug_data,
-- GTX parallel interface -- GTX parallel interface
i_mgt_rst => mgt_lossofsync, i_mgt_rst => mgt_lossofsync,
i_mgt_rx_clk => clk_evr, i_mgt_rx_clk => clk_evr,
i_mgt_rx_data => mgt_rx_data, i_mgt_rx_data => mgt_rx_data,
i_mgt_rx_charisk => mgt_rx_charisk, i_mgt_rx_charisk => mgt_rx_charisk,
-- User interface CPU clock -- User interface CPU clock
i_usr_clk => mem_clk, i_usr_clk => mem_clk,
i_evr_params => evr_params, i_evr_params => evr_params,
o_event_recorder_stat => event_recorder_status, o_event_recorder_stat => event_recorder_status,
i_event_recorder_ctrl => event_recorder_control, i_event_recorder_ctrl => event_recorder_control,
i_mem_addr => mem_addr_evr, i_mem_addr => mem_addr_evr,
o_mem_data => mem_data, o_mem_data => mem_data,
-- user stream interface, user clock -- user stream interface, user clock
i_stream_clk => stream_clk_i, i_stream_clk => stream_clk_i,
o_stream_data => stream_data_o, o_stream_data => stream_data_o,
o_stream_addr => stream_addr_o, o_stream_addr => stream_addr_o,
o_stream_valid => stream_valid_o, o_stream_valid => stream_valid_o,
-- User interface MGT clock -- User interface MGT clock
o_usr_events => usr_events_s, o_usr_events => usr_events_o,
-- o_usr_events_ext => usr_events_ext_o, -- not in use anymore o_usr_events_ext => usr_events_ext_o,
o_sos_event => sos_event_s, o_sos_event => sos_event_o
o_event => decoder_event, );
o_event_valid => decoder_event_valid
);
usr_events_o <= usr_events_s;
sos_event_o <= sos_event_s;
-- -------------------------------------------------------------------------- -- --------------------------------------------------------------------------
-- MGT Wrapper for GTX Virtex-6 -- MGT Wrapper for GTX Virtex-6
-- -------------------------------------------------------------------------- -- --------------------------------------------------------------------------
mgt_wrapper_inst : entity work.v6vlx_gtxe1_wrapper mgt_wrapper_inst: entity work.v6vlx_gtxe1_wrapper
generic map( generic map(
g_MGT_LOCATION => g_MGT_LOCATION, g_MGT_LOCATION => g_MGT_LOCATION,
g_FACILITY => g_FACILITY) g_FACILITY => g_FACILITY )
port map( port map(
-- MGT serial interface -- MGT serial interface
i_mgt_refclk => mgt_refclk_i, i_mgt_refclk => mgt_refclk_i,
o_mgt_refclk => open, o_mgt_refclk => open,
i_mgt_rx_p => mgt_rx_p, i_mgt_rx_p => mgt_rx_p,
i_mgt_rx_n => mgt_rx_n, i_mgt_rx_n => mgt_rx_n,
o_mgt_tx_p => mgt_tx_p, o_mgt_tx_p => mgt_tx_p,
o_mgt_tx_n => mgt_tx_n, o_mgt_tx_n => mgt_tx_n,
-- MGT parallel interface -- MGT parallel interface
o_mgt_status => mgt_status, o_mgt_status => mgt_status,
i_mgt_control => mgt_control, i_mgt_control => mgt_control,
o_mgt_recclk => clk_evr, o_mgt_recclk => clk_evr,
o_mgt_rx_data => mgt_rx_data, o_mgt_rx_data => mgt_rx_data,
o_mgt_rx_charisk => mgt_rx_charisk o_mgt_rx_charisk => mgt_rx_charisk
); );
mgt_rx_charisk_o <= mgt_rx_charisk;
mgt_rx_data_o <= mgt_rx_data;
-- -------------------------------------------------------------------------- -- --------------------------------------------------------------------------
-- TMEM -- TMEM
-- -------------------------------------------------------------------------- -- --------------------------------------------------------------------------
--formatter:off evr320_tmem_inst: entity work.evr320_tmem
evr320_tmem_inst : entity work.evr320_tmem port map(
port map( -- TOSCA2 TMEM Interface
-- TOSCA2 TMEM Interface xuser_CLK => xuser_CLK,
xuser_CLK => xuser_CLK, xuser_RESET => xuser_RESET,
xuser_RESET => xuser_RESET, xuser_TMEM_ENA => xuser_TMEM_ENA,
xuser_TMEM_ENA => xuser_TMEM_ENA, xuser_TMEM_WE => xuser_TMEM_WE,
xuser_TMEM_WE => xuser_TMEM_WE, xuser_TMEM_ADD => xuser_TMEM_ADD,
xuser_TMEM_ADD => xuser_TMEM_ADD, xuser_TMEM_DATW => xuser_TMEM_DATW,
xuser_TMEM_DATW => xuser_TMEM_DATW, xuser_TMEM_DATR => xuser_TMEM_DATR,
xuser_TMEM_DATR => xuser_TMEM_DATR, -- EVR320 Memory/Parameter Interface
-- EVR320 Memory/Parameter Interface evr_params_o => evr_params_xuser,
evr_params_o => evr_params_xuser, evr_frequency_i => evr_frequency,
evr_frequency_i => evr_frequency, evr_evt_rec_status_i => event_recorder_status,
evr_evt_rec_status_i => event_recorder_status, evr_evt_rec_control_o => event_recorder_control_xuser,
evr_evt_rec_control_o => event_recorder_control_xuser, mgt_status_i => mgt_status,
evr_latency_measure_stat_i => evr_latency_measure_stat, mgt_reset_o => mgt_reset_tmem_evr,
evr_latency_measure_ctrl_o => evr_latency_measure_ctrl, mem_clk_o => mem_clk,
mgt_status_i => mgt_status, mem_addr_o => mem_addr_tosca,
mgt_reset_o => mgt_reset_tmem_evr, mem_data_i => mem_data
mem_clk_o => mem_clk, );
mem_addr_o => mem_addr_tosca,
mem_data_i => mem_data,
--
evr_clk_i => clk_evr,
evr_rst_i => evr_rst_s,
evr_pulse_delay_o => usr_event_delay_s,
evr_pulse_width_o => usr_event_width_s);
-- -------------------------------------------------------------------------- -- --------------------------------------------------------------------------
-- Measure EVR Clock (based on xuser_CLK) -- Measure EVR Clock (based on xuser_CLK)
-- -------------------------------------------------------------------------- -- --------------------------------------------------------------------------
clock_meas_inst : entity work.psi_common_clk_meas clock_meas_inst : entity work.psi_common_clk_meas
generic map( generic map (
MasterFrequency_g => g_XUSER_CLK_FREQ, MasterFrequency_g => g_XUSER_CLK_FREQ,
MaxMeasFrequency_g => 150000000 MaxMeasFrequency_g => 150000000
) )
port map( port map (
ClkMaster => xuser_CLK, ClkMaster => xuser_CLK,
Rst => xuser_RESET, Rst => xuser_RESET,
ClkTest => clk_evr, ClkTest => clk_evr,
FrequencyHz => evr_frequency FrequencyHz => evr_frequency
); );
-- --------------------------------------------------------------------------
-- Event Latency Measurement for SW tests
-- --------------------------------------------------------------------------
lat_meas_block : block
type state_type is (armed, count);
signal state : state_type;
signal counter : unsigned(31 downto 0);
signal event_nr_sync, event_nr : std_logic_vector(7 downto 0);
signal event_detected : std_logic_vector(3 downto 0);
signal event_detected_sync : std_logic_vector(1 downto 0);
constant MAX_COUNT : unsigned(31 downto 0) := to_unsigned(g_XUSER_CLK_FREQ / 10, 32); -- MAX 100ms ~ 10Hz
begin
-- Process: filter events for matching event_nr register:
---------------------------------------------------------
ext_event_proc : process(clk_evr)
begin
if (rising_edge(clk_evr)) then
-- sync to MGT clock domain:
event_nr_sync <= evr_latency_measure_ctrl.event_nr;
event_nr <= event_nr_sync;
-- check if event has been detected and stretch pulse:
event_detected <= event_detected(2 downto 0) & '0';
if (decoder_event_valid = '1' and decoder_event = event_nr) then
event_detected <= (others => '1');
end if;
end if;
end process;
-- Process: Counter when configured event has been detected:
------------------------------------------------------------
lat_meas_proc : process(xuser_CLK, counter)
begin
if rising_edge(xuser_CLK) then
-- sync to user clock domain:
event_detected_sync <= event_detected_sync(0) & event_detected(3);
-- counter FSM:
---------------
case state is
-- counter is armed:
when armed =>
counter <= (others => '0');
-- start counting when event detected (rising edge):
if (event_detected_sync(1) = '0' and event_detected_sync(0) = '1') then
state <= count;
end if;
-- counting:
when count =>
-- count only up to 10ms, and stop:
if (counter < MAX_COUNT) then
counter <= counter + 1;
end if;
if (evr_latency_measure_ctrl.counter_arm = '1') then
state <= armed;
end if;
end case;
end if;
evr_latency_measure_stat.counter_val <= std_logic_vector(counter);
end process;
end block;
-- --------------------------------------------------------------------------
-- Add delay output
-- --------------------------------------------------------------------------
output_delay_block : block
--signal rst0_s, rst1_s : std_logic; -- double stage sync for reset
signal usr_evt_shaped_s : std_logic_vector(4 downto 0);
signal usr_events_adj_s : std_logic_vector(4 downto 0);
signal usr_events_concat_s : std_logic_vector(4 downto 0);
begin
evr_rst_s <= mgt_status(15); -- RXLOSSOFSYNC
usr_events_concat_s <= usr_events_s & sos_event_s;
gene_adj_out : for i in 0 to 4 generate
--*** Adjust pulse length in clk cycles EVENT 0,1,2,3 ***
inst_pulslength_evt0 : entity work.psi_common_pulse_shaper_cfg
generic map(HoldIn_g => false,
HoldOffEna_g => false,
MaxHoldOff_g => 10,
MaxDuration_g => MaxDuration_c,
RstPol_g => '1')
port map(clk_i => clk_evr,
rst_i => evr_rst_s,
width_i => usr_event_width_s(i),
hold_i => (others => '0'),
dat_i => usr_events_concat_s(i),
dat_o => usr_evt_shaped_s(i));
--*** delay adjust EVENT 0,1,2,3***
inst_adjdelay_evt0 : entity work.psi_common_delay_cfg
generic map(Width_g => 1,
MaxDelay_g => MaxDelay_c,
RStPol_g => '1',
RamBehavior_g => "RBW",
Hold_g => True)
port map( clk_i => clk_evr,
rst_i => evr_rst_s,
dat_i(0) => usr_evt_shaped_s(i),
str_i => '1',
del_i => usr_event_delay_s(i),
dat_o(0) => usr_events_adj_s(i));
end generate;
usr_events_adj_o <= usr_events_adj_s(4 downto 1);
sos_events_adj_o <= usr_events_adj_s(0);
end block;
-- -------------------------------------------------------------------------- -- --------------------------------------------------------------------------
-- port mapping -- port mapping
-- -------------------------------------------------------------------------- -- --------------------------------------------------------------------------
clk_evr_o <= clk_evr; clk_evr_o <= clk_evr;
mgt_status_o <= mgt_status; mgt_status_o <= mgt_status;
debug <= debug_data; debug <= debug_data;
end rtl; end rtl;
-- ---------------------------------------------------------------------------- -- ----------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////// -- ////////////////////////////////////////////////////////////////////////////

21
hdl/evr320_pkg.vhd
View File

@@ -12,7 +12,6 @@
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use work.psi_common_math_pkg.all;
package evr320_pkg is package evr320_pkg is
@@ -23,7 +22,7 @@ package evr320_pkg is
constant c_CHECKSUM_MIN_TIME : std_logic_vector(31 downto 0) := X"0015CA20"; -- Check sum min time for events 10 ms constant c_CHECKSUM_MIN_TIME : std_logic_vector(31 downto 0) := X"0015CA20"; -- Check sum min time for events 10 ms
constant c_SOS_EVENT_DEFAULT : std_logic_vector( 7 downto 0) := X"20"; -- decimal 32 constant c_SOS_EVENT_DEFAULT : std_logic_vector( 7 downto 0) := X"20"; -- decimal 32
-- -------------------------------------------------------------------------- -- --------------------------------------------------------------------------
-- Type Definitions -- Type Definitions
-- -------------------------------------------------------------------------- -- --------------------------------------------------------------------------
@@ -53,20 +52,6 @@ package evr320_pkg is
error_ack : std_logic; error_ack : std_logic;
end record typ_evt_rec_ctrl; end record typ_evt_rec_ctrl;
type typ_rec_latency_measure_ctrl is record
event_nr : std_logic_vector(7 downto 0);
counter_arm : std_logic;
end record;
type typ_rec_latency_measure_stat is record
counter_val : std_logic_vector(31 downto 0);
end record;
--*** Type record and constant for new feature pulse width & delay ***
constant MaxDuration_c : positive := 2**16-1; -- defines maximum pulse width to add on user events pulse output, in recovery clock cycles
constant MaxDelay_c : positive := 2**16-1; -- defines maximum delay to add on user events pulse output, in recovery clock cycles
type typ_arr_width is array (4 downto 0) of std_logic_vector(log2ceil(MaxDuration_c)-1 downto 0);
type typ_arr_delay is array (4 downto 0) of std_logic_vector(log2ceil(MaxDelay_c)-1 downto 0);
-- -------------------------------------------------------------------------- -- --------------------------------------------------------------------------
-- Type Initialisation -- Type Initialisation
@@ -79,10 +64,6 @@ package evr320_pkg is
event_enable => '0', event_enable => '0',
data_ack => '0', data_ack => '0',
error_ack => '0'); error_ack => '0');
constant c_INIT_REC_LATENCY_MEASURE_CTRL : typ_rec_latency_measure_ctrl := (event_nr => (others =>'0'),
counter_arm => '1');
constant c_INIT_REC_LATENCY_MEASURE_STAT : typ_rec_latency_measure_stat := (counter_val => (others =>'0'));
-- -------------------------------------------------------------------------- -- --------------------------------------------------------------------------
-- Function Prototypes -- Function Prototypes
-- -------------------------------------------------------------------------- -- --------------------------------------------------------------------------

100
hdl/evr320_timestamp.vhd
View File

@@ -4,17 +4,17 @@
-- Unit : evr320_timestamp.vhd -- Unit : evr320_timestamp.vhd
-- Author : Patric Bucher, Section DSV -- Author : Patric Bucher, Section DSV
-- Goran Marinkovic, Section Diagnostic -- Goran Marinkovic, Section Diagnostic
-- Benoît Stef, Section DSP
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Copyright© PSI, Section Diagnostic -- Copyright© PSI, Section Diagnostic
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Comment : -- Comment : modif 02.10.2019 - numeric_std instead of std_logic_unsigned
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
use ieee.math_real.all; use ieee.math_real.all;
entity evr320_timestamp is entity evr320_timestamp is
generic generic
( (
@@ -90,28 +90,46 @@ begin
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
dob_32bit: if MEM_DOB_WIDTH = 32 generate dob_32bit: if MEM_DOB_WIDTH = 32 generate
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
process (clka) process (clka)
variable concat7to0_v : std_logic_vector(addra'high+3 downto 0);
variable concat15to8_v : std_logic_vector(addra'high+3 downto 0);
variable concat23to16_v : std_logic_vector(addra'high+3 downto 0);
variable concat31to24_v : std_logic_vector(addra'high+3 downto 0);
begin begin
if rising_edge(clka) then if rising_edge(clka) then
if (ena = '1') then if (ena = '1') then
if (wea = '1') then if (wea = '1') then
RAM(to_integer(unsigned(std_logic_vector'(page_addr_clka & addra & "00")))) := dia( 7 downto 0); concat7to0_v := page_addr_clka & addra & "00";
RAM(to_integer(unsigned(std_logic_vector'(page_addr_clka & addra & "01")))) := dia(15 downto 8); concat15to8_v := page_addr_clka & addra & "01";
RAM(to_integer(unsigned(std_logic_vector'(page_addr_clka & addra & "10")))) := dia(23 downto 16); concat23to16_v := page_addr_clka & addra & "10";
RAM(to_integer(unsigned(std_logic_vector'(page_addr_clka & addra & "11")))) := dia(31 downto 24); concat31to24_v := page_addr_clka & addra & "11";
--
RAM(to_integer(unsigned( concat7to0_v))) := dia( 7 downto 0);
RAM(to_integer(unsigned( concat15to8_v))) := dia(15 downto 8);
RAM(to_integer(unsigned(concat23to16_v))) := dia(23 downto 16);
RAM(to_integer(unsigned(concat31to24_v))) := dia(31 downto 24);
end if; end if;
end if; end if;
end if; end if;
end process; end process;
process (clkb) process (clkb)
variable concat7to0_v : std_logic_vector(addrb'high+3 downto 0);
variable concat15to8_v : std_logic_vector(addrb'high+3 downto 0);
variable concat23to16_v : std_logic_vector(addrb'high+3 downto 0);
variable concat31to24_v : std_logic_vector(addrb'high+3 downto 0);
begin begin
if rising_edge(clkb) then if rising_edge(clkb) then
if (enb = '1') then if (enb = '1') then
dob( 7 downto 0) <= RAM(to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "00")))); concat7to0_v := page_addr_clkb( 3) & addrb & "00";
dob(15 downto 8) <= RAM(to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "01")))); concat15to8_v := page_addr_clkb( 3) & addrb & "01";
dob(23 downto 16) <= RAM(to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "10")))); concat23to16_v := page_addr_clkb( 3) & addrb & "10";
dob(31 downto 24) <= RAM(to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "11")))); concat31to24_v := page_addr_clkb( 3) & addrb & "11";
--
dob( 7 downto 0) <= RAM(to_integer(unsigned(concat7to0_v)));
dob(15 downto 8) <= RAM(to_integer(unsigned(concat15to8_v )));
dob(23 downto 16) <= RAM(to_integer(unsigned(concat23to16_v)));
dob(31 downto 24) <= RAM(to_integer(unsigned(concat31to24_v)));
end if; end if;
end if; end if;
end process; end process;
@@ -120,32 +138,58 @@ begin
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
dob_64bit: if MEM_DOB_WIDTH = 64 generate dob_64bit: if MEM_DOB_WIDTH = 64 generate
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
process (clka) process (clka)
variable concat7to0_v : std_logic_vector(addra'high+2 downto 0);
variable concat15to8_v : std_logic_vector(addra'high+2 downto 0);
variable concat23to16_v : std_logic_vector(addra'high+2 downto 0);
variable concat31to24_v : std_logic_vector(addra'high+2 downto 0);
begin begin
if rising_edge(clka) then if rising_edge(clka) then
if (ena = '1') then if (ena = '1') then
if (wea = '1') then if (wea = '1') then
RAM_EVEN(to_integer(unsigned(std_logic_vector'(page_addr_clka & addra & '0')))) := dia( 7 downto 0); concat7to0_v := page_addr_clka & addra & '0';
RAM_ODD (to_integer(unsigned(std_logic_vector'(page_addr_clka & addra & '0')))) := dia(15 downto 8); concat15to8_v := page_addr_clka & addra & '0';
RAM_EVEN(to_integer(unsigned(std_logic_vector'(page_addr_clka & addra & '1')))) := dia(23 downto 16); concat23to16_v := page_addr_clka & addra & '1';
RAM_ODD (to_integer(unsigned(std_logic_vector'(page_addr_clka & addra & '1')))) := dia(31 downto 24); concat31to24_v := page_addr_clka & addra & '1';
--
RAM_EVEN(to_integer(unsigned(concat7to0_v ))) := dia( 7 downto 0);
RAM_ODD (to_integer(unsigned(concat15to8_v ))) := dia(15 downto 8);
RAM_EVEN(to_integer(unsigned(concat23to16_v ))) := dia(23 downto 16);
RAM_ODD (to_integer(unsigned(concat31to24_v ))) := dia(31 downto 24);
end if; end if;
end if; end if;
end if; end if;
end process; end process;
process (clkb) process (clkb)
variable concat7to0_v : std_logic_vector(addrb'high+3 downto 0);
variable concat15to8_v : std_logic_vector(addrb'high+3 downto 0);
variable concat23to16_v : std_logic_vector(addrb'high+3 downto 0);
variable concat31to24_v : std_logic_vector(addrb'high+3 downto 0);
variable concat39to32_v : std_logic_vector(addrb'high+3 downto 0);
variable concat47to40_v : std_logic_vector(addrb'high+3 downto 0);
variable concat55to48_v : std_logic_vector(addrb'high+3 downto 0);
variable concat63to56_v : std_logic_vector(addrb'high+3 downto 0);
begin begin
if rising_edge(clkb) then if rising_edge(clkb) then
if (enb = '1') then if (enb = '1') then
dob( 7 downto 0) <= RAM_EVEN(to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "00")))); concat7to0_v := page_addr_clkb( 3) & addrb & "00";
dob(15 downto 8) <= RAM_ODD (to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "00")))); concat15to8_v := page_addr_clkb( 3) & addrb & "00";
dob(23 downto 16) <= RAM_EVEN(to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "01")))); concat23to16_v := page_addr_clkb( 3) & addrb & "01";
dob(31 downto 24) <= RAM_ODD (to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "01")))); concat31to24_v := page_addr_clkb( 3) & addrb & "01";
dob(39 downto 32) <= RAM_EVEN(to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "10")))); concat39to32_v := page_addr_clkb( 3) & addrb & "10";
dob(47 downto 40) <= RAM_ODD (to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "10")))); concat47to40_v := page_addr_clkb( 3) & addrb & "10";
dob(55 downto 48) <= RAM_EVEN(to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "11")))); concat55to48_v := page_addr_clkb( 3) & addrb & "11";
dob(63 downto 56) <= RAM_ODD (to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "11")))); concat63to56_v := page_addr_clkb( 3) & addrb & "11";
--
dob( 7 downto 0) <= RAM_EVEN(to_integer(unsigned( concat7to0_v)));
dob(15 downto 8) <= RAM_ODD (to_integer(unsigned( concat15to8_v)));
dob(23 downto 16) <= RAM_EVEN(to_integer(unsigned( concat23to16_v)));
dob(31 downto 24) <= RAM_ODD (to_integer(unsigned( concat31to24_v)));
dob(39 downto 32) <= RAM_EVEN(to_integer(unsigned( concat39to32_v)));
dob(47 downto 40) <= RAM_ODD (to_integer(unsigned( concat47to40_v)));
dob(55 downto 48) <= RAM_EVEN(to_integer(unsigned( concat55to48_v)));
dob(63 downto 56) <= RAM_ODD (to_integer(unsigned( concat63to56_v)));
end if; end if;
end if; end if;
end process; end process;

197
hdl/evr320_tmem.vhd
View File

@@ -2,11 +2,13 @@
-- Paul Scherrer Institute (PSI) -- Paul Scherrer Institute (PSI)
-- --------------------------------------------------------------------------- -- ---------------------------------------------------------------------------
-- Unit : evr320_tmem.vhd -- Unit : evr320_tmem.vhd
-- Author : Patric Bucher, Benoit Stef -- Author : Patric Bucher
-- Benoît Stef
-- --------------------------------------------------------------------------- -- ---------------------------------------------------------------------------
-- Copyright (c) PSI, Section DSV -- Copyright© PSI, Section DSV
-- --------------------------------------------------------------------------- -- ---------------------------------------------------------------------------
-- Comment : TMEM address decoding for register and memory access to evr320. -- Comment : TMEM address decoding for register and memory access to evr320.
-- modif 02.10.2019 - numeric_std only
-- --------------------------------------------------------------------------- -- ---------------------------------------------------------------------------
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
@@ -18,6 +20,7 @@ use tosca2.tosca2_glb_pkg.all;
use work.evr320_pkg.all; use work.evr320_pkg.all;
entity evr320_tmem is entity evr320_tmem is
port( port(
-- ------------------------------------------------------------------------ -- ------------------------------------------------------------------------
@@ -37,20 +40,11 @@ entity evr320_tmem is
evr_frequency_i : in std_logic_vector(31 downto 0); evr_frequency_i : in std_logic_vector(31 downto 0);
evr_evt_rec_status_i : in typ_evt_rec_status; evr_evt_rec_status_i : in typ_evt_rec_status;
evr_evt_rec_control_o : out typ_evt_rec_ctrl; evr_evt_rec_control_o : out typ_evt_rec_ctrl;
evr_latency_measure_stat_i : in typ_rec_latency_measure_stat;
evr_latency_measure_ctrl_o : out typ_rec_latency_measure_ctrl;
mgt_status_i : in std_logic_vector(31 downto 0); mgt_status_i : in std_logic_vector(31 downto 0);
mgt_reset_o : out std_logic; mgt_reset_o : out std_logic;
mem_clk_o : out std_logic; mem_clk_o : out std_logic;
mem_addr_o : out std_logic_vector(10 downto 0); mem_addr_o : out std_logic_vector(10 downto 0);
mem_data_i : in std_logic_vector(63 downto 0); mem_data_i : in std_logic_vector(63 downto 0)
---------------------------------------------------------------------------
-- EVR320 pulse output paremters
---------------------------------------------------------------------------
evr_clk_i : in std_logic;
evr_rst_i : in std_logic;
evr_pulse_delay_o : out typ_arr_delay;
evr_pulse_width_o : out typ_arr_width
); );
end evr320_tmem; end evr320_tmem;
@@ -61,7 +55,6 @@ architecture rtl of evr320_tmem is
-- Constants -- Constants
-- --------------------------------------------------------------------------- -- ---------------------------------------------------------------------------
constant reserved : std_logic_vector(63 downto 0) := X"0000_0000_0000_0000"; constant reserved : std_logic_vector(63 downto 0) := X"0000_0000_0000_0000";
constant c_LOW : std_logic_vector(63 downto 0) := X"0000_0000_0000_0000";
constant NUM_REG64 : integer := 16; constant NUM_REG64 : integer := 16;
constant TMEM_ADDR_LSB : integer := 3; -- 64 bit constant TMEM_ADDR_LSB : integer := 3; -- 64 bit
constant REG_ADDR_WIDTH : integer := integer(ceil(log2(real(NUM_REG64)))) + TMEM_ADDR_LSB; constant REG_ADDR_WIDTH : integer := integer(ceil(log2(real(NUM_REG64)))) + TMEM_ADDR_LSB;
@@ -101,19 +94,11 @@ architecture rtl of evr320_tmem is
signal er_handshake_status : std_logic_vector(31 downto 0) := (others => '0'); signal er_handshake_status : std_logic_vector(31 downto 0) := (others => '0');
signal er_control_concat : std_logic_vector(31 downto 0) := (others => '0'); signal er_control_concat : std_logic_vector(31 downto 0) := (others => '0');
-- latency measurement
signal lat_counter_arm : std_logic := '0';
signal lat_event_nr : std_logic_vector(7 downto 0) := x"26"; -- default SOS event
signal lat_counter_val : std_logic_vector(31 downto 0) := (others=>'0');
-- signal evr_force : std_logic_vector(3 downto 0) := (others => '0'); -- signal evr_force : std_logic_vector(3 downto 0) := (others => '0');
-- signal evr_force_rd : std_logic_vector(3 downto 0) := (others => '0'); -- readback -- signal evr_force_rd : std_logic_vector(3 downto 0) := (others => '0'); -- readback
-- signal evr_force_pulse : typ_arr4(3 downto 0) := (others => (others => '0')); -- signal evr_force_pulse : typ_arr4(3 downto 0) := (others => (others => '0'));
-- event pulse config
signal evr_puls_width_cfg_s : typ_arr_width :=((others=>(others=>'0')));
signal evr_puls_delay_cfg_s : typ_arr_delay :=((others=>(others=>'0')));
-- ---------------------------------------------------------------------------- -- ----------------------------------------------------------------------------
-- ---------------------------------------------------------------------------- -- ----------------------------------------------------------------------------
@@ -128,10 +113,9 @@ begin
event_numbers_concat <= event_numbers(3) & event_numbers(2) & event_numbers(1) & event_numbers(0); event_numbers_concat <= event_numbers(3) & event_numbers(2) & event_numbers(1) & event_numbers(0);
er_handshake_status <= X"0000" & bit2byte(er_status.data_error) & bit2byte(er_status.data_valid); er_handshake_status <= X"0000" & bit2byte(er_status.data_error) & bit2byte(er_status.data_valid);
er_control_concat <= X"0000" & er_event_number & bit2byte(er_event_enable); er_control_concat <= X"0000" & er_event_number & bit2byte(er_event_enable);
lat_counter_val <= evr_latency_measure_stat_i.counter_val;
-- -------------------------------------------------------------------------- -- --------------------------------------------------------------------------
-- TODO: proper CDC
-- Synchronisation to xuser_CLK -- Synchronisation to xuser_CLK
-- -------------------------------------------------------------------------- -- --------------------------------------------------------------------------
prc_sync_xuser: process (xuser_CLK) prc_sync_xuser: process (xuser_CLK)
@@ -155,29 +139,26 @@ begin
end if; end if;
end process; end process;
-- -------------------------------------------------------------------------- -- --------------------------------------------------------------------------
-- Read operation -- Read operation
-- -------------------------------------------------------------------------- -- --------------------------------------------------------------------------
read_tmem_evr: process(xuser_CLK) read_tmem_evr: process(xuser_CLK)
begin begin
if (rising_edge(xuser_CLK)) then if (rising_edge(xuser_CLK)) then
lat_counter_arm <= '0';
if (xuser_TMEM_ENA_reg = '1') then if (xuser_TMEM_ENA_reg = '1') then
if (xuser_TMEM_ADD_reg(13 downto REG_ADDR_WIDTH) = c_LOW(13 downto REG_ADDR_WIDTH)) then if (unsigned(xuser_TMEM_ADD_reg(13 downto REG_ADDR_WIDTH)) = 0) then
case xuser_TMEM_ADD_reg(REG_ADDR_MSB downto TMEM_ADDR_LSB) is case xuser_TMEM_ADD_reg(REG_ADDR_MSB downto TMEM_ADDR_LSB) is
when X"0" => xuser_TMEM_DATR <= event_numbers_concat & X"0000" & mgt_status_evr; -- 64bit / ByteAddr 000 when X"0" => xuser_TMEM_DATR <= event_numbers_concat & X"0000" & mgt_status_evr; -- 64bit / ByteAddr 000
when X"1" => xuser_TMEM_DATR <= reserved(63 downto 32) & X"0000_00" & bit2byte(mgt_reset); -- 64bit / ByteAddr 008 --> 0x00C = not implemented in ifc1210 when X"1" => xuser_TMEM_DATR <= reserved(63 downto 32) & X"0000_00" & bit2byte(mgt_reset); -- 64bit / ByteAddr 008 --> 0x00C = not implemented in ifc1210
when X"2" => xuser_TMEM_DATR <= reserved(63 downto 32) & bit2byte(event_enable); -- 64bit / ByteAddr 010 --> 0x014 = Bit0 SW Trigger Event 0, Bit8 SW Trigger Event 1, ... evr_force when X"2" => xuser_TMEM_DATR <= reserved(63 downto 32) & bit2byte(event_enable); -- 64bit / ByteAddr 010 --> 0x014 = Bit0 SW Trigger Event 0, Bit8 SW Trigger Event 1, ... evr_force
when X"3" => xuser_TMEM_DATR <= evr_frequency & reserved(31 downto 0); -- 64bit / ByteAddr 018 --> 0x018 = Implementation Options + c_EVR_Location_vec when X"3" => xuser_TMEM_DATR <= evr_frequency & reserved(31 downto 0); -- 64bit / ByteAddr 018 --> 0x018 = Implementation Options + c_EVR_Location_vec
when X"4" => xuser_TMEM_DATR <= cs_min_time & cs_min_cnt; -- 64bit / ByteAddr 020 when X"4" => xuser_TMEM_DATR <= cs_min_time & cs_min_cnt; -- 64bit / ByteAddr 020
when X"5" => xuser_TMEM_DATR <= reserved(63 downto 0); -- 64bit / ByteAddr 028 when X"5" => xuser_TMEM_DATR <= reserved(63 downto 0); -- 64bit / ByteAddr 028
when X"6" => xuser_TMEM_DATR <= lat_counter_val & X"000000" & lat_event_nr; -- 64bit / ByteAddr 030 when X"6" => xuser_TMEM_DATR <= reserved(63 downto 0); -- 64bit / ByteAddr 030
when X"7" => xuser_TMEM_DATR <= reserved(63 downto 32) & lat_counter_val; lat_counter_arm <= '1'; -- 64bit / ByteAddr 038 when X"7" => xuser_TMEM_DATR <= reserved(63 downto 0); -- 64bit / ByteAddr 038
when X"8" => xuser_TMEM_DATR <= er_handshake_status & er_control_concat; -- 64bit / ByteAddr 040 when X"8" => xuser_TMEM_DATR <= er_handshake_status & er_control_concat; -- 64bit / ByteAddr 040
when X"9" => xuser_TMEM_DATR <= reserved(63 downto 32) & er_status.usr_events_counter; -- 64bit / ByteAddr 048 when X"9" => xuser_TMEM_DATR <= reserved(63 downto 32) & er_status.usr_events_counter; -- 64bit / ByteAddr 048
when X"A" => xuser_TMEM_DATR <= evr_puls_delay_cfg_s(4) & evr_puls_delay_cfg_s(3) & evr_puls_delay_cfg_s(2) & evr_puls_delay_cfg_s(1) ; -- 64bit / ByteAddr 050
when X"B" => xuser_TMEM_DATR <= evr_puls_width_cfg_s(4) & evr_puls_width_cfg_s(3) & evr_puls_width_cfg_s(2) & evr_puls_width_cfg_s(1) ; --64 bit / ByteAddr 054
when X"C" => xuser_TMEM_DATR <= reserved(63 downto 32) & evr_puls_width_cfg_s(0) & evr_puls_delay_cfg_s(0); -- 64bit / ByteAddr 058
when others => xuser_TMEM_DATR <= (others => '0'); when others => xuser_TMEM_DATR <= (others => '0');
end case; end case;
else --> 0x0080-0x4000 else --> 0x0080-0x4000
@@ -200,7 +181,7 @@ begin
er_error_ack <= er_error_ack(2 downto 0) & '0'; er_error_ack <= er_error_ack(2 downto 0) & '0';
if (xuser_TMEM_ENA_reg = '1' and xuser_TMEM_ADD_reg(13 downto REG_ADDR_WIDTH) = c_LOW(13 downto REG_ADDR_WIDTH)) then if (xuser_TMEM_ENA_reg = '1' and unsigned(xuser_TMEM_ADD_reg(13 downto REG_ADDR_WIDTH)) = 0) then
----------------------------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------------------
if xuser_TMEM_ADD_reg(6 downto 3) = X"0" then --ByteAddr 000 if xuser_TMEM_ADD_reg(6 downto 3) = X"0" then --ByteAddr 000
-- if xuser_TMEM_WE_reg(0) = '1' then -read only- <= xuser_TMEM_DATW_reg( 7 downto 0); end if; -- if xuser_TMEM_WE_reg(0) = '1' then -read only- <= xuser_TMEM_DATW_reg( 7 downto 0); end if;
@@ -246,17 +227,6 @@ begin
if xuser_TMEM_WE_reg(7) = '1' then cs_min_time(31 downto 24) <= xuser_TMEM_DATW_reg(63 downto 56); end if; if xuser_TMEM_WE_reg(7) = '1' then cs_min_time(31 downto 24) <= xuser_TMEM_DATW_reg(63 downto 56); end if;
end if; end if;
----------------------------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------------------
if xuser_TMEM_ADD_reg(6 downto 3) = X"6" then --ByteAddr 030 Latency Measurement
if xuser_TMEM_WE_reg(0) = '1' then lat_event_nr ( 7 downto 0) <= xuser_TMEM_DATW_reg( 7 downto 0); end if;
-- if xuser_TMEM_WE_reg(1) = '1' then -reserved- (15 downto 8) <= xuser_TMEM_DATW_reg(15 downto 8); end if;
-- if xuser_TMEM_WE_reg(2) = '1' then -reserved- (23 downto 16) <= xuser_TMEM_DATW_reg(23 downto 16); end if;
-- if xuser_TMEM_WE_reg(3) = '1' then -reserved- (31 downto 24) <= xuser_TMEM_DATW_reg(31 downto 24); end if;
-- if xuser_TMEM_WE_reg(4) = '1' then -reserved- ( 7 downto 0) <= xuser_TMEM_DATW_reg(39 downto 32); end if;
-- if xuser_TMEM_WE_reg(5) = '1' then -reserved- (15 downto 8) <= xuser_TMEM_DATW_reg(47 downto 40); end if;
-- if xuser_TMEM_WE_reg(6) = '1' then -reserved- (23 downto 16) <= xuser_TMEM_DATW_reg(55 downto 48); end if;
-- if xuser_TMEM_WE_reg(7) = '1' then -reserved- (31 downto 24) <= xuser_TMEM_DATW_reg(63 downto 56); end if;
end if;
-----------------------------------------------------------------------------------------------------------------
if xuser_TMEM_ADD_reg(6 downto 3) = X"8" then --ByteAddr 040 if xuser_TMEM_ADD_reg(6 downto 3) = X"8" then --ByteAddr 040
if xuser_TMEM_WE_reg(0) = '1' then er_event_enable <= xuser_TMEM_DATW_reg(0); end if; if xuser_TMEM_WE_reg(0) = '1' then er_event_enable <= xuser_TMEM_DATW_reg(0); end if;
if xuser_TMEM_WE_reg(1) = '1' then er_event_number <= xuser_TMEM_DATW_reg(15 downto 8); end if; if xuser_TMEM_WE_reg(1) = '1' then er_event_number <= xuser_TMEM_DATW_reg(15 downto 8); end if;
@@ -268,24 +238,6 @@ begin
if xuser_TMEM_WE_reg(7) = '1' and xuser_TMEM_DATW_reg(56) = '1' then er_error_ack <= (others => '1'); end if; if xuser_TMEM_WE_reg(7) = '1' and xuser_TMEM_DATW_reg(56) = '1' then er_error_ack <= (others => '1'); end if;
end if; end if;
----------------------------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------------------
if xuser_TMEM_ADD_reg(6 downto 3) = X"A" then --ByteAddr 050
if xuser_TMEM_WE_reg(1 downto 0) = "11" then evr_puls_delay_cfg_s(1) <= xuser_TMEM_DATW_reg(15 downto 0); end if; -- usr evt 0 del
if xuser_TMEM_WE_reg(3 downto 2) = "11" then evr_puls_delay_cfg_s(2) <= xuser_TMEM_DATW_reg(31 downto 16); end if; -- usr evt 1 del
if xuser_TMEM_WE_reg(5 downto 4) = "11" then evr_puls_delay_cfg_s(3) <= xuser_TMEM_DATW_reg(47 downto 32); end if; -- usr evt 2 del
if xuser_TMEM_WE_reg(7 downto 6) = "11" then evr_puls_delay_cfg_s(4) <= xuser_TMEM_DATW_reg(63 downto 48); end if; -- usr evt 3 del
end if;
-----------------------------------------------------------------------------------------------------------------
if xuser_TMEM_ADD_reg(6 downto 3) = X"B" then --ByteAddr 058
if xuser_TMEM_WE_reg(1 downto 0) = "11" then evr_puls_width_cfg_s(1) <= xuser_TMEM_DATW_reg(15 downto 0); end if; -- usr evt 0 width
if xuser_TMEM_WE_reg(3 downto 2) = "11" then evr_puls_width_cfg_s(2) <= xuser_TMEM_DATW_reg(31 downto 16); end if; -- usr evt 1 width
if xuser_TMEM_WE_reg(5 downto 4) = "11" then evr_puls_width_cfg_s(3) <= xuser_TMEM_DATW_reg(47 downto 32); end if; -- usr evt 2 width
if xuser_TMEM_WE_reg(7 downto 6) = "11" then evr_puls_width_cfg_s(4) <= xuser_TMEM_DATW_reg(63 downto 48); end if; -- usr evt 3 width
end if;
-----------------------------------------------------------------------------------------------------------------
if xuser_TMEM_ADD_reg(6 downto 3) = X"C" then --ByteAddr 060
if xuser_TMEM_WE_reg(1 downto 0) = "11" then evr_puls_delay_cfg_s(0) <= xuser_TMEM_DATW_reg(15 downto 0); end if; -- sos evt del
if xuser_TMEM_WE_reg(3 downto 2) = "11" then evr_puls_width_cfg_s(0) <= xuser_TMEM_DATW_reg(31 downto 16); end if; -- sos evt width
end if;
end if; end if;
end if; end if;
end process; end process;
@@ -294,110 +246,15 @@ begin
-- -------------------------------------------------------------------------- -- --------------------------------------------------------------------------
-- Port mapping -- Port mapping
-- -------------------------------------------------------------------------- -- --------------------------------------------------------------------------
mem_clk_o <= xuser_CLK; mem_clk_o <= xuser_CLK;
mem_addr_o <= std_logic_vector(unsigned(xuser_TMEM_ADD) - unsigned(MEM_ADDR_START)); mem_addr_o <= std_logic_vector(unsigned(xuser_TMEM_ADD) - unsigned(MEM_ADDR_START));
--event recorder had to be also added to cdc evr_params_o <= (event_numbers, event_enable, cs_min_cnt, cs_min_time);
evr_evt_rec_control_o <= (er_event_number, er_event_enable, er_data_ack(3), er_error_ack(3)); evr_evt_rec_control_o <= (er_event_number, er_event_enable, er_data_ack(3), er_error_ack(3));
mgt_reset_o <= mgt_reset; mgt_reset_o <= mgt_reset;
-- --------------------------------------------------------------------------
-- add CDC output
-- --------------------------------------------------------------------------
block_cdc_evr_puls_param : block
signal input_s, output_s : std_logic_vector(10 * 16 - 1 downto 0);
begin
-- ------------------------------------------------------------------------
-- Assemble Input
-- ------------------------------------------------------------------------
--** pulse delay parameters **
input_s(15 downto 0) <= evr_puls_delay_cfg_s(0);
input_s(31 downto 16) <= evr_puls_delay_cfg_s(1);
input_s(47 downto 32) <= evr_puls_delay_cfg_s(2);
input_s(63 downto 48) <= evr_puls_delay_cfg_s(3);
input_s(79 downto 64) <= evr_puls_delay_cfg_s(4);
--** pulse width parameters **
input_s(95 downto 80) <= evr_puls_width_cfg_s(0);
input_s(111 downto 96) <= evr_puls_width_cfg_s(1);
input_s(127 downto 112) <= evr_puls_width_cfg_s(2);
input_s(143 downto 128) <= evr_puls_width_cfg_s(3);
input_s(159 downto 144) <= evr_puls_width_cfg_s(4);
-- Instance
inst_cdc_fast_stat : entity work.psi_common_status_cc
generic map(DataWidth_g => input_s'length)
port map(ClkA => xuser_CLK,
RstInA => xuser_RESET,
DataA => input_s,
ClkB => evr_clk_i,
RstInB => evr_rst_i,
DataB => output_s);
-- ------------------------------------------------------------------------
-- Disassemble Output
-- ------------------------------------------------------------------------
--** pulse delay parameters **
evr_pulse_delay_o(0) <= output_s(15 downto 0);
evr_pulse_delay_o(1) <= output_s(31 downto 16);
evr_pulse_delay_o(2) <= output_s(47 downto 32);
evr_pulse_delay_o(3) <= output_s(63 downto 48);
evr_pulse_delay_o(4) <= output_s(79 downto 64);
--** pulse width parameters **
evr_pulse_width_o(0) <= output_s(95 downto 80);
evr_pulse_width_o(1) <= output_s(111 downto 96);
evr_pulse_width_o(2) <= output_s(127 downto 112);
evr_pulse_width_o(3) <= output_s(143 downto 128);
evr_pulse_width_o(4) <= output_s(159 downto 144);
end block;
block_cdc_evr_code_param : block
signal input_s, output_s : std_logic_vector(108 downto 0);
begin
-- ------------------------------------------------------------------------
-- Assemble Input
-- ------------------------------------------------------------------------
--** event numbers **
input_s( 7 downto 0) <= event_numbers(0);
input_s(15 downto 8) <= event_numbers(1);
input_s(23 downto 16) <= event_numbers(2);
input_s(31 downto 24) <= event_numbers(3);
--** event pulse enable **
input_s(35 downto 32) <= event_enable;
--** time counter **
input_s(67 downto 36) <= cs_min_time;
input_s(99 downto 68) <= cs_min_cnt;
--** latency counter **
input_s(100) <= lat_counter_arm;
input_s(108 downto 101) <= lat_event_nr;
-- Instance
inst_cdc_fast_stat : entity work.psi_common_status_cc
generic map(DataWidth_g => input_s'length)
port map(ClkA => xuser_CLK,
RstInA => xuser_RESET,
RstOutA => open,
DataA => input_s,
ClkB => evr_clk_i,
RstInB => evr_rst_i,
RstOutB => open,
DataB => output_s);
-- ------------------------------------------------------------------------
-- Disassemble Output
-- ------------------------------------------------------------------------
--** event numbers **
evr_params_o.event_numbers(0) <= output_s( 7 downto 0) ;
evr_params_o.event_numbers(1) <= output_s(15 downto 8) ;
evr_params_o.event_numbers(2) <= output_s(23 downto 16);
evr_params_o.event_numbers(3) <= output_s(31 downto 24);
--** event pulse enable **
evr_params_o.event_enable <= output_s(35 downto 32);
--** time counter **
evr_params_o.cs_min_time <= output_s(67 downto 36);
evr_params_o.cs_min_cnt <= output_s(99 downto 68);
--** latency counter **
evr_latency_measure_ctrl_o.counter_arm <= output_s(100) ;
evr_latency_measure_ctrl_o.event_nr <= output_s(108 downto 101) ;
end block;
end rtl; end rtl;
-- ---------------------------------------------------------------------------- -- ----------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////// -- ////////////////////////////////////////////////////////////////////////////
-- ---------------------------------------------------------------------------- -- ----------------------------------------------------------------------------

4
hdl/v6vlx_gtxe1_101MHz27_1Gbps0127.vhd
View File

@@ -7,7 +7,7 @@
-- : Patric Bucher, Section DSV -- : Patric Bucher, Section DSV
-- Version : $Revision: 1.1 $ -- Version : $Revision: 1.1 $
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Copyright<EFBFBD> PSI, Section Diagnostic -- Copyright© PSI, Section Diagnostic
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Comment : Virtex-6 GTXE1 primitive configured for HIPA 50.63282 MHz -- Comment : Virtex-6 GTXE1 primitive configured for HIPA 50.63282 MHz
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
@@ -384,7 +384,7 @@ begin
RXPLLLKDET => o_mgt.ctrl.RXPLLLKDET , --RXPLLLKDET_OUT, RXPLLLKDET => o_mgt.ctrl.RXPLLLKDET , --RXPLLLKDET_OUT,
RXPLLLKDETEN => '1', -- RXPLLLKDETEN => '1', --
RXPLLPOWERDOWN => '0', -- RXPLLPOWERDOWN => '0', --
RXPLLREFSELDY => "000", --GREFCLKRX RXPLLREFSELDY => "000", -- GREFCLKRX
RXRATE => "00", -- RXRATE => "00", --
RXRATEDONE => open, -- RXRATEDONE => open, --
RXRESETDONE => o_mgt.ctrl.RXRESETDONE , --RXRESETDONE_OUT, RXRESETDONE => o_mgt.ctrl.RXRESETDONE , --RXRESETDONE_OUT,

10
hdl/v6vlx_gtxe1_wrapper.vhd
View File

@@ -7,13 +7,13 @@
-- : Patric Bucher, Section DSV -- : Patric Bucher, Section DSV
-- Version : $Revision: 1.1 $ -- Version : $Revision: 1.1 $
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Copyright<EFBFBD> PSI, Section Diagnostic -- Copyright© PSI, Section Diagnostic
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Comment : Wrapper vor Virtex-6 GTX ready to use in HIPA and SwissFEL (SFEL) -- Comment : Wrapper vor Virtex-6 GTX ready to use in HIPA and SwissFEL (SFEL)
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.std_logic_unsigned.all;
library unisim; library unisim;
use unisim.vcomponents.all; use unisim.vcomponents.all;
@@ -68,7 +68,7 @@ architecture RTL of v6vlx_gtxe1_wrapper is
signal sl_rx0_slide : std_logic; signal sl_rx0_slide : std_logic;
signal slv_cnt : unsigned(5 downto 0); signal slv_cnt : std_logic_vector(5 downto 0);
-- MMCM -- MMCM
signal mmcm_CLKFB : std_logic; signal mmcm_CLKFB : std_logic;
@@ -137,8 +137,8 @@ begin
o_mgt_status(16) <= sl_rx0_slide; o_mgt_status(16) <= sl_rx0_slide;
o_mgt_status(17) <= sl_gtxe_rx_sync_done; o_mgt_status(17) <= sl_gtxe_rx_sync_done;
o_mgt_status(19 downto 18) <= o_mgt.rx.RXNOTINTABLE(1 downto 0); -- Byte 1 + Byte 0 o_mgt_status(19 downto 18) <= o_mgt.rx.RXNOTINTABLE(1 downto 0); -- Byte 1 + Byte 0
o_mgt_status(23 downto 20) <= o_mgt.rx.RXDISPERR(3 downto 0); -- Byte 1 + Byte 0 o_mgt_status(21 downto 20) <= o_mgt.rx.RXDISPERR(1 downto 0); -- Byte 1 + Byte 0
o_mgt_status(31 downto 24) <= B"0000_0000"; -- undefined o_mgt_status(31 downto 22) <= B"00_0000_0000"; -- undefined
-- GTXE RX IF --------------------------------------------------------------------- -- GTXE RX IF ---------------------------------------------------------------------

22
sim/.gitignore vendored
View File

@@ -1,22 +0,0 @@
# ignore ModelSim generated files and directories (temp files and so on)
[_@]*
*.txt
*.mti
*.dat
*.dbs
*.psm
*.bak
*.cmp
*.jpg
*.html
*.bsf
wlf*
*.wlf
*.vstf
*.ucdb
cov*/
Transcript*
transcript*
sc_dpiheader.h
vsim.dbg

2
sim/ci.do
View File

@@ -1,2 +1,2 @@
source run.tcl source run.tcl
quit #quit

77
sim/config.tcl
View File

@@ -1,43 +1,13 @@
#Import psi::sim library #Import psi::sim library
namespace import psi::sim::* namespace import psi::sim::*
#Set library
add_library evr320
#suppress messages #suppress messages
compile_suppress 135,1236 compile_suppress 135,1236
run_suppress 8684,3479,3813,8009,3812 run_suppress 8684,3479,3813,8009,3812
#Set library path relative to this config file
variable fileLoc [file normalize [file dirname [info script]]]
variable LibPath $fileLoc/../../../..
# tosca2_glb_pkg dependency
add_library tosca2
add_sources $LibPath/BoardSupport/IFC1210/tosca2/hdl/top_ip/src {
tosca2_glb_pkg.vhd \
} -version 2002
add_sources $LibPath/BoardSupport/IFC1210/tosca2/testbench/utilities {
ifc1210_simu_mapping_xuser_pkg.vhd \
ifc1210_simu_procedures_pkg.vhd \
}
#Set library
add_library evr320
# psi_common dependency:
add_sources $LibPath/Firmware/VHDL/psi_common/hdl {
psi_common_array_pkg.vhd \
psi_common_math_pkg.vhd \
psi_common_logic_pkg.vhd \
psi_common_sdp_ram.vhd \
psi_common_pulse_cc.vhd \
psi_common_async_fifo.vhd \
psi_common_clk_meas.vhd \
psi_common_pulse_shaper_cfg.vhd \
psi_common_delay_cfg.vhd \
psi_common_simple_cc.vhd \
psi_common_status_cc.vhd \
} -tag psi_common
# EVR320 Decoder # EVR320 Decoder
add_sources $LibPath/Firmware/VHDL/evr320/hdl { add_sources $LibPath/Firmware/VHDL/evr320/hdl {
@@ -49,6 +19,14 @@ add_sources $LibPath/Firmware/VHDL/evr320/hdl {
evr320_data_filter.vhd \ evr320_data_filter.vhd \
} -tag evr320_decoder } -tag evr320_decoder
# EVR320 Decoder Testbench
add_sources $LibPath/Firmware/VHDL/evr320/tb {
evr320_decoder_tb.vhd \
} -tag evr320_decoder_tb
# setup tb runs
create_tb_run "evr320_decoder_tb"
add_tb_run
# IFC1210 Bindings # IFC1210 Bindings
add_sources $LibPath/Firmware/VHDL/evr320/hdl { add_sources $LibPath/Firmware/VHDL/evr320/hdl {
@@ -61,24 +39,21 @@ add_sources $LibPath/Firmware/VHDL/evr320/hdl {
evr320_ifc1210_wrapper.vhd \ evr320_ifc1210_wrapper.vhd \
} -tag evr320_ifc1210 } -tag evr320_ifc1210
# EVR320 Decoder Testbench # psi_common dependency:
add_sources $LibPath/Firmware/VHDL/evr320/tb { add_sources $LibPath/Firmware/VHDL/psi_common/hdl {
evr320_decoder_tb.vhd \ psi_common_array_pkg.vhd \
evr320_ifc1210_wrapper_tb.vhd \ psi_common_math_pkg.vhd \
} -tag evr320_tb psi_common_logic_pkg.vhd \
psi_common_sdp_ram.vhd \
psi_common_pulse_cc.vhd \
psi_common_async_fifo.vhd \
psi_common_clk_meas.vhd \
} -tag psi_common
# EVR320 IFC1210 Wrapper Testbench # tosca2_glb_pkg dependency
#add_sources $LibPath/Firmware/VHDL/evr320/tb { add_library tosca2
# evr320_ifc1210_wrapper_tb.vhd \
#} -tag evr320_ifc1210_wrapper_tb
# setup tb runs add_sources $LibPath/BoardSupport/IFC1210/tosca2/hdl/top_ip/src {
create_tb_run "evr320_decoder_tb" tosca2_glb_pkg.vhd \
tb_run_add_arguments \ }
"-gg_EVENT_NR_0=16#0F# -gg_EVENT_NR_1=0 -gg_EVENT_NR_2=0 -gg_EVENT_NR_3=0 -gg_EVENT_NR_SOS=0" \
"-gg_EVENT_NR_0=2 -gg_EVENT_NR_1=4 -gg_EVENT_NR_2=0 -gg_EVENT_NR_3=3 -gg_EVENT_NR_SOS=0" \
"-gg_EVENT_NR_0=0 -gg_EVENT_NR_1=0 -gg_EVENT_NR_2=5 -gg_EVENT_NR_3=0 -gg_EVENT_NR_SOS=6"
add_tb_run
create_tb_run "evr320_ifc1210_wrapper_tb"
add_tb_run

49
sim/run.tcl
View File

@@ -1,12 +1,42 @@
# Library Path # Library Path
set LibPath "../../../.." set LibPath "../../../.."
# Configure UVVM -> until compile when not existing # Compile UVVM library (if necessary):
set uvvm_path $LibPath/Firmware/VHDL/UVVM/uvvm_util # -------------------------------------------------------
if {[file isdirectory uvvm_util]} { set uvvm_lib $LibPath/Firmware/VHDL/UVVM/uvvm_util/sim/uvvm_util/
puts "UVVM directory evr320/sim/uvvm_util is present --> not compiled again!" # compile lib if folder not exist:
#if {![file isdirectory $uvvm_lib]} {
# copy adapted pkg:
# comment the line after because adaptation pkg is in uvvm_util lib already... stef.b
#file copy -force ../tb/adaptations_pkg.vhd $LibPath/Firmware/VHDL/UVVM/uvvm_util/src/
set last_dir [pwd]
cd $LibPath/Firmware/VHDL/UVVM/uvvm_util/script/
do compile_src.do
cd $last_dir
#}
vmap uvvm_util $LibPath/Firmware/VHDL/UVVM/uvvm_util/sim/uvvm_util/
# -------------------------------------------------------
# Check if running in jenkins environment
if [info exists env(JENKINS_HOME)] {
set jenkins 1
} else { } else {
do $uvvm_path/script/compile_src.do $uvvm_path set jenkins 0
}
# map different libraries when running on jenkins machine:
if {$jenkins == 1} {
vmap unisim /home/modelsim/xilinx_libs/13.4/unisim
vmap xilinxcorelib /home/modelsim/xilinx_libs/13.4/xilinxcorelib
vmap secureip /home/modelsim/xilinx_libs/13.4/secureip
} else {
#vmap unisim C:/Xilinx/13.4/ISE_DS/ISE/vhdl/mti_se/10.3c/nt64/unisim
vmap unisim C:/Xilinx/13.4/ISE_DS/ISE/vhdl/mti_se/10.6/nt/unisim
#vmap xilinxcorelib C:/Xilinx/13.4/ISE_DS/ISE/vhdl/mti_se/10.3c/nt64/xilinxcorelib
vmap xilinxcorelib C:/Xilinx/13.4/ISE_DS/ISE/vhdl/mti_se/10.6/nt/xilinxcorelib
#vmap secureip C:/Xilinx/13.4/ISE_DS/ISE/vhdl/mti_se/10.3c/nt64/unisim
vmap secureip C:/Xilinx/13.4/ISE_DS/ISE/vhdl/mti_se/10.6/nt/unisim
} }
#Load dependencies TODO #Load dependencies TODO
@@ -27,14 +57,11 @@ puts "-- Compile"
puts "------------------------------" puts "------------------------------"
clean_libraries -all clean_libraries -all
compile_files -tag psi_common compile_files -tag psi_common
compile_files -lib tosca2
compile_files -tag evr320_decoder compile_files -tag evr320_decoder
compile_files -tag evr320_decoder_tb
compile_files -lib tosca2
compile_files -tag evr320_ifc1210 compile_files -tag evr320_ifc1210
#compile_files -tag evr320_decoder_tb
compile_files -tag evr320_tb
#compile_files -lib evr320 #compile_files -lib evr320
#run_tb -all run_tb -all
run_tb -name evr320_decoder_tb
run_tb -name evr320_ifc1210_wrapper_tb
run_check_errors "###ERROR###" run_check_errors "###ERROR###"

290
tb/adaptations_pkg.vhd
View File

@@ -1,290 +0,0 @@
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.types_pkg.all;
package adaptations_pkg is
constant C_ALERT_FILE_NAME : string := "_Alert.txt";
constant C_LOG_FILE_NAME : string := "_Log.txt";
constant C_SHOW_UVVM_UTILITY_LIBRARY_INFO : boolean := false; -- Set this to false when you no longer need the initial info
constant C_SHOW_UVVM_UTILITY_LIBRARY_RELEASE_INFO : boolean := false; -- Set this to false when you no longer need the release info
-------------------------------------------------------------------------------
-- Log format
-------------------------------------------------------------------------------
--UVVM: [<ID>] <time> <Scope> Msg
--PPPPPPPPIIIIII TTTTTTTT SSSSSSSSSSSSSS MMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMM
constant C_LOG_PREFIX : string := "UVVM: "; -- Note: ': ' is recommended as final characters
constant C_LOG_PREFIX_WIDTH : natural := C_LOG_PREFIX'length;
constant C_LOG_MSG_ID_WIDTH : natural := 18;
constant C_LOG_TIME_WIDTH : natural := 14; -- 3 chars used for unit eg. " ns"
constant C_LOG_TIME_BASE : time := ns; -- Unit in which time is shown in log (ns | ps)
constant C_LOG_TIME_DECIMALS : natural := 1; -- Decimals to show for given C_LOG_TIME_BASE
constant C_LOG_SCOPE_WIDTH : natural := 16;
constant C_LOG_LINE_WIDTH : natural := 200;
constant C_LOG_INFO_WIDTH : natural := C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH;
constant C_USE_BACKSLASH_N_AS_LF : boolean := true; -- If true interprets '\n' as Line feed
constant C_USE_BACKSLASH_R_AS_LF : boolean := true; -- If true, inserts an empty line if '\r'
-- is the first character of the string.
-- All others '\r' will be printed as is.
constant C_SINGLE_LINE_ALERT : boolean := false; -- If true prints alerts on a single line.
constant C_SINGLE_LINE_LOG : boolean := false; -- If true prints log messages on a single line.
constant C_TB_SCOPE_DEFAULT : string := "TB_SCOPE"; -- Default scope in test sequencer
constant C_LOG_TIME_TRUNC_WARNING : boolean := false; -- Yields a single TB_WARNING if time stamp truncated. Otherwise none
constant C_SHOW_LOG_ID : boolean := true; -- This constant has replaced the global_show_log_id
constant C_SHOW_LOG_SCOPE : boolean := true; -- This constant has replaced the global_show_log_scope
constant C_WARNING_ON_LOG_ALERT_FILE_RUNTIME_RENAME : boolean := false;
constant C_USE_STD_STOP_ON_ALERT_STOP_LIMIT : boolean := true; -- true: break using std.env.stop, false: break using failure
shared variable shared_default_log_destination : t_log_destination := CONSOLE_AND_LOG;
-------------------------------------------------------------------------------
-- Verbosity control
-- NOTE: Do not enter new IDs without proper evaluation:
-- 1. Is it - or could it be covered by an existing ID
-- 2. Could it be combined with other needs for a more general new ID
-- Feel free to suggest new ID for future versions of UVVM Utility Library (support@bitvis.no)
-------------------------------------------------------------------------------
type t_msg_id is (
-- Bitvis utility methods
NO_ID, -- Used as default prior to setting actual ID when transfering ID as a field in a record
ID_UTIL_BURIED, -- Used for buried log messages where msg and scope cannot be modified from outside
ID_BITVIS_DEBUG, -- Bitvis internal ID used for UVVM debugging
ID_UTIL_SETUP, -- Used for Utility setup
ID_LOG_MSG_CTRL, -- Used inside Utility library only - when enabling/disabling msg IDs.
ID_ALERT_CTRL, -- Used inside Utility library only - when setting IGNORE or REGARD on various alerts.
ID_NEVER, -- Used for avoiding log entry. Cannot be enabled.
ID_FINISH_OR_STOP, -- Used when terminating the complete simulation - independent of why
ID_CLOCK_GEN, -- Used for logging when clock generators are enabled or disabled
ID_GEN_PULSE, -- Used for logging when a gen_pulse procedure starts pulsing a signal
ID_BLOCKING, -- Used for logging when using synchronisation flags
-- General
ID_POS_ACK, -- To write a positive acknowledge on a check
-- Directly inside test sequencers
ID_LOG_HDR, -- ONLY allowed in test sequencer, Log section headers
ID_LOG_HDR_LARGE, -- ONLY allowed in test sequencer, Large log section headers
ID_LOG_HDR_XL, -- ONLY allowed in test sequencer, Extra large log section headers
ID_SEQUENCER, -- ONLY allowed in test sequencer, Normal log (not log headers)
ID_SEQUENCER_SUB, -- ONLY allowed in test sequencer, Subprograms defined in sequencer
-- BFMs
ID_BFM, -- Used inside a BFM (to log BFM access)
ID_BFM_WAIT, -- Used inside a BFM to indicate that it is waiting for something (e.g. for ready)
ID_BFM_POLL, -- Used inside a BFM when polling until reading a given value. I.e. to show all reads until expected value found (e.g. for sbi_poll_until())
ID_BFM_POLL_SUMMARY, -- Used inside a BFM when showing the summary of data that has been received while waiting for expected data.
ID_TERMINATE_CMD, -- Typically used inside a loop in a procedure to end the loop (e.g. for sbi_poll_until() or any looped generation of random stimuli
-- Packet related data Ids with three levels of granularity, for differentiating between frames, packets and segments.
-- Segment Ids, finest granularity of packet data
ID_SEGMENT_INITIATE, -- Notify that a packet is about to be transmitted or received
ID_SEGMENT_COMPLETE, -- Notify that a packet has been transmitted or received
ID_SEGMENT_HDR, -- AS ID_SEGMENT_COMPLETE, but also writes header info
ID_SEGMENT_DATA, -- AS ID_SEGMENT_COMPLETE, but also writes packet data (could be huge)
-- Packet Ids, medium granularity of packet data
ID_PACKET_INITIATE, -- Notify that a packet is about to be transmitted or received
ID_PACKET_COMPLETE, -- Notify that a packet has been transmitted or received
ID_PACKET_HDR, -- AS ID_PACKET_COMPLETED, but also writes header info
ID_PACKET_DATA, -- AS ID_PACKET_COMPLETED, but also writes packet data (could be huge)
-- Frame Ids, roughest granularity of packet data
ID_FRAME_INITIATE, -- Notify that a packet is about to be transmitted or received
ID_FRAME_COMPLETE, -- Notify that a packet has been transmitted or received
ID_FRAME_HDR, -- AS ID_FRAME_COMPLETE, but also writes header info
ID_FRAME_DATA, -- AS ID_FRAME_COMPLETE, but also writes packet data (could be huge)
-- OSVVM Ids
ID_COVERAGE_MAKEBIN, -- Log messages from MakeBin (IllegalBin/GenBin/IgnoreBin)
ID_COVERAGE_ADDBIN, -- Log messages from AddBin/AddCross
ID_COVERAGE_ICOVER, -- ICover logging, NB: Very low level debugging. Can result in large amount of data.
ID_COVERAGE_CONFIG, -- Logging of configuration in the coverage package
ID_COVERAGE_SUMMARY, -- Report logging : Summary of coverage, with both covered bins and holes
ID_COVERAGE_HOLES, -- Report logging : Holes only
-- Distributed command systems
ID_UVVM_SEND_CMD,
ID_UVVM_CMD_ACK,
ID_UVVM_CMD_RESULT,
ID_CMD_INTERPRETER, -- Message from VVC interpreter about correctly received and queued/issued command
ID_CMD_INTERPRETER_WAIT, -- Message from VVC interpreter that it is actively waiting for a command
ID_IMMEDIATE_CMD, -- Message from VVC interpreter that an IMMEDIATE command has been executed
ID_IMMEDIATE_CMD_WAIT, -- Message from VVC interpreter that an IMMEDIATE command is waiting for command to complete
ID_CMD_EXECUTOR, -- Message from VVC executor about correctly received command - prior to actual execution
ID_CMD_EXECUTOR_WAIT, -- Message from VVC executor that it is actively waiting for a command
ID_INSERTED_DELAY, -- Message from VVC executor that it is waiting a given delay
-- Distributed data
ID_UVVM_DATA_QUEUE, -- Information about UVVM data FIFO/stack (initialization, put, get, etc)
-- VVC system
ID_CONSTRUCTOR, -- Constructor message from VVCs (or other components/process when needed)
ID_CONSTRUCTOR_SUB, -- Constructor message for lower level constructor messages (like Queue-information and other limitations)
-- SB package
ID_DATA,
ID_CTRL,
-- Special purpose - Not really IDs
ALL_MESSAGES -- Applies to ALL message ID apart from ID_NEVER
);
type t_msg_id_panel is array (t_msg_id'left to t_msg_id'right) of t_enabled;
constant C_TB_MSG_ID_DEFAULT : t_msg_id := ID_SEQUENCER; -- msg ID used when calling the log method without any msg ID switch.
-- Default message Id panel to be used for all message Id panels, except:
-- - VVC message Id panels, see constant C_VVC_MSG_ID_PANEL_DEFAULT
constant C_MSG_ID_PANEL_DEFAULT : t_msg_id_panel := (
ID_NEVER => DISABLED,
ID_UTIL_BURIED => DISABLED,
ID_BITVIS_DEBUG => DISABLED,
ID_COVERAGE_MAKEBIN => DISABLED,
ID_COVERAGE_ADDBIN => DISABLED,
ID_COVERAGE_ICOVER => DISABLED,
others => ENABLED
);
-- If false, OSVVM uses the default message id panel. If true, it uses a separate message id panel.
constant C_USE_LOCAL_OSVVM_MSG_ID_PANELS : boolean := TRUE;
type t_msg_id_indent is array (t_msg_id'left to t_msg_id'right) of string(1 to 4);
constant C_MSG_ID_INDENT : t_msg_id_indent := (
ID_IMMEDIATE_CMD_WAIT => " ..",
ID_CMD_INTERPRETER => " " & NUL & NUL,
ID_CMD_INTERPRETER_WAIT => " ..",
ID_CMD_EXECUTOR => " " & NUL & NUL,
ID_CMD_EXECUTOR_WAIT => " ..",
ID_UVVM_SEND_CMD => "->" & NUL & NUL,
ID_UVVM_CMD_ACK => " ",
others => "" & NUL & NUL & NUL & NUL
);
constant C_MSG_DELIMITER : character := ''';
-------------------------------------------------------------------------
-- Alert counters
-------------------------------------------------------------------------
-- Default values. These can be overwritten in each sequencer by using
-- set_alert_attention or set_alert_stop_limit (see quick ref).
constant C_DEFAULT_ALERT_ATTENTION : t_alert_attention := (others => REGARD);
-- 0 = Never stop
constant C_DEFAULT_STOP_LIMIT : t_alert_counters := (note to manual_check => 0,
others => 1);
-------------------------------------------------------------------------
-- Hierarchical alerts
-------------------------------------------------------------------------
constant C_ENABLE_HIERARCHICAL_ALERTS : boolean := false;
constant C_BASE_HIERARCHY_LEVEL : string(1 to 5) := "Total";
constant C_EMPTY_NODE : t_hierarchy_node := (" ",
(others => (others => 0)),
(others => 0),
(others => true));
-------------------------------------------------------------------------
-- Deprecate
-------------------------------------------------------------------------
-- These values are used to indicate outdated sub-programs
constant C_DEPRECATE_SETTING : t_deprecate_setting := DEPRECATE_ONCE;
shared variable deprecated_subprogram_list : t_deprecate_list := (others=>(others => ' '));
------------------------------------------------------------------------
-- UVVM VVC Framework adaptations
------------------------------------------------------------------------
constant C_SCOPE : string := C_TB_SCOPE_DEFAULT & "(uvvm)";
signal global_show_msg_for_uvvm_cmd : boolean := true;
constant C_CMD_QUEUE_COUNT_MAX : natural := 20; -- (VVC Command queue) May be overwritten for dedicated VVC
constant C_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING;
constant C_CMD_QUEUE_COUNT_THRESHOLD : natural := 18;
constant C_RESULT_QUEUE_COUNT_MAX : natural := 20; -- (VVC Result queue) May be overwritten for dedicated VVC
constant C_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING;
constant C_RESULT_QUEUE_COUNT_THRESHOLD : natural := 18;
constant C_MAX_VVC_INSTANCE_NUM : natural := 20;
constant C_MAX_NUM_SEQUENCERS : natural := 10; -- Max number of sequencers
-- Maximum allowed length of VVC names
constant C_MAX_VVC_NAME_LENGTH : positive := 20;
-- Minimum width of vvc name and channel displayed in scope.
-- These combined + the length of instance + 2 (commas), cannot exceed C_LOG_SCOPE_WIDTH.
constant C_MINIMUM_CHANNEL_SCOPE_WIDTH : natural := 10;
constant C_MINIMUM_VVC_NAME_SCOPE_WIDTH : natural := 10;
constant C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER : natural := 2048;
constant C_NUMBER_OF_DATA_BUFFERS : natural := 10;
-- Default message Id panel intended for use in the VVCs
constant C_VVC_MSG_ID_PANEL_DEFAULT : t_msg_id_panel := (
ID_NEVER => DISABLED,
ID_UTIL_BURIED => DISABLED,
others => ENABLED
);
type t_data_source is ( -- May add more types of random ++ later
NA,
FROM_BUFFER,
RANDOM,
RANDOM_TO_BUFFER
);
type t_error_injection is ( -- May add more controlled error injection later
NA,
RANDOM_BIT_ERROR,
RANDOM_DATA_ERROR,
RANDOM_ADDRESS_ERROR
);
constant C_CMD_IDX_PREFIX : string := " [";
constant C_CMD_IDX_SUFFIX : string := "]";
type t_channel is ( -- NOTE: Add more types of channels when needed for a VVC
NA, -- When channel is not relevant
ALL_CHANNELS, -- When command shall be received by all channels
RX,
TX);
constant C_VVCT_ALL_INSTANCES, ALL_INSTANCES : integer := -2;
constant ALL_ENABLED_INSTANCES : integer := -3;
constant C_NUM_SEMAPHORE_LOCK_TRIES : natural := 500;
------------------------------------------------------------------------
-- Scoreboard adaptations
------------------------------------------------------------------------
constant C_MAX_QUEUE_INSTANCE_NUM : positive := 100; -- Maximum number of instances
constant C_SB_TAG_WIDTH : positive := 128; -- Number of characters in SB tag
constant C_SB_SOURCE_WIDTH : positive := 128; -- Number of characters in SB source element
constant C_SB_SLV_WIDTH : positive := 8; -- Width of the SLV in the predefined SLV SB
-- Default message Id panel intended for use in SB
constant C_SB_MSG_ID_PANEL_DEFAULT : t_msg_id_panel := (
ID_CTRL => ENABLED,
ID_DATA => DISABLED,
others => DISABLED
);
end package adaptations_pkg;
package body adaptations_pkg is
end package body adaptations_pkg;

745
tb/evr320_decoder_tb.vhd
View File

@@ -29,407 +29,319 @@ library work;
use work.evr320_pkg.all; use work.evr320_pkg.all;
entity evr320_decoder_tb is entity evr320_decoder_tb is
generic (
g_EVENT_NR_0 : integer range 0 to 255 := 16#00#;
g_EVENT_NR_1 : integer range 0 to 255 := 16#04#;
g_EVENT_NR_2 : integer range 0 to 255 := 16#00#;
g_EVENT_NR_3 : integer range 0 to 255 := 16#00#;
g_EVENT_NR_SOS : integer range 0 to 255 := 16#20#
);
end entity; end entity;
architecture testbench of evr320_decoder_tb is architecture testbench of evr320_decoder_tb is
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
-- System -- System
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
constant C_RXUSRCLK_CYCLE : time:= 7 ns; -- System
constant C_USRCLK_CYCLE : time:= 8 ns; constant C_RXUSRCLK_CYCLE : time:= 7 ns;
constant C_EVT_NR : integer := 4; constant C_USRCLK_CYCLE : time:= 8 ns;
constant C_MEM_DATA_WIDTH : integer := 32; -- 32|64 (64 bit used for tosca2 on ifc1210) ---------------------------------------------------------------------------
constant C_EVENT_RECORDER : boolean := true; -- MGT stream
constant C_EVENT_REC_FLAGS : std_logic_vector(11 downto 6) := B"1101_11"; ---------------------------------------------------------------------------
type mgt_stream_sample_type is record
data : std_logic_vector(7 downto 0);
data_k : std_logic_vector(0 downto 0);
event : std_logic_vector(7 downto 0);
event_k : std_logic_vector(0 downto 0);
end record mgt_stream_sample_type;
type mgt_stream_type is array (natural range <>) of mgt_stream_sample_type;
signal mgt_stream_index : integer range 0 to 511 := 0;
signal mgt_stream : mgt_stream_type(511 downto 0) := (others=>(others=>(others=>'0')));
-----------------------------------------------------------------------------
-- Timing decoder interface
-----------------------------------------------------------------------------
-- Link status
signal rxlos : std_logic := '0';
-- Clock
signal rxusrclk : std_logic := '0';
-- Data
signal rxdata : std_logic_vector(15 downto 0) := (others => '0');
-- Status 8B/10B decoder
signal rxcharisk : std_logic_vector( 1 downto 0) := (others => '0');
signal usr_clk : std_logic := '0';
signal evr_params : typ_evr320_params;
signal mem_addr : std_logic_vector(11 downto 0) := (others => '0');
signal mem_data : std_logic_vector(31 downto 0) := (others => '0');
-- Decoder stream:
type dec_stream_type is record
data : std_logic_vector(7 downto 0);
addr : std_logic_vector(10 downto 0);
end record dec_stream_type;
type dec_stream_check_arr is array (natural range <>) of dec_stream_type;
signal dec_stream_data : std_logic_vector(7 downto 0) := (others => '0');
signal dec_stream_addr : std_logic_vector(10 downto 0) := (others => '0');
signal dec_stream_valid : std_logic;
signal dec_stream_check : dec_stream_check_arr(0 to 2047);
signal dec_stream_recv_bytes : integer range 0 to 2047;
type segment_data_arr is array (natural range <>) of std_logic_vector(7 downto 0);
signal segment_addr : std_logic_vector(7 downto 0);
signal segment_data : segment_data_arr(0 to 2047);
signal segment_length : natural range 0 to 2047;
--------------------------------------------------------------------------- signal usr_events : std_logic_vector( 3 downto 0) := (others => '0');
-- MGT stream
--------------------------------------------------------------------------- constant FILTER_ADDRESS : std_logic_vector(11 downto 0) := x"028";
type mgt_stream_sample_type is record constant FILTER_NUM_BYTES : integer := 8;
data : std_logic_vector(7 downto 0); constant STIMULI_RUNS : integer := 2;
data_k : std_logic_vector(0 downto 0);
event : std_logic_vector(7 downto 0); signal received_events : integer := 0;
event_k : std_logic_vector(0 downto 0); signal expect_num_events : integer := 0;
end record mgt_stream_sample_type; signal filter_data, filter_data_check : std_logic_vector(63 downto 0) := (others => '0');
signal filter_valid : std_logic := '0';
type mgt_stream_type is array (natural range <>) of mgt_stream_sample_type;
signal mgt_stream_index : integer range 0 to 511 := 0;
signal mgt_stream : mgt_stream_type(511 downto 0) := (others=>(others=>(others=>'0')));
-----------------------------------------------------------------------------
-- Timing decoder interface
-----------------------------------------------------------------------------
-- Link status
signal rxlos : std_logic := '0';
-- Clock
signal rxusrclk : std_logic := '0';
-- Data
signal rxdata : std_logic_vector(15 downto 0) := (others => '0');
-- Status 8B/10B decoder
signal rxcharisk : std_logic_vector( 1 downto 0) := (others => '0');
signal usr_clk : std_logic := '0';
signal evr_params : typ_evr320_params;
signal mem_addr : std_logic_vector(11 downto 0) := (others => '0');
signal mem_data : std_logic_vector(31 downto 0) := (others => '0');
-- Decoder stream
type dec_stream_type is record
data : std_logic_vector(7 downto 0);
addr : std_logic_vector(10 downto 0);
end record dec_stream_type;
type dec_stream_check_arr is array (natural range <>) of dec_stream_type;
signal dec_stream_data : std_logic_vector(7 downto 0) := (others => '0');
signal dec_stream_addr : std_logic_vector(10 downto 0) := (others => '0');
signal dec_stream_valid : std_logic;
signal dec_stream_check : dec_stream_check_arr(0 to 2047);
signal dec_stream_recv_bytes : integer range 0 to 2047;
type segment_data_arr is array (natural range <>) of std_logic_vector(7 downto 0);
signal segment_addr : std_logic_vector(7 downto 0);
signal segment_data : segment_data_arr(0 to 2047);
signal segment_length : natural range 0 to 2047;
constant FILTER_ADDRESS : std_logic_vector(11 downto 0) := x"028";
constant FILTER_NUM_BYTES : integer := 8;
constant STIMULI_RUNS : integer := 2;
signal filter_data, filter_data_check : std_logic_vector(63 downto 0) := (others => '0');
signal filter_valid : std_logic := '0';
-- Events
signal usr_events : std_logic_vector( 3 downto 0) := (others => '0');
signal sos_event : std_logic := '0';
type typ_arrint is array (natural range <>) of integer;
signal received_events : typ_arrint(0 to C_EVT_NR-1) := (others => 0);
signal expect_events : typ_arrint(0 to C_EVT_NR-1) := (others => 0);
signal expect_events_total : integer := 0;
-- Event Recorder
signal event_recorder_status : typ_evt_rec_status;
signal event_recorder_ctrl : typ_evt_rec_ctrl := c_INIT_EVT_REC_CTRL;
signal check_evt_rec_events : std_logic := '0';
signal all_expected_events : std_logic_vector(255 downto 0) := (others => '0');
signal expected_user_events : integer range 0 to 255 := 0;
begin begin
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- Timing decoder -- Timing decoder
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
evr320_decoder_inst: entity work.evr320_decoder evr320_decoder_inst: entity work.evr320_decoder
generic map port map
( (
EVENT_RECORDER => C_EVENT_RECORDER, --------------------------------------------------------------------------
MEM_DATA_WIDTH => C_MEM_DATA_WIDTH -- Debug interface
) --------------------------------------------------------------------------
port map debug_clk => open,
( debug => open,
-------------------------------------------------------------------------- --------------------------------------------------------------------------
-- Debug interface -- GTX parallel interface
-------------------------------------------------------------------------- --------------------------------------------------------------------------
debug_clk => open, i_mgt_rst => rxlos,
debug => open, i_mgt_rx_clk => rxusrclk,
-------------------------------------------------------------------------- i_mgt_rx_data => rxdata,
-- GTX parallel interface i_mgt_rx_charisk => rxcharisk,
-------------------------------------------------------------------------- --------------------------------------------------------------------------
i_mgt_rst => rxlos, -- User interface CPU clock
i_mgt_rx_clk => rxusrclk, --------------------------------------------------------------------------
i_mgt_rx_data => rxdata, i_usr_clk => usr_clk,
i_mgt_rx_charisk => rxcharisk, i_evr_params => evr_params,
-------------------------------------------------------------------------- o_event_recorder_stat => open,
-- User interface CPU clock i_event_recorder_ctrl => c_INIT_EVT_REC_CTRL,
-------------------------------------------------------------------------- i_mem_addr => mem_addr,
i_usr_clk => usr_clk, o_mem_data => mem_data,
i_evr_params => evr_params, --------------------------------------------------------------------------
o_event_recorder_stat => event_recorder_status, -- User stream interface User clock
i_event_recorder_ctrl => event_recorder_ctrl, --------------------------------------------------------------------------
i_mem_addr => mem_addr, i_stream_clk => usr_clk,
o_mem_data => mem_data, o_stream_data => dec_stream_data,
-------------------------------------------------------------------------- o_stream_addr => dec_stream_addr,
-- User stream interface User clock o_stream_valid => dec_stream_valid,
-------------------------------------------------------------------------- --------------------------------------------------------------------------
i_stream_clk => usr_clk, -- User interface MGT clock
o_stream_data => dec_stream_data, --------------------------------------------------------------------------
o_stream_addr => dec_stream_addr, o_usr_events => usr_events,
o_stream_valid => dec_stream_valid, o_usr_events_ext => open,
-------------------------------------------------------------------------- o_sos_event => open
-- User interface MGT clock );
--------------------------------------------------------------------------
o_usr_events => usr_events,
o_usr_events_ext => open,
o_sos_event => sos_event
);
evr320_data_filter_inst: entity work.evr320_data_filter evr320_data_filter_inst: entity work.evr320_data_filter
generic map ( generic map (
SWAP => false ADDRESS => FILTER_ADDRESS,
NUM_BYTES => 8 NUM_BYTES => 8
) )
port map ( port map (
i_stream_clk => usr_clk, i_stream_clk => usr_clk,
i_stream_data => dec_stream_data, i_stream_data => dec_stream_data,
i_stream_addr => dec_stream_addr, i_stream_addr => dec_stream_addr,
i_stream_valid => dec_stream_valid, i_stream_valid => dec_stream_valid,
i_address => FILTER_ADDRESS, o_data => filter_data,
o_data => filter_data, o_valid => filter_valid
o_valid => filter_valid );
); -----------------------------------------------------------------------------
-- MGT / User clock
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- MGT / User clock clock_generator(rxusrclk, C_RXUSRCLK_CYCLE);
----------------------------------------------------------------------------- clock_generator(usr_clk, C_USRCLK_CYCLE);
clock_generator(rxusrclk, C_RXUSRCLK_CYCLE);
clock_generator(usr_clk, C_USRCLK_CYCLE);
-----------------------------------------------------------------------------
-- Decoder reset due to MGT main status
-----------------------------------------------------------------------------
process
begin
rxlos <= '1';
wait for 50 ns;
wait until (falling_edge(rxusrclk));
rxlos <= '0';
wait ;
end process;
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- Read stimuli file -- Decoder reset due to MGT main status
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
file_blk : block process
file file_stimuli : text; begin
type parse_fsm_state is (idle, seg_start, seg_addr, seg_Wait, seg_payload, seg_payload_wait, seg_done); rxlos <= '1';
begin wait for 50 ns;
wait until (falling_edge(rxusrclk));
rxlos <= '0';
wait ;
end process;
---------------------------------------------------------
-- Receive decoder data stream
---------------------------------------------------------
process process
variable file_line : line; variable addr : std_logic_vector(10 downto 0);
variable data, event : std_logic_vector(7 downto 0); variable data : std_logic_vector(7 downto 0);
variable data_k, event_k : std_logic_vector(0 downto 0); variable i : integer := 0;
variable space : character;
variable i : integer;
variable parse_fsm : parse_fsm_state := idle;
variable payload_cnt : integer range 0 to 2047;
variable event_cnt_total : integer := 0;
variable event_cnt_0 : integer := 0;
variable event_cnt_1 : integer := 0;
variable event_cnt_2 : integer := 0;
variable event_cnt_3 : integer := 0;
variable event_cnt_user : integer := 0;
begin begin
file_open(file_stimuli, "../tb/stimuli_mgt.dat", read_mode); wait until rising_edge(usr_clk);
readline(file_stimuli, file_line); -- comment if (dec_stream_valid = '1') then
readline(file_stimuli, file_line); -- comment addr := dec_stream_addr;
i := 0; data := dec_stream_data;
-- read line by line from .dat file: i := to_integer(unsigned(addr)) - to_integer(unsigned(segment_addr))*16;
while not endfile(file_stimuli) loop -- save stream for later comparision:
readline(file_stimuli, file_line); dec_stream_check(i).addr <= addr;
hread(file_line, event); dec_stream_check(i).data <= data;
read(file_line, event_k); log(ID_SEGMENT_DATA, "Recv Decoder Stream: count=" & integer'image(i) & " addr=0x" & to_string(addr, HEX) & " data=0x" & to_string(data, HEX));
read(file_line, space); i := i + 1;
read(file_line, space); dec_stream_recv_bytes <= i;
hread(file_line, data); end if;
read(file_line, space);
read(file_line, data_k);
-- write to array:
mgt_stream(i).data <= data;
mgt_stream(i).data_k <= data_k;
mgt_stream(i).event <= event;
mgt_stream(i).event_k <= event_k;
mgt_stream_index <= i;
--debug output:
--log(ID_SEGMENT_DATA, "stimuli file: i=" & integer'image(i) & " event=0x" & to_string(event, HEX) & " k=" & to_string(event_k, HEX)
-- & " data=0x" & to_string(data, HEX) & " k=" & to_string(data_k, HEX) & " ");
-- Count Events:
----------------
if (event /= x"00" and event_k = "0") then
event_cnt_total := event_cnt_total + 1;
if (event = std_logic_vector(to_unsigned(g_EVENT_NR_0, 8))) then
event_cnt_0 := event_cnt_0 + 1;
end if;
if (event = std_logic_vector(to_unsigned(g_EVENT_NR_1, 8))) then
event_cnt_1 := event_cnt_1 + 1;
end if;
if (event = std_logic_vector(to_unsigned(g_EVENT_NR_2, 8))) then
event_cnt_2 := event_cnt_2 + 1;
end if;
if (event = std_logic_vector(to_unsigned(g_EVENT_NR_3, 8))) then
event_cnt_3 := event_cnt_3 + 1;
end if;
end if;
expect_events_total <= event_cnt_total * STIMULI_RUNS;
expect_events(0) <= event_cnt_0 * STIMULI_RUNS;
expect_events(1) <= event_cnt_1 * STIMULI_RUNS;
expect_events(2) <= event_cnt_2 * STIMULI_RUNS;
expect_events(3) <= event_cnt_3 * STIMULI_RUNS;
-- Event Recorder:
------------------
if (event_k = "0") then
all_expected_events(to_integer(unsigned(event))) <= '1';
if (event = std_logic_vector(to_unsigned(g_EVENT_NR_SOS, 8))) then
log("Start-of-Sequence Event in Stimuli present");
end if;
if (event /= X"00" and event(7 downto 4) /= X"7") then
event_cnt_user := event_cnt_user + 1;
end if;
end if;
expected_user_events <= event_cnt_user;
-- Parse only segment:
----------------------
case (parse_fsm) is
when idle =>
if (data = x"5C" and data_k = "1") then -- check if frame start
parse_fsm := seg_start;
end if;
when seg_start =>
parse_fsm := seg_addr;
when seg_addr =>
segment_addr <= data;
parse_fsm := seg_wait;
when seg_wait =>
parse_fsm := seg_payload;
payload_cnt := 0;
when seg_payload =>
if (data = x"3C" and data_k = "1") then -- check if frame end
parse_fsm := seg_done;
else
segment_data(payload_cnt) <= data;
parse_fsm := seg_payload_wait;
segment_length <= payload_cnt+1;
end if;
when seg_payload_wait =>
payload_cnt := payload_cnt + 1;
parse_fsm := seg_payload;
when seg_done =>
-- done
end case;
i := i + 1;
end loop;
file_close(file_stimuli);
wait;
end process; end process;
end block;
---------------------------------------------------------
-- Receive decoder data stream
---------------------------------------------------------
process
variable addr : std_logic_vector(10 downto 0);
variable data : std_logic_vector(7 downto 0);
variable i : integer := 0;
begin
wait until rising_edge(usr_clk);
if (dec_stream_valid = '1') then
addr := dec_stream_addr;
data := dec_stream_data;
i := to_integer(unsigned(addr)) - to_integer(unsigned(segment_addr))*16;
-- save stream for later comparision:
dec_stream_check(i).addr <= addr;
dec_stream_check(i).data <= data;
log(ID_SEGMENT_DATA, "Recv Decoder Stream: count=" & integer'image(i) & " addr=0x" & to_string(addr, HEX) & " data=0x" & to_string(data, HEX));
i := i + 1;
dec_stream_recv_bytes <= i;
end if;
end process;
---------------------------------------------------------
-- Fetch filter data
---------------------------------------------------------
process
begin
wait until rising_edge(usr_clk);
if (filter_valid = '1') then
filter_data_check <= filter_data;
log(ID_SEGMENT_DATA, "Filter Valid: data=" & to_string(filter_data, HEX, AS_IS, INCL_RADIX));
end if;
end process;
---------------------------------------------------------
-- Wait for User Events
---------------------------------------------------------
process
begin
wait until rising_edge(rxusrclk);
for i in 0 to C_EVT_NR-1 loop
if (usr_events(i) = '1') then
log(ID_CTRL, "Event Received: " & to_string(evr_params.event_numbers(i), HEX, AS_IS, INCL_RADIX) );
received_events(i) <= received_events(i) + 1;
end if;
end loop;
end process;
---------------------------------------------------------
-- Wait for Start of Sequence Event
---------------------------------------------------------
process
begin
wait until rising_edge(rxusrclk);
if (sos_event = '1') then
log(ID_CTRL, "Start of Sequence Event Received: "& to_string(std_logic_vector(to_unsigned(g_EVENT_NR_SOS, 8)), HEX, AS_IS, INCL_RADIX) ); -- change to await_value
check_evt_rec_events <= '1';
end if;
end process;
----------------------------------------------------------------------------- ---------------------------------------------------------
-- Stimulus CPU interface -- Wait for Event
----------------------------------------------------------------------------- ---------------------------------------------------------
process process
constant C_SCOPE : string := C_TB_SCOPE_DEFAULT; begin
constant c_TB_NAME : string := "evr320_decoder_tb"; wait until rising_edge(usr_clk);
variable mgt_stream_rep_var : integer := 0; for i in 0 to 3 loop
variable mgt_stream_index_var : integer := 0; if (usr_events(i) = '1') then
variable i : integer := 0; log(ID_CTRL, "Event Received: 0x" & to_string(evr_params.event_numbers(i), HEX) );
type state is (idle, payload, frame_end, segment_nr); received_events <= received_events + 1;
variable mem_base : integer range 0 to 127; end if;
variable segment_data_word : std_logic_vector(31 downto 0); end loop;
variable var_filter_offset : integer range 0 to 2047; end process;
variable var_filter_word : std_logic_vector(FILTER_NUM_BYTES*8-1 downto 0);
variable expected_evt_rec_events : integer range 0 to 255 := 0; ---------------------------------------------------------
begin -- Fetch filter data
---------------------------------------------------------
process
begin
wait until rising_edge(usr_clk);
if (filter_valid = '1') then
filter_data_check <= filter_data;
log(ID_SEGMENT_DATA, "Filter Valid: data=0x" & to_string(filter_data, HEX));
end if;
end process;
-----------------------------------------------------------------------------
-- Read stimuli file
-----------------------------------------------------------------------------
file_blk : block
file file_stimuli : text;
type parse_fsm_state is (idle, seg_start, seg_addr, seg_Wait, seg_payload, seg_payload_wait, seg_done);
begin
process
variable file_line : line;
variable data, event : std_logic_vector(7 downto 0);
variable data_k, event_k : std_logic_vector(0 downto 0);
variable space : character;
variable i : integer;
variable parse_fsm : parse_fsm_state := idle;
variable payload_cnt : integer range 0 to 2047;
variable event_cnt : integer := 0;
begin
file_open(file_stimuli, "../tb/stimuli_mgt.dat", read_mode);
readline(file_stimuli, file_line); -- comment
readline(file_stimuli, file_line); -- comment
i := 0;
-- read line by line from .dat file:
while not endfile(file_stimuli) loop
readline(file_stimuli, file_line);
hread(file_line, event);
read(file_line, event_k);
read(file_line, space);
read(file_line, space);
hread(file_line, data);
read(file_line, space);
read(file_line, data_k);
-- write to array:
mgt_stream(i).data <= data;
mgt_stream(i).data_k <= data_k;
mgt_stream(i).event <= event;
mgt_stream(i).event_k <= event_k;
mgt_stream_index <= i;
--debug output:
--log(ID_SEGMENT_DATA, "stimuli file: i=" & integer'image(i) & " event=0x" & to_string(event, HEX) & " k=" & to_string(event_k, HEX)
-- & " data=0x" & to_string(data, HEX) & " k=" & to_string(data_k, HEX) & " ");
-- Count Events:
----------------
if (event /= x"00" and event_k = "0") then
event_cnt := event_cnt + 1;
end if;
expect_num_events <= event_cnt * STIMULI_RUNS;
-- Parse only segment:
----------------------
case (parse_fsm) is
when idle =>
if (data = x"5C" and data_k = "1") then -- check if frame start
parse_fsm := seg_start;
end if;
when seg_start =>
parse_fsm := seg_addr;
when seg_addr =>
segment_addr <= data;
parse_fsm := seg_wait;
when seg_wait =>
parse_fsm := seg_payload;
payload_cnt := 0;
when seg_payload =>
if (data = x"3C" and data_k = "1") then -- check if frame end
parse_fsm := seg_done;
else
segment_data(payload_cnt) <= data;
parse_fsm := seg_payload_wait;
segment_length <= payload_cnt+1;
end if;
when seg_payload_wait =>
payload_cnt := payload_cnt + 1;
parse_fsm := seg_payload;
when seg_done =>
-- done
end case;
i := i + 1;
end loop;
file_close(file_stimuli);
wait;
end process;
end block;
-----------------------------------------------------------------------------
-- Stimulus CPU interface
-----------------------------------------------------------------------------
process
constant C_SCOPE : string := C_TB_SCOPE_DEFAULT;
constant c_TB_NAME : string := "evr320_decoder_tb";
variable mgt_stream_rep_var : integer := 0;
variable mgt_stream_index_var : integer := 0;
variable i : integer := 0;
type state is (idle, payload, frame_end, segment_nr);
variable mem_base : integer range 0 to 127;
variable segment_data_word : std_logic_vector(31 downto 0);
variable var_filter_offset : integer range 0 to 2047;
variable var_filter_word : std_logic_vector(FILTER_NUM_BYTES*8-1 downto 0);
begin
-- init uvvm: -- init uvvm:
set_log_file_name(c_TB_NAME & "_LOG.txt"); set_log_file_name(c_TB_NAME & "_LOG.txt");
set_alert_file_name(c_TB_NAME & "_ALERT.txt"); set_alert_file_name(c_TB_NAME & "_ALERT.txt");
set_alert_stop_limit(ERROR, 0); -- never(0) pause simulator on error set_alert_stop_limit(ERROR, 0); -- never(0) pause simulator on error
set_alert_stop_limit(TB_ERROR, 0); -- never(0) pause simulator on error set_alert_stop_limit(TB_ERROR, 0); -- never(0) pause simulator on error
enable_log_msg(ALL_MESSAGES); enable_log_msg(ALL_MESSAGES);
--------------------------------------------------------------------------
log(ID_LOG_HDR, "Start Simulation of evr320 decoder", C_SCOPE); log(ID_LOG_HDR, "Start Simulation of evr320 decoder", C_SCOPE);
--------------------------------------------------------------------------
-------------------------------------------------------------------------- --------------------------------------------------------------------------
-- Get out of reset, enable events -- Get out of reset, enable events
-------------------------------------------------------------------------- --------------------------------------------------------------------------
evr_params.event_enable( 0) <= '0' when g_EVENT_NR_0 = 0 else '1'; evr_params.event_enable( 0) <= '1';
evr_params.event_enable( 1) <= '0' when g_EVENT_NR_1 = 0 else '1'; evr_params.event_enable( 1) <= '0';
evr_params.event_enable( 2) <= '0' when g_EVENT_NR_2 = 0 else '1'; evr_params.event_enable( 2) <= '0';
evr_params.event_enable( 3) <= '0' when g_EVENT_NR_3 = 0 else '1'; evr_params.event_enable( 3) <= '0';
event_recorder_ctrl.event_enable <= '0' when g_EVENT_NR_SOS = 0 else '1'; evr_params.event_numbers( 0)<= X"0F";
evr_params.event_numbers( 0) <= std_logic_vector(to_unsigned(g_EVENT_NR_0, 8)); evr_params.event_numbers( 1)<= X"00";
evr_params.event_numbers( 1) <= std_logic_vector(to_unsigned(g_EVENT_NR_1, 8)); evr_params.event_numbers( 2)<= X"00";
evr_params.event_numbers( 2) <= std_logic_vector(to_unsigned(g_EVENT_NR_2, 8)); evr_params.event_numbers( 3)<= X"00";
evr_params.event_numbers( 3) <= std_logic_vector(to_unsigned(g_EVENT_NR_3, 8)); evr_params.cs_min_cnt <= X"00000000";
event_recorder_ctrl.event_number <= std_logic_vector(to_unsigned(g_EVENT_NR_SOS, 8)); evr_params.cs_min_time <= X"00000000";
evr_params.cs_min_cnt <= X"00000000"; mem_addr <= x"000";
evr_params.cs_min_time <= X"00000000";
mem_addr <= x"000";
await_value(rxlos, '0', 0 ns, 10 us, FAILURE, "wait for release RX LOS"); await_value(rxlos, '0', 0 ns, 10 us, FAILURE, "wait for release RX LOS");
--wait until (rxlos = '0'); --wait until (rxlos = '0');
@@ -438,7 +350,7 @@ begin
-------------------------------------------------------------------------- --------------------------------------------------------------------------
wait until rising_edge(rxusrclk); wait until rising_edge(rxusrclk);
for b in 0 to STIMULI_RUNS-1 loop for b in 0 to STIMULI_RUNS-1 loop
log(ID_LOG_HDR, "Send stimuli stream to MGT - RUN " & to_string(b+1)); log(ID_DATA, "Send stimuli stream to MGT");
for idx in 0 to mgt_stream_index loop for idx in 0 to mgt_stream_index loop
--log(ID_FRAME_DATA, to_string(mgt_stream(idx).data, HEX), to_string(mgt_stream(idx).event, HEX)); --log(ID_FRAME_DATA, to_string(mgt_stream(idx).data, HEX), to_string(mgt_stream(idx).event, HEX));
wait until rising_edge(rxusrclk); wait until rising_edge(rxusrclk);
@@ -448,7 +360,7 @@ begin
end loop; end loop;
-------------------------------------------------------------------------- --------------------------------------------------------------------------
log(ID_LOG_HDR, "Check if decoder stream is correct", C_SCOPE); -- Check if decoder stream is correct
-------------------------------------------------------------------------- --------------------------------------------------------------------------
await_value(dec_stream_recv_bytes, segment_length, 0 ns, 5 us, ERROR, "Wait for right number of bytes streamed"); await_value(dec_stream_recv_bytes, segment_length, 0 ns, 5 us, ERROR, "Wait for right number of bytes streamed");
-- loop through segment and compare frame bytes with received decoder-stream: -- loop through segment and compare frame bytes with received decoder-stream:
@@ -457,7 +369,7 @@ begin
end loop; end loop;
-------------------------------------------------------------------------- --------------------------------------------------------------------------
log(ID_LOG_HDR, "Check if filter data is correct", C_SCOPE); -- Check if filter data is correct
-------------------------------------------------------------------------- --------------------------------------------------------------------------
var_filter_offset := to_integer(unsigned(FILTER_ADDRESS)) - (to_integer(unsigned(segment_addr))*16); var_filter_offset := to_integer(unsigned(FILTER_ADDRESS)) - (to_integer(unsigned(segment_addr))*16);
--log(ID_CTRL, "var_filter_offset=" & integer'image(var_filter_offset) & " : " & to_string(FILTER_ADDRESS,HEX) & " : " & to_string(segment_addr, HEX)); --log(ID_CTRL, "var_filter_offset=" & integer'image(var_filter_offset) & " : " & to_string(FILTER_ADDRESS,HEX) & " : " & to_string(segment_addr, HEX));
@@ -471,64 +383,12 @@ begin
-------------------------------------------------------------------------- --------------------------------------------------------------------------
-- Check if correct number of events has been detected -- Check if correct number of events has been detected
-------------------------------------------------------------------------- --------------------------------------------------------------------------
for i in 0 to C_EVT_NR-1 loop check_value(received_events, expect_num_events, ERROR, "Check correct number of received events");
check_value(received_events(i), expect_events(i), ERROR, "Event " & to_string(i) & ": received = " & to_string(received_events(i)) & ", expected = " & to_string(expect_events(i)));
end loop;
-------------------------------------------------------------------------- --------------------------------------------------------------------------
log(ID_LOG_HDR, "Event Recorder Checks", C_SCOPE); -- Read DPRAM buffer
-------------------------------------------------------------------------- --------------------------------------------------------------------------
wait for 1 us; wait for 1 us;
if (C_EVENT_RECORDER) then
if (check_evt_rec_events = '1' and STIMULI_RUNS > 1) then
----------------------------------------------------------------------
log(ID_DATA, "Check expected Event Flags after SOS Event detected");
----------------------------------------------------------------------
wait until rising_edge(usr_clk);
for addr in 0 to 63 loop
mem_addr <= C_EVENT_REC_FLAGS & std_logic_vector(to_unsigned(addr, 6));
wait until rising_edge(usr_clk);
await_value(mem_data(0), all_expected_events(4*addr), 0 ns, 1 ns, ERROR, "Event " & to_string(4*addr) & " Flag");
await_value(mem_data(8), all_expected_events(4*addr + 1), 0 ns, 1 ns, ERROR, "Event " & to_string(4*addr + 1) & " Flag");
await_value(mem_data(16), all_expected_events(4*addr + 2), 0 ns, 1 ns, ERROR, "Event " & to_string(4*addr + 2) & " Flag");
await_value(mem_data(24), all_expected_events(4*addr + 3), 0 ns, 1 ns, ERROR, "Event " & to_string(4*addr + 3) & " Flag");
end loop;
----------------------------------------------------------------------
log(ID_DATA, "Check Memory block border");
----------------------------------------------------------------------
-- read data mux switching made visible with delayed address.
mem_addr <= C_EVENT_REC_FLAGS & "000000";
wait until rising_edge(usr_clk);
wait for C_USRCLK_CYCLE/4;
for addr in 62 to 65 loop
mem_addr <= (C_EVENT_REC_FLAGS & "000000") + std_logic_vector(to_unsigned(addr, 7));
wait until rising_edge(usr_clk);
check_stable(mem_data, C_USRCLK_CYCLE, ERROR, "Read Data stable on Output");
wait for C_USRCLK_CYCLE/4;
if (addr < 64) then
check_value(mem_data(0), all_expected_events(4*addr), ERROR, "Event " & to_string(4*addr) & " Flag");
check_value(mem_data(8), all_expected_events(4*addr + 1), ERROR, "Event " & to_string(4*addr + 1) & " Flag");
check_value(mem_data(16), all_expected_events(4*addr + 2), ERROR, "Event " & to_string(4*addr + 2) & " Flag");
check_value(mem_data(24), all_expected_events(4*addr + 3), ERROR, "Event " & to_string(4*addr + 3) & " Flag");
else
check_value(mem_data, X"0000_0000", ERROR, "After Event Recorder Mem Map");
end if;
end loop;
----------------------------------------------------------------------
log(ID_DATA, "Check expected Event Recorder User Events");
----------------------------------------------------------------------
check_value(to_integer(unsigned(event_recorder_status.usr_events_counter)), expected_user_events, ERROR, "Total User Events: received = " & to_string(to_integer(unsigned(event_recorder_status.usr_events_counter))) & ", expected = " & to_string(expected_user_events));
end if;
end if;
--------------------------------------------------------------------------
log(ID_LOG_HDR, "Read DPRAM buffer", C_SCOPE);
--------------------------------------------------------------------------
wait for 50 * C_USRCLK_CYCLE;
log(ID_DATA, "Read Segment from DPRAM"); log(ID_DATA, "Read Segment from DPRAM");
-- print 16 words from dpram data buffer: -- print 16 words from dpram data buffer:
for offset in 0 to segment_length/4-1 loop for offset in 0 to segment_length/4-1 loop
@@ -548,17 +408,16 @@ begin
-------------------------------------------------------------------------- --------------------------------------------------------------------------
-- Test Done -- Test Done
-------------------------------------------------------------------------- --------------------------------------------------------------------------
wait for 1000 ns; -- to allow some time for completion
report_alert_counters(FINAL); -- Report final counters and print conclusion for simulation (Success/Fail)
-- ------------------------------------------------------------------------
log(ID_LOG_HDR, "SIMULATION COMPLETED", C_SCOPE); log(ID_LOG_HDR, "SIMULATION COMPLETED", C_SCOPE);
-- ------------------------------------------------------------------------ report_alert_counters(VOID);
-- assert error if UVVM mismatch flag is 1 => upstream info for scripts/jenkins
assert shared_uvvm_status.mismatch_on_expected_simulation_errors_or_worse = 0 report "###ERROR### - UVVM Mismatch Errors with Expected Errors -> Check Log for details" severity ERROR;
std.env.stop(0);
wait; -- stop simulation
end process; assert shared_uvvm_status.found_unexpected_simulation_warnings_or_worse = 0
report "UVVM Found unexpected warnings or worse" severity ERROR;
stop(0);
-- finish(0); -- wants to close modelsim!?
wait;
end process;
end architecture testbench; end architecture testbench;

596
tb/evr320_ifc1210_wrapper_tb.vhd
View File

@@ -1,596 +0,0 @@
--------------------------------------------------------------------------------
-- ifc1210_wrapper testbench
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_1164.all;
library std;
use std.env.all;
use std.textio.all;
library tosca2;
use tosca2.ifc1210_simu_procedures_pkg.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
-- Work library (application) --------------------------------------------------
library work;
use work.evr320_pkg.all;
use work.psi_common_math_pkg.all;
entity evr320_ifc1210_wrapper_tb is
end entity;
architecture testbench of evr320_ifc1210_wrapper_tb is
---------------------------------------------------------------------------
-- System
---------------------------------------------------------------------------
constant C_RXUSRCLK_CYCLE : time := 7 ns;
constant C_USRCLK_CYCLE : time := 8 ns;
constant C_EVT_NR : integer := 4;
constant C_MEM_DATA_WIDTH : integer := 32; -- 32|64 (64 bit used for tosca2 on ifc1210)
constant C_EVENT_RECORDER : boolean := true;
constant C_EVENT_REC_FLAGS : std_logic_vector(11 downto 6) := B"1101_11";
constant g_EVENT_NR_SOS : integer range 0 to 255 := 16#20#;
constant g_EVENT_NR_0 : integer range 0 to 255 := 16#00#;
constant g_EVENT_NR_1 : integer range 0 to 255 := 16#04#;
constant g_EVENT_NR_2 : integer range 0 to 255 := 16#00#;
constant g_EVENT_NR_3 : integer range 0 to 255 := 16#00#;
---------------------------------------------------------------------------
-- MGT stream
---------------------------------------------------------------------------
type mgt_stream_sample_type is record
data : std_logic_vector(7 downto 0);
data_k : std_logic_vector(0 downto 0);
event : std_logic_vector(7 downto 0);
event_k : std_logic_vector(0 downto 0);
end record mgt_stream_sample_type;
type mgt_stream_type is array (natural range <>) of mgt_stream_sample_type;
signal mgt_stream_index : integer range 0 to 511 := 0;
signal mgt_stream : mgt_stream_type(511 downto 0) := (others => (others => (others => '0')));
-----------------------------------------------------------------------------
-- Timing decoder interface
-----------------------------------------------------------------------------
signal usr_clk : std_logic := '0';
signal evr_params : typ_evr320_params;
signal mem_addr : std_logic_vector(11 downto 0) := (others => '0');
signal mem_data : std_logic_vector(31 downto 0) := (others => '0');
-- Decoder stream
type dec_stream_type is record
data : std_logic_vector(7 downto 0);
addr : std_logic_vector(10 downto 0);
end record dec_stream_type;
type dec_stream_check_arr is array (natural range <>) of dec_stream_type;
signal dec_stream_data : std_logic_vector(7 downto 0) := (others => '0');
signal dec_stream_addr : std_logic_vector(10 downto 0) := (others => '0');
signal dec_stream_valid : std_logic;
signal dec_stream_check : dec_stream_check_arr(0 to 2047);
signal dec_stream_recv_bytes : integer range 0 to 2047;
type segment_data_arr is array (natural range <>) of std_logic_vector(7 downto 0);
signal segment_addr : std_logic_vector(7 downto 0);
signal segment_data : segment_data_arr(0 to 2047);
signal segment_length : natural range 0 to 2047;
constant FILTER_ADDRESS : std_logic_vector(11 downto 0) := x"028";
constant FILTER_NUM_BYTES : integer := 8;
constant STIMULI_RUNS : integer := 2;
signal filter_data, filter_data_check : std_logic_vector(63 downto 0) := (others => '0');
signal filter_valid : std_logic := '0';
signal tmem_i : tmem_bus_in_t;
signal tmem_o : tmem_bus_out_t;
signal tmem_clk : std_logic;
signal tmem_rst : std_logic;
signal tmem_data_rd : std_logic_vector(63 downto 0);
signal tick1sec : std_logic;
alias rxlos is <<signal .evr320_ifc1210_wrapper_tb.evr320_ifc1210_wrapper_inst.evr320_decoder_inst.i_mgt_rst : std_logic>>;
alias clk_evr is <<signal .evr320_ifc1210_wrapper_tb.evr320_ifc1210_wrapper_inst.clk_evr : std_logic>>;
alias rxdata is <<signal .evr320_ifc1210_wrapper_tb.evr320_ifc1210_wrapper_inst.evr320_decoder_inst.i_mgt_rx_data : std_logic_vector(15 downto 0)>>;
alias rxcharisk is <<signal .evr320_ifc1210_wrapper_tb.evr320_ifc1210_wrapper_inst.evr320_decoder_inst.i_mgt_rx_charisk : std_logic_vector(1 downto 0)>>;
alias sos_event is <<signal .evr320_ifc1210_wrapper_tb.evr320_ifc1210_wrapper_inst.evr320_decoder_inst.o_sos_event : std_logic>>;
alias usr_events is <<signal .evr320_ifc1210_wrapper_tb.evr320_ifc1210_wrapper_inst.evr320_decoder_inst.o_usr_events : std_logic_vector(3 downto 0)>>;
alias evr_stable is <<signal .evr320_ifc1210_wrapper_tb.evr320_ifc1210_wrapper_inst.evr320_decoder_inst.evr_stable : std_logic>>;
--*** stimuli for delay & pulse width ***
signal usr_event_width_sti : typ_arr_width := (to_uslv(2, log2ceil(MaxDuration_c)), --sos set to 2
to_uslv(3, log2ceil(MaxDuration_c)), --0
to_uslv(4, log2ceil(MaxDuration_c)), --1
to_uslv(5, log2ceil(MaxDuration_c)), --2
to_uslv(6, log2ceil(MaxDuration_c)) --3
);
signal usr_event_delay_sti : typ_arr_delay := (to_uslv(2, log2ceil(MaxDelay_c)), --sos set to 2
to_uslv(3, log2ceil(MaxDelay_c)), --0
to_uslv(4, log2ceil(MaxDelay_c)), --1
to_uslv(5, log2ceil(MaxDelay_c)), --2
to_uslv(6, log2ceil(MaxDelay_c)) --3
);
begin
tmem_o.TMEM_BUSY_o <= '0';
tmem_o.TMEM_PIPE_o <= "10";
-----------------------------------------------------------------------------
-- Timing decoder
-----------------------------------------------------------------------------
evr320_ifc1210_wrapper_inst : entity work.evr320_ifc1210_wrapper
generic map(
g_MGT_LOCATION => "GTXE1_X0Y16", -- "GTXE1_X0Y0" to "GTXE1_X0Y11" | "GTXE1_X0Y16" to "GTXE1_X0Y19"
g_FACILITY => "SFEL", -- "HIPA" | "SFEL"
g_EVENT_RECORDER => C_EVENT_RECORDER, -- enable/disable Event Recorder functionality
g_XUSER_CLK_FREQ => 125000000 -- Xuser Clk Frequency in Hz
)
port map(
--------------------------------------------------------------------------
-- Debug interface
--------------------------------------------------------------------------
debug_clk => open,
debug => open,
--------------------------------------------------------------------------
-- TOSCA2 TMEM interface
--------------------------------------------------------------------------
xuser_CLK => tmem_clk,
xuser_RESET => tmem_rst,
xuser_TMEM_ENA => tmem_i.TMEM_ENA_i,
xuser_TMEM_WE => tmem_i.TMEM_WE_i,
xuser_TMEM_ADD => tmem_i.TMEM_ADD_i(13 downto 3),
xuser_TMEM_DATW => tmem_i.TMEM_DATW_i,
xuser_TMEM_DATR => tmem_o.TMEM_DATR_o,
-- ------------------------------------------------------------------------
-- MGT Interface
-- ------------------------------------------------------------------------
mgt_refclk_i => '0',
mgt_sfp_los_i => '0',
mgt_rx_n => '0',
mgt_rx_p => '0',
mgt_tx_n => open,
mgt_tx_p => open,
mgt_status_o => open,
mgt_control_i => (others => '0'),
---------------------------------------------------------------------------
-- User interface MGT clock
---------------------------------------------------------------------------
clk_evr_o => open,
usr_events_o => open,
sos_event_o => open,
usr_events_adj_o => open,
sos_events_adj_o => open,
--------------------------------------------------------------------------
-- Decoder axi stream interface, User clock
--------------------------------------------------------------------------
stream_clk_i => '1',
stream_data_o => open,
stream_addr_o => open,
stream_valid_o => open
);
gen_pulse(tick1sec, '1', usr_clk, 1, "");
-----------------------------------------------------------------------------
-- MGT / User clock
-----------------------------------------------------------------------------
clock_generator(usr_clk, C_USRCLK_CYCLE);
tmem_clk <= usr_clk;
-- Simulate MGT Clock
mgt_clk_proc : process
begin
clk_evr <= force in '0';
loop
wait for C_RXUSRCLK_CYCLE / 2;
clk_evr <= force in not (clk_evr);
end loop;
end process;
-----------------------------------------------------------------------------
-- Decoder reset due to MGT main status
-----------------------------------------------------------------------------
process
begin
rxlos <= force in '1';
tmem_rst <= '1';
wait for 50 ns;
wait until (falling_edge(clk_evr));
rxlos <= force in '0';
tmem_rst <= '0';
wait;
end process;
-----------------------------------------------------------------------------
-- Read stimuli file
-----------------------------------------------------------------------------
file_blk : block
file file_stimuli : text;
type parse_fsm_state is (idle, seg_start, seg_addr, seg_Wait, seg_payload, seg_payload_wait, seg_done);
begin
process
variable file_line : line;
variable data, event : std_logic_vector(7 downto 0);
variable data_k, event_k : std_logic_vector(0 downto 0);
variable space : character;
variable i : integer;
variable parse_fsm : parse_fsm_state := idle;
variable payload_cnt : integer range 0 to 2047;
variable event_cnt_total : integer := 0;
variable event_cnt_0 : integer := 0;
variable event_cnt_1 : integer := 0;
variable event_cnt_2 : integer := 0;
variable event_cnt_3 : integer := 0;
variable event_cnt_user : integer := 0;
begin
file_open(file_stimuli, "../tb/stimuli_mgt.dat", read_mode);
readline(file_stimuli, file_line); -- comment
readline(file_stimuli, file_line); -- comment
i := 0;
-- read line by line from .dat file:
while not endfile(file_stimuli) loop
readline(file_stimuli, file_line);
hread(file_line, event);
read(file_line, event_k);
read(file_line, space);
read(file_line, space);
hread(file_line, data);
read(file_line, space);
read(file_line, data_k);
-- write to array:
mgt_stream(i).data <= data;
mgt_stream(i).data_k <= data_k;
mgt_stream(i).event <= event;
mgt_stream(i).event_k <= event_k;
mgt_stream_index <= i;
--debug output:
--log(ID_SEGMENT_DATA, "stimuli file: i=" & integer'image(i) & " event=0x" & to_string(event, HEX) & " k=" & to_string(event_k, HEX)
-- & " data=0x" & to_string(data, HEX) & " k=" & to_string(data_k, HEX) & " ");
-- Parse only segment:
----------------------
case (parse_fsm) is
when idle =>
if (data = x"5C" and data_k = "1") then -- check if frame start
parse_fsm := seg_start;
end if;
when seg_start =>
parse_fsm := seg_addr;
when seg_addr =>
segment_addr <= data;
parse_fsm := seg_wait;
when seg_wait =>
parse_fsm := seg_payload;
payload_cnt := 0;
when seg_payload =>
if (data = x"3C" and data_k = "1") then -- check if frame end
parse_fsm := seg_done;
else
segment_data(payload_cnt) <= data;
parse_fsm := seg_payload_wait;
segment_length <= payload_cnt + 1;
end if;
when seg_payload_wait =>
payload_cnt := payload_cnt + 1;
parse_fsm := seg_payload;
when seg_done =>
-- done
end case;
i := i + 1;
end loop;
file_close(file_stimuli);
wait;
end process;
end block;
---------------------------------------------------------
-- Wait for Start of Sequence Event
---------------------------------------------------------
process
begin
wait until rising_edge(sos_event);
log(ID_CTRL, "Start of Sequence Event Received: " & to_string(std_logic_vector(to_unsigned(g_EVENT_NR_SOS, 8)), HEX, AS_IS, INCL_RADIX)); -- change to await_value
end process;
--------------------------------------------------------------------------
-- Stimuli MGT
--------------------------------------------------------------------------
process
begin
wait until rising_edge(clk_evr);
for b in 0 to STIMULI_RUNS - 1 loop
log(ID_LOG_HDR, "Send stimuli stream to MGT - RUN " & to_string(b + 1));
for idx in 0 to mgt_stream_index loop
--log(ID_FRAME_DATA, to_string(mgt_stream(idx).data, HEX), to_string(mgt_stream(idx).event, HEX));
wait until rising_edge(clk_evr);
rxdata <= force out mgt_stream(idx).data & mgt_stream(idx).event;
rxcharisk <= force out mgt_stream(idx).data_k & mgt_stream(idx).event_k;
end loop;
wait for 3 us;
end loop;
wait;
end process;
-----------------------------------------------------------------------------
-- Main Process
-----------------------------------------------------------------------------
process
constant C_SCOPE : string := C_TB_SCOPE_DEFAULT;
constant c_TB_NAME : string := "evr320_decoder_tb";
variable latency_cnt_val : unsigned(31 downto 0);
begin
disable_log_msg(ID_GEN_PULSE);
--------------------------------------------------------------------------
log(ID_LOG_HDR, "Start Simulation of evr320 decoder", C_SCOPE);
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Get out of reset, enable events
--------------------------------------------------------------------------
evr_params.event_enable(0) <= '0' when g_EVENT_NR_0 = 0 else '1';
evr_params.event_enable(1) <= '0' when g_EVENT_NR_1 = 0 else '1';
evr_params.event_enable(2) <= '0' when g_EVENT_NR_2 = 0 else '1';
evr_params.event_enable(3) <= '0' when g_EVENT_NR_3 = 0 else '1';
evr_params.event_numbers(0) <= std_logic_vector(to_unsigned(g_EVENT_NR_0, 8));
evr_params.event_numbers(1) <= std_logic_vector(to_unsigned(g_EVENT_NR_1, 8));
evr_params.event_numbers(2) <= std_logic_vector(to_unsigned(g_EVENT_NR_2, 8));
evr_params.event_numbers(3) <= std_logic_vector(to_unsigned(g_EVENT_NR_3, 8));
evr_params.cs_min_cnt <= X"00000000";
evr_params.cs_min_time <= X"00000000";
mem_addr <= x"000";
await_value(rxlos, '0', 0 ns, 10 us, FAILURE, "wait for release RX LOS");
-- overwrite evr_stable flag:
evr_stable <= force '1';
-- enable sos event and set event number:
TMEM_BUS_WRITE(seqid => "A00_001",
tmem_add => x"00_0040",
tmem_we => x"0F",
tmem_burst => 1,
tmem_data_wr => x"0000_0000_0000_2001",
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
-- read back sos event and event number:
TMEM_BUS_READ(seqid => "A00_001",
tmem_add => x"00_0040",
tmem_burst => 1,
tmem_data_rd => tmem_data_rd,
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
-- ---------------------------------------------------------
-- send delay and width parameters:
TMEM_BUS_WRITE(seqid => "A00_002",
tmem_add => x"00_0050",
tmem_we => x"FF",
tmem_burst => 1,
tmem_data_wr => x"0005_0004_0003_0002",
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
-- read back delay parameters:
TMEM_BUS_READ(seqid => "A00_002",
tmem_add => x"00_0050",
tmem_burst => 1,
tmem_data_rd => tmem_data_rd,
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
check_value(tmem_data_rd, x"0005_0004_0003_0002", ERROR, "TMEM Write/Read check: EVR Puls delay Event Cfg");
-- ---------------------------------------------------------
-- ---------------------------------------------------------
-- send width and width parameters:
TMEM_BUS_WRITE(seqid => "A00_003",
tmem_add => x"00_0058",
tmem_we => x"FF",
tmem_burst => 1,
tmem_data_wr => x"0009_0008_0007_0006",
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
-- read back delay parameters:
TMEM_BUS_READ(seqid => "A00_003",
tmem_add => x"00_0058",
tmem_burst => 1,
tmem_data_rd => tmem_data_rd,
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
check_value(tmem_data_rd, x"0009_0008_0007_0006", ERROR, "TMEM Write/Read check: EVR Puls Width Event Cfg");
-- ---------------------------------------------------------
-- ---------------------------------------------------------
-- send width and width parameters for SOS:
TMEM_BUS_WRITE(seqid => "A00_004",
tmem_add => x"00_0060",
tmem_we => x"FF",
tmem_burst => 1,
tmem_data_wr => x"0000_0000_0001_0001",
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
-- read back delay parameters:
TMEM_BUS_READ(seqid => "A00_004",
tmem_add => x"00_0060",
tmem_burst => 1,
tmem_data_rd => tmem_data_rd,
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
check_value(tmem_data_rd, x"0000_0000_0001_0001", ERROR, "TMEM Write/Read check: SOS width & delay Event Cfg");
-- ---------------------------------------------------------
-- latency measurement: set event nr:
TMEM_BUS_WRITE(seqid => "A00_002",
tmem_add => x"00_0030",
tmem_we => x"0F",
tmem_burst => 1,
tmem_data_wr => x"0000_0000_0000_0020",
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
-- read back sos event and event number:
TMEM_BUS_READ(seqid => "A00_002",
tmem_add => x"00_0030",
tmem_burst => 1,
tmem_data_rd => tmem_data_rd,
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
-- latency measurement: set event nr:
TMEM_BUS_WRITE(seqid => "A00_002",
tmem_add => x"00_0030",
tmem_we => x"0F",
tmem_burst => 1,
tmem_data_wr => x"0000_0000_0000_0020",
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
-- read back sos event and event number:
TMEM_BUS_READ(seqid => "A00_002",
tmem_add => x"00_0030",
tmem_burst => 1,
tmem_data_rd => tmem_data_rd,
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
check_value(tmem_data_rd, x"0000_0000_0000_0020", ERROR, "TMEM Write/Read check: lat. meas. event nr");
-- 1. check latency measurement counter:
----------------------------------------
await_value(sos_event, '1', 0 ns, 2 us, ERROR, "wait for sos event");
wait for 2000 ns;
latency_cnt_val := x"00000000";
-- read latency measurement counter without rearm:
TMEM_BUS_READ(seqid => "A00_002",
tmem_add => x"00_0030",
tmem_burst => 1,
tmem_data_rd => tmem_data_rd,
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
latency_cnt_val := unsigned(tmem_data_rd(63 downto 32));
log(ID_CTRL, "Latency Counter: 0x" & to_string(latency_cnt_val, HEX));
check_value_in_range(latency_cnt_val, x"000000F5", x"000000FE", ERROR, "Latency Counter Value (no-rearm) Check after 2us");
-- 2. read latency measurement counter again with rearm:
--------------------------------------------------------
latency_cnt_val := x"00000000";
TMEM_BUS_READ(seqid => "A00_002",
tmem_add => x"00_0038",
tmem_burst => 1,
tmem_data_rd => tmem_data_rd,
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
latency_cnt_val := unsigned(tmem_data_rd(31 downto 0));
log(ID_CTRL, "Latency Counter: 0x" & to_string(latency_cnt_val, HEX));
check_value_in_range(latency_cnt_val, x"000000FA", x"00000102", ERROR, "Latency Counter Value (rearm) Check directly after first read");
-- read 2. time rearm latency counter which should be cleared now:
TMEM_BUS_READ(seqid => "A00_002",
tmem_add => x"00_0038",
tmem_burst => 1,
tmem_data_rd => tmem_data_rd,
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
latency_cnt_val := unsigned(tmem_data_rd(31 downto 0));
check_value(latency_cnt_val, x"00000000", ERROR, "Check if counter is cleared");
-- 4. read latency measurement counter with rearm:
--------------------------------------------------
await_value(sos_event, '1', 0 ns, 3 us, ERROR, "wait for sos event");
wait for 1 us;
-- read counter and rearm:
TMEM_BUS_READ(seqid => "A00_002",
tmem_add => x"00_0038",
tmem_burst => 1,
tmem_data_rd => tmem_data_rd,
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
latency_cnt_val := unsigned(tmem_data_rd(31 downto 0));
log(ID_CTRL, "Latency Counter: 0x" & to_string(latency_cnt_val, HEX));
check_value_in_range(latency_cnt_val, x"0000007A", x"00000080", ERROR, "Latency Counter Value (rearm) Check after 1us");
--------------------------------------------------------------------------
-- Test Done
--------------------------------------------------------------------------
wait for 1000 ns; -- to allow some time for completion
report_alert_counters(FINAL); -- Report final counters and print conclusion for simulation (Success/Fail)
-- ------------------------------------------------------------------------
log(ID_LOG_HDR, "SIMULATION COMPLETED", C_SCOPE);
-- ------------------------------------------------------------------------
-- assert error if UVVM mismatch flag is 1 => upstream info for scripts/jenkins
assert shared_uvvm_status.mismatch_on_expected_simulation_errors_or_worse = 0 report "###ERROR### - UVVM Mismatch Errors with Expected Errors -> Check Log for details" severity ERROR;
std.env.stop(0);
wait; -- stop simulation
end process;
end architecture testbench;
--------------------------------------------------------------------------------
-- End of file
--------------------------------------------------------------------------------

108
tb/stimuli_mgt.dat
View File

@@ -95,93 +95,37 @@ BC 1 00 0 align
00 0 00 0 gap 00 0 00 0 gap
BC 1 00 0 align BC 1 00 0 align
00 0 00 0 gap 00 0 00 0 gap
04 0 00 0 event 4 00 0 00 0 gap
00 0 00 0 gap 00 0 00 0 gap
BC 1 00 0 align BC 1 00 0 align
00 0 00 0 gap 00 0 00 0 gap
70 0 00 0 system event 00 0 00 0 gap
00 0 00 0 gap
BC 1 00 0 align
00 0 00 0 gap
00 0 00 0 gap
00 0 00 0 gap
BC 1 00 0 align
00 0 00 0 gap
00 0 00 0 gap
00 0 00 0 gap
BC 1 00 0 align
00 0 00 0 gap
00 0 00 0 gap
00 0 00 0 gap
BC 1 00 0 align
00 0 00 0 gap
00 0 00 0 gap
00 0 00 0 gap
BC 1 00 0 align
00 0 00 0 gap
00 0 00 0 gap
00 0 00 0 gap
BC 1 00 0 align
00 0 00 0 gap
00 0 00 0 gap
00 0 00 0 gap 00 0 00 0 gap
BC 1 00 0 align BC 1 00 0 align
00 0 00 0 gap 00 0 00 0 gap
0F 0 00 0 BPM event 0F 0 00 0 BPM event
00 0 00 0 gap 00 0 00 0 gap
BC 1 00 0 align
00 0 00 0 gap
00 0 00 0 gap
00 0 00 0 gap
BC 1 00 0 align
00 0 00 0 gap
00 0 00 0 gap
00 0 00 0 gap
BC 1 00 0 align
00 0 00 0 gap
20 0 00 0 event Start-of-Sequence
00 0 00 0 gap
BC 1 00 0 align
00 0 00 0 gap
00 0 00 0 gap
00 0 00 0 gap
BC 1 00 0 align
00 0 00 0 gap
00 0 00 0 gap
00 0 00 0 gap
BC 1 00 0 align
00 0 00 0 gap
00 0 00 0 gap
00 0 00 0 gap
BC 1 00 0 align
01 0 00 0 event 1
02 0 00 0 event 2
03 0 00 0 event 3
BC 1 00 0 align
04 0 00 0 event 4
05 0 00 0 event 5
06 0 00 0 event 6
BC 1 00 0 align
07 0 00 0 event 7
08 0 00 0 event 8
09 0 00 0 event 9
BC 1 00 0 align
0A 0 00 0 event 10
0B 0 00 0 event 11
0C 0 00 0 event 12
BC 1 00 0 align
32 0 00 0 event 50
33 0 00 0 event 51
34 0 00 0 event 52
BC 1 00 0 align
35 0 00 0 event 53
36 0 00 0 event 54
37 0 00 0 event 55
BC 1 00 0 align
38 0 00 0 event 56
39 0 00 0 event 57
3A 0 00 0 event 58
BC 1 00 0 align
FA 0 00 0 event 250
FB 0 00 0 event 251
FC 0 00 0 event 252
BC 1 00 0 align
FD 0 00 0 event 253
FE 0 00 0 event 254
FF 0 00 0 event 255
BC 1 00 0 align
00 0 00 0 gap
0F 0 00 0 gap
00 0 00 0 gap
BC 1 00 0 align
00 0 00 0 gap
00 0 00 0 gap
00 0 00 0 gap
BC 1 00 0 align
00 0 00 0 gap
00 0 00 0 gap
00 0 00 0 gap
BC 1 00 0 align
00 0 00 0 gap
00 0 00 0 gap
00 0 00 0 gap
BC 1 00 0 align
00 0 00 0 gap
00 0 00 0 gap
00 0 00 0 gap