AEK_8220_Libraries/firmware_vhdl_evr320
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Amendment: removed 'evr_params.cs_timeout_cnt' assignment

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This parameter is a local enhancement and not present on the
master branch.

Also: two small changes which address GHDL issues.
This commit is contained in:
till straumann
2021-02-24 13:46:29 +01:00
parent 50860b9e20
commit badd801839
3 changed files with 7 additions and 4 deletions
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6
hdl/evr320_decoder.vhd
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@ -180,6 +180,7 @@ architecture behavioral of evr320_decoder is
signal mem_data_wren : std_logic := '0'; signal mem_data_wren : std_logic := '0';
signal mem_data_wr_addr : std_logic_vector(10 downto 0) := (others => '0'); signal mem_data_wr_addr : std_logic_vector(10 downto 0) := (others => '0');
signal mem_data_wr_byte : std_logic_vector( 7 downto 0) := (others => '0'); signal mem_data_wr_byte : std_logic_vector( 7 downto 0) := (others => '0');
signal mem_data : std_logic_vector(11+8-1 downto 0);
-- Data memory read -- Data memory read
signal mem_data_dpram : std_logic_vector(MEM_DATA_WIDTH - 1 downto 0) := (others => '0'); signal mem_data_dpram : std_logic_vector(MEM_DATA_WIDTH - 1 downto 0) := (others => '0');
signal mem_data_event0 : std_logic_vector(MEM_DATA_WIDTH - 1 downto 0) := (others => '0'); signal mem_data_event0 : std_logic_vector(MEM_DATA_WIDTH - 1 downto 0) := (others => '0');
@ -709,6 +710,9 @@ begin
mem_data_wr_addr <= frame_data_rd_addr; mem_data_wr_addr <= frame_data_rd_addr;
mem_data_wr_byte <= frame_data_rd_byte; mem_data_wr_byte <= frame_data_rd_byte;
-- concatenate - this avoids an internal error in ghdl v0.37!
mem_data <= mem_data_wr_addr & mem_data_wr_byte;
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- Address delay for read data mux -- Address delay for read data mux
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
@ -870,7 +874,7 @@ begin
OutRst => '0', OutRst => '0',
-- Input Data -- Input Data
InData => mem_data_wr_addr & mem_data_wr_byte, InData => mem_data,
InVld => mem_data_wren, InVld => mem_data_wren,
InRdy => open, InRdy => open,

4
hdl/evr320_tmem.vhd
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@ -110,8 +110,8 @@ architecture rtl of evr320_tmem is
signal lat_arm_edge : std_logic_vector(1 downto 0) := (others=>'0'); signal lat_arm_edge : std_logic_vector(1 downto 0) := (others=>'0');
-- event pulse config -- event pulse config
signal evr_puls_width_cfg_s : typ_arr_width :=((others => UsrEventWidthDefault_c)); signal evr_puls_width_cfg_s : typ_arr_width :=(others => UsrEventWidthDefault_c);
signal evr_puls_delay_cfg_s : typ_arr_delay :=((others => (others => '0'))); signal evr_puls_delay_cfg_s : typ_arr_delay :=(others => (others => '0'));
-- ---------------------------------------------------------------------------- -- ----------------------------------------------------------------------------
-- ---------------------------------------------------------------------------- -- ----------------------------------------------------------------------------

1
tb/evr320_decoder_tb.vhd
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@ -431,7 +431,6 @@ begin
event_recorder_ctrl.event_number <= std_logic_vector(to_unsigned(g_EVENT_NR_SOS, 8)); event_recorder_ctrl.event_number <= std_logic_vector(to_unsigned(g_EVENT_NR_SOS, 8));
evr_params.cs_min_cnt <= X"00000000"; evr_params.cs_min_cnt <= X"00000000";
evr_params.cs_min_time <= X"00000000"; evr_params.cs_min_time <= X"00000000";
evr_params.cs_timeout_cnt <= X"00000000";
mem_addr <= x"000"; mem_addr <= x"000";
await_value(rxlos, '0', 0 ns, 10 us, FAILURE, "wait for release RX LOS"); await_value(rxlos, '0', 0 ns, 10 us, FAILURE, "wait for release RX LOS");
--wait until (rxlos = '0'); --wait until (rxlos = '0');