AEK_8220_Libraries/firmware_vhdl_evr320
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FIX: event_decoder ports in tb updated. Added Event Flag check for data width = 64.

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This commit is contained in:
bucher_p1
2020-12-17 09:33:03 +01:00
parent 34b221f62a
commit 83b6d6562d
3 changed files with 70 additions and 48 deletions
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1
sim/config.tcl
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@ -64,7 +64,6 @@ add_sources $LibPath/Firmware/VHDL/evr320/hdl {
# EVR320 Decoder Testbench # EVR320 Decoder Testbench
add_sources $LibPath/Firmware/VHDL/evr320/tb { add_sources $LibPath/Firmware/VHDL/evr320/tb {
evr320_decoder_tb.vhd \ evr320_decoder_tb.vhd \
evr320_ifc1210_wrapper_tb.vhd \
} -tag evr320_tb } -tag evr320_tb
# EVR320 IFC1210 Wrapper Testbench # EVR320 IFC1210 Wrapper Testbench

115
tb/evr320_decoder_tb.vhd
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@ -80,7 +80,7 @@ architecture testbench of evr320_decoder_tb is
signal usr_clk : std_logic := '0'; signal usr_clk : std_logic := '0';
signal evr_params : typ_evr320_params; signal evr_params : typ_evr320_params;
signal mem_addr : std_logic_vector(11 downto 0) := (others => '0'); signal mem_addr : std_logic_vector(11 downto 0) := (others => '0');
signal mem_data : std_logic_vector(31 downto 0) := (others => '0'); signal mem_data : std_logic_vector(C_MEM_DATA_WIDTH-1 downto 0) := (others => '0');
-- Decoder stream -- Decoder stream
type dec_stream_type is record type dec_stream_type is record
@ -169,12 +169,14 @@ begin
-------------------------------------------------------------------------- --------------------------------------------------------------------------
o_usr_events => usr_events, o_usr_events => usr_events,
o_usr_events_ext => open, o_usr_events_ext => open,
o_sos_event => sos_event o_sos_event => sos_event,
o_event => open,
o_event_valid => open
); );
evr320_data_filter_inst: entity work.evr320_data_filter evr320_data_filter_inst: entity work.evr320_data_filter
generic map ( generic map (
SWAP => false SWAP => false,
NUM_BYTES => 8 NUM_BYTES => 8
) )
port map ( port map (
@ -399,7 +401,7 @@ begin
variable i : integer := 0; variable i : integer := 0;
type state is (idle, payload, frame_end, segment_nr); type state is (idle, payload, frame_end, segment_nr);
variable mem_base : integer range 0 to 127; variable mem_base : integer range 0 to 127;
variable segment_data_word : std_logic_vector(31 downto 0); variable segment_data_word : std_logic_vector(C_MEM_DATA_WIDTH-1 downto 0);
variable var_filter_offset : integer range 0 to 2047; variable var_filter_offset : integer range 0 to 2047;
variable var_filter_word : std_logic_vector(FILTER_NUM_BYTES*8-1 downto 0); variable var_filter_word : std_logic_vector(FILTER_NUM_BYTES*8-1 downto 0);
variable expected_evt_rec_events : integer range 0 to 255 := 0; variable expected_evt_rec_events : integer range 0 to 255 := 0;
@ -486,37 +488,56 @@ begin
log(ID_DATA, "Check expected Event Flags after SOS Event detected"); log(ID_DATA, "Check expected Event Flags after SOS Event detected");
---------------------------------------------------------------------- ----------------------------------------------------------------------
wait until rising_edge(usr_clk); wait until rising_edge(usr_clk);
for addr in 0 to 63 loop if (C_MEM_DATA_WIDTH = 32) then
mem_addr <= C_EVENT_REC_FLAGS & std_logic_vector(to_unsigned(addr, 6)); for addr in 0 to 63 loop
wait until rising_edge(usr_clk); mem_addr <= C_EVENT_REC_FLAGS & std_logic_vector(to_unsigned(addr, 6));
await_value(mem_data(0), all_expected_events(4*addr), 0 ns, 1 ns, ERROR, "Event " & to_string(4*addr) & " Flag"); wait_num_rising_edge_plus_margin(usr_clk, 1, 1 ns);
await_value(mem_data(8), all_expected_events(4*addr + 1), 0 ns, 1 ns, ERROR, "Event " & to_string(4*addr + 1) & " Flag");
await_value(mem_data(16), all_expected_events(4*addr + 2), 0 ns, 1 ns, ERROR, "Event " & to_string(4*addr + 2) & " Flag");
await_value(mem_data(24), all_expected_events(4*addr + 3), 0 ns, 1 ns, ERROR, "Event " & to_string(4*addr + 3) & " Flag");
end loop;
----------------------------------------------------------------------
log(ID_DATA, "Check Memory block border");
----------------------------------------------------------------------
-- read data mux switching made visible with delayed address.
mem_addr <= C_EVENT_REC_FLAGS & "000000";
wait until rising_edge(usr_clk);
wait for C_USRCLK_CYCLE/4;
for addr in 62 to 65 loop
mem_addr <= (C_EVENT_REC_FLAGS & "000000") + std_logic_vector(to_unsigned(addr, 7));
wait until rising_edge(usr_clk);
check_stable(mem_data, C_USRCLK_CYCLE, ERROR, "Read Data stable on Output");
wait for C_USRCLK_CYCLE/4;
if (addr < 64) then
check_value(mem_data(0), all_expected_events(4*addr), ERROR, "Event " & to_string(4*addr) & " Flag"); check_value(mem_data(0), all_expected_events(4*addr), ERROR, "Event " & to_string(4*addr) & " Flag");
check_value(mem_data(8), all_expected_events(4*addr + 1), ERROR, "Event " & to_string(4*addr + 1) & " Flag"); check_value(mem_data(8), all_expected_events(4*addr + 1), ERROR, "Event " & to_string(4*addr + 1) & " Flag");
check_value(mem_data(16), all_expected_events(4*addr + 2), ERROR, "Event " & to_string(4*addr + 2) & " Flag"); check_value(mem_data(16), all_expected_events(4*addr + 2), ERROR, "Event " & to_string(4*addr + 2) & " Flag");
check_value(mem_data(24), all_expected_events(4*addr + 3), ERROR, "Event " & to_string(4*addr + 3) & " Flag"); check_value(mem_data(24), all_expected_events(4*addr + 3), ERROR, "Event " & to_string(4*addr + 3) & " Flag");
else wait until rising_edge(usr_clk);
check_value(mem_data, X"0000_0000", ERROR, "After Event Recorder Mem Map"); end loop;
end if; elsif (C_MEM_DATA_WIDTH = 64) then
end loop; for addr in 0 to 31 loop
mem_addr <= '0' & C_EVENT_REC_FLAGS & std_logic_vector(to_unsigned(addr, 5));
wait_num_rising_edge_plus_margin(usr_clk, 1, 1 ns);
check_value(mem_data(0), all_expected_events(8*addr), ERROR, "Event " & to_string(8*addr) & " Flag");
check_value(mem_data(8), all_expected_events(8*addr + 1), ERROR, "Event " & to_string(8*addr + 1) & " Flag");
check_value(mem_data(16), all_expected_events(8*addr + 2), ERROR, "Event " & to_string(8*addr + 2) & " Flag");
check_value(mem_data(24), all_expected_events(8*addr + 3), ERROR, "Event " & to_string(8*addr + 3) & " Flag");
check_value(mem_data(32), all_expected_events(8*addr + 4), ERROR, "Event " & to_string(8*addr + 4) & " Flag");
check_value(mem_data(40), all_expected_events(8*addr + 5), ERROR, "Event " & to_string(8*addr + 5) & " Flag");
check_value(mem_data(48), all_expected_events(8*addr + 6), ERROR, "Event " & to_string(8*addr + 6) & " Flag");
check_value(mem_data(56), all_expected_events(8*addr + 7), ERROR, "Event " & to_string(8*addr + 7) & " Flag");
end loop;
else
error("Unsupported width of C_MEM_DATA_WIDTH");
end if;
-- ----------------------------------------------------------------------
-- log(ID_DATA, "Check Memory block border");
-- ----------------------------------------------------------------------
if (C_MEM_DATA_WIDTH = 32) then
-- read data mux switching made visible with delayed address.
mem_addr <= C_EVENT_REC_FLAGS & "000000";
wait until rising_edge(usr_clk);
wait for C_USRCLK_CYCLE/4;
for addr in 62 to 65 loop
mem_addr <= (C_EVENT_REC_FLAGS & "000000") + std_logic_vector(to_unsigned(addr, 7));
wait until rising_edge(usr_clk);
check_stable(mem_data, C_USRCLK_CYCLE, ERROR, "Read Data stable on Output");
wait for C_USRCLK_CYCLE/4;
if (addr < 64) then
check_value(mem_data(0), all_expected_events(4*addr), ERROR, "Event " & to_string(4*addr) & " Flag");
check_value(mem_data(8), all_expected_events(4*addr + 1), ERROR, "Event " & to_string(4*addr + 1) & " Flag");
check_value(mem_data(16), all_expected_events(4*addr + 2), ERROR, "Event " & to_string(4*addr + 2) & " Flag");
check_value(mem_data(24), all_expected_events(4*addr + 3), ERROR, "Event " & to_string(4*addr + 3) & " Flag");
else
check_value(mem_data, X"0000_0000", ERROR, "After Event Recorder Mem Map");
end if;
end loop;
end if;
---------------------------------------------------------------------- ----------------------------------------------------------------------
log(ID_DATA, "Check expected Event Recorder User Events"); log(ID_DATA, "Check expected Event Recorder User Events");
---------------------------------------------------------------------- ----------------------------------------------------------------------
@ -528,22 +549,24 @@ begin
-------------------------------------------------------------------------- --------------------------------------------------------------------------
log(ID_LOG_HDR, "Read DPRAM buffer", C_SCOPE); log(ID_LOG_HDR, "Read DPRAM buffer", C_SCOPE);
-------------------------------------------------------------------------- --------------------------------------------------------------------------
wait for 50 * C_USRCLK_CYCLE; if (C_MEM_DATA_WIDTH = 32) then
log(ID_DATA, "Read Segment from DPRAM"); wait for 50 * C_USRCLK_CYCLE;
-- print 16 words from dpram data buffer: log(ID_DATA, "Read Segment from DPRAM");
for offset in 0 to segment_length/4-1 loop -- print 16 words from dpram data buffer:
mem_base := to_integer(unsigned(segment_addr)); for offset in 0 to segment_length/4-1 loop
mem_addr <= std_logic_vector(to_unsigned(4*mem_base + offset , 12)); mem_base := to_integer(unsigned(segment_addr));
wait until rising_edge(usr_clk); mem_addr <= std_logic_vector(to_unsigned(4*mem_base + offset , 12));
wait until rising_edge(usr_clk); wait until rising_edge(usr_clk);
wait until rising_edge(usr_clk); wait until rising_edge(usr_clk);
segment_data_word := segment_data(offset*4+3) wait until rising_edge(usr_clk);
& segment_data(offset*4+2) segment_data_word := segment_data(offset*4+3)
& segment_data(offset*4+1) & segment_data(offset*4+2)
& segment_data(offset*4); & segment_data(offset*4+1)
check_value(mem_data, segment_data_word, ERROR, "Compare DPRAM with Sent Segment"); & segment_data(offset*4);
--log(ID_PACKET_DATA, "Data buffer DPRAM: addr=0x" & to_string(mem_addr, HEX) & " data=0x" & to_string(mem_data, HEX)); check_value(mem_data, segment_data_word, ERROR, "Compare DPRAM with Sent Segment");
end loop; --log(ID_PACKET_DATA, "Data buffer DPRAM: addr=0x" & to_string(mem_addr, HEX) & " data=0x" & to_string(mem_data, HEX));
end loop;
end if;
-------------------------------------------------------------------------- --------------------------------------------------------------------------
-- Test Done -- Test Done

2
tb/stimuli_mgt.dat
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@ -167,7 +167,7 @@ FE 0 00 0 event 254
FF 0 00 0 event 255 FF 0 00 0 event 255
BC 1 00 0 align BC 1 00 0 align
00 0 00 0 gap 00 0 00 0 gap
0F 0 00 0 gap 00 0 00 0 gap
00 0 00 0 gap 00 0 00 0 gap
BC 1 00 0 align BC 1 00 0 align
00 0 00 0 gap 00 0 00 0 gap