mirror of
https://github.com/paulscherrerinstitute/sf_daq_broker.git
synced 2026-05-14 06:25:35 +02:00
Dmitry Ozerov
75 lines
1.5 KiB
Plaintext
75 lines
1.5 KiB
Plaintext
detsize 1024 4608
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hostname JF4M5-01+JF4M5-02+JF4M5-03+JF4M5-04+JF4M5-05+JF4M5-06+JF4M5-07+JF4M5-08+JF4M5-09+
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#sf-daq-4
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udp_dstmac 9c:dc:71:4d:2a:b5
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udp_dstip 10.30.20.6
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#sf-daq-8
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#udp_dstmac b8:83:03:6e:de:9c
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#udp_dstip 10.30.20.9
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0:udp_dstport 50020
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0:udp_srcip 10.30.20.20
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0:udp_srcmac 00:aa:bb:cc:dd:30
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1:udp_dstport 50021
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1:udp_srcip 10.30.20.21
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1:udp_srcmac 00:aa:bb:cc:dd:31
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2:udp_dstport 50022
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2:udp_srcip 10.30.20.22
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2:udp_srcmac 00:aa:bb:cc:dd:32
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3:udp_dstport 50023
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3:udp_srcip 10.30.20.23
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3:udp_srcmac 00:aa:bb:cc:dd:33
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4:udp_dstport 50024
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4:udp_srcip 10.30.20.24
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4:udp_srcmac 00:aa:bb:cc:dd:34
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5:udp_dstport 50025
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5:udp_srcip 10.30.20.25
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5:udp_srcmac 00:aa:bb:cc:dd:35
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6:udp_dstport 50026
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6:udp_srcip 10.30.20.26
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6:udp_srcmac 00:aa:bb:cc:dd:36
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7:udp_dstport 50027
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7:udp_srcip 10.30.20.27
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7:udp_srcmac 00:aa:bb:cc:dd:37
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8:udp_dstport 50028
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8:udp_srcip 10.30.20.28
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8:udp_srcmac 00:aa:bb:cc:dd:38
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# use last two time slots (first 8 is occupied by 16M, but 4p5M will not be running together with full 16M yet). For 100Hz we can use 10 time slots.
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# for 40G link (currently bottleneck at daq machines) - 4 modules/slot. With 100G - 8 modules/time slot
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0:txndelay_frame 7
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1:txndelay_frame 7
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2:txndelay_frame 7
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3:txndelay_frame 7
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4:txndelay_frame 8
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5:txndelay_frame 8
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6:txndelay_frame 8
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7:txndelay_frame 8
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8:txndelay_frame 9
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triggers 10000
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frames 1
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timing trigger
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delay 0.001989
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#delay 1989us
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dac vb_comp 2220
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# DAQ comparator reset
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setbit 0x5d 4
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# Temperature
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temp_threshold 45
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temp_control 1
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# to clear event : temp_event 0
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