58 lines
2.0 KiB
C++
58 lines
2.0 KiB
C++
// SPDX-FileCopyrightText: 2024 Filip Leonarski, Paul Scherrer Institute <filip.leonarski@psi.ch>
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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#include "hls_jfjoch.h"
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void pixel_mask(STREAM_768 &data_in,
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STREAM_768 &data_out,
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const uint32_t pixel_mask[MAX_MODULES_FPGA*RAW_MODULE_SIZE/32],
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hls::stream<axis_completion > &s_axis_completion,
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hls::stream<axis_completion > &m_axis_completion) {
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#pragma HLS INTERFACE ap_ctrl_none port=return
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#pragma HLS INTERFACE register both axis port=data_in
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#pragma HLS INTERFACE register both axis port=data_out
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#pragma HLS INTERFACE register both axis port=m_axis_completion
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#pragma HLS INTERFACE register both axis port=s_axis_completion
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#pragma HLS INTERFACE mode=m_axi port=pixel_mask bundle=pixel_mask depth=65536 offset=off \
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max_read_burst_length=64 max_write_burst_length=2 latency=5 num_write_outstanding=1 num_read_outstanding=2
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packet_768_t packet;
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{
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#pragma HLS PROTOCOL fixed
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data_in >> packet;
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ap_wait();
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data_out << packet;
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ap_wait();
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}
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ap_uint<32> data_collection_mode = ACT_REG_MODE(packet.data);
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ap_uint<1> apply_mask = ((data_collection_mode & MODE_APPLY_PIXEL_MASK) ? 1 : 0);
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axis_completion cmpl;
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s_axis_completion >> cmpl;
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while (!cmpl.last) {
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m_axis_completion << cmpl;
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for (int i = 0; i < RAW_MODULE_SIZE * sizeof(uint16_t) / 64; i++) {
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#pragma HLS PIPELINE II=1
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data_in >> packet;
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ap_uint<32> mask = pixel_mask[(cmpl.module * RAW_MODULE_SIZE / 32) + i];
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ap_int<24> in_val[32];
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unpack32(packet.data, in_val);
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for (int j = 0; j < 32 ; j++) {
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if (apply_mask && mask[j])
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in_val[j] = INT24_MIN;
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}
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packet.strb = ~mask;
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packet.data = pack32(in_val);
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data_out << packet;
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}
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s_axis_completion >> cmpl;
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}
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m_axis_completion << cmpl;
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data_in >> packet;
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data_out << packet;
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} |