FPGA data flow

The following steps are performed on FPGA (in the order of operation):

UDP header decoding
SLS detector header decoding
State machine that controls data acquisition (start/stop/cancel)
High-bandwidth memory cache to buffer network packets and reorder them to form full modules
ADU histogram for JUNGFRAU
Mask pixels from missing packets with special value
Reorder lines for EIGER to form a proper module
Mask pixels based on provided pixel mask
JUNGFRAU conversion with gain and pedestal corrections
Threshold to zero pixels below certain count value
Integration according to predefined map (e.g., 1D azimuthal integration)
Spot finding
ROI calculation
Image lossy compression using N*sqrt(pixel) values
Send images, analysis results and metadata to host memory via PCI Express

Each step has dedicated core, written in the high-level synthesis. Exact operation of cores for data analysis is explained in dedicated document.