247 lines
7.6 KiB
C++
247 lines
7.6 KiB
C++
// Copyright (2019-2023) Paul Scherrer Institute
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#include <iostream>
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#include <catch2/catch.hpp>
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#include "../fpga/hls/hls_jfjoch.h"
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#include "../fpga/hls/spot_finder.h"
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TEST_CASE("Pack32_Unpack32","[FPGA][SpotFinder]") {
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ap_int<16> value[32];
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for (int i = 0; i < 32; i++)
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value[i] = i;
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ap_int<512> packed = pack32(value);
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ap_int<16> restore[32];
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unpack32(packed, restore);
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for (int i = 0; i < 32; i++) {
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REQUIRE(value[i] == restore[i]);
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}
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}
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TEST_CASE("Pack32_Unpack32_36","[FPGA][SpotFinder]") {
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ap_int<36> value[32];
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for (int i = 0; i < 32; i++)
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value[i] = i;
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ap_int<36*32> packed = pack32(value);
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ap_int<36> restore[32];
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unpack32(packed, restore);
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for (int i = 0; i < 32; i++) {
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REQUIRE(value[i] == restore[i]);
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}
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}
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TEST_CASE("FPGA_calc_sum","[FPGA][SpotFinder]") {
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ap_int<16> old_value[32];
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ap_int<16> new_value[32];
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ap_int<SUM_BITWIDTH> new_sum[32];
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ap_int<SUM2_BITWIDTH> new_sum2[32];
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for (int i = 0; i < 32; i++) {
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old_value[i] = i;
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new_value[i] = 2;
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}
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ap_uint<SUM_BITWIDTH*32> diff_sum;
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ap_uint<SUM2_BITWIDTH*32> diff_sum2;
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calc_sum(diff_sum, pack32(old_value), pack32(new_value));
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calc_sum2(diff_sum2, pack32(old_value), pack32(new_value));
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unpack32(diff_sum, new_sum);
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unpack32(diff_sum2, new_sum2);
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for (int i = 0; i < 32; i++) {
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REQUIRE(new_sum[i] == 2-i);
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REQUIRE(new_sum2[i] == 4-i*i);
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}
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}
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TEST_CASE("FPGA_calc_valid","[FPGA][SpotFinder]") {
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ap_uint<32> old_mask = UINT32_MAX;
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ap_uint<32> new_mask = UINT32_MAX;
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old_mask[15] = 0;
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new_mask[13] = 0;
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ap_uint<MASK_SUM_BITWIDTH*32> diff_mask;
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calc_mask_diff(diff_mask, old_mask, new_mask);
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ap_int<MASK_SUM_BITWIDTH> diff_mask_32[32];
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unpack32(diff_mask, diff_mask_32);
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REQUIRE(diff_mask_32[0] == 0);
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REQUIRE(diff_mask_32[1] == 0);
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REQUIRE(diff_mask_32[13] == -1);
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REQUIRE(diff_mask_32[15] == 1);
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}
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TEST_CASE("FPGA_calc_mask","[FPGA][SpotFinder]") {
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ap_int<16> value_in[32], value_out[32];
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for (int i = 0; i < 32; i++)
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value_in[i] = 154 + i;
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value_in[15] = INT16_MAX;
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value_in[0] = INT16_MIN;
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value_in[1] = INT16_MIN + 1;
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value_in[2] = INT16_MAX - 1;
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ap_uint<512> input = pack32(value_in);
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ap_uint<512> output = 0;
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ap_uint<32> mask = 0;
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calc_mask(input, output, mask);
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REQUIRE(mask[0] == 0);
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REQUIRE(mask[15] == 0);
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REQUIRE(mask[1] == 1);
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REQUIRE(mask[2] == 1);
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REQUIRE(mask[3] == 1);
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REQUIRE(mask[4] == 1);
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unpack32(output, value_out);
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REQUIRE(value_out[0] == 0);
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REQUIRE(value_out[15] == 0);
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REQUIRE(value_out[1] == value_in[1]);
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REQUIRE(value_out[2] == value_in[2]);
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REQUIRE(value_out[3] == value_in[3]);
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REQUIRE(value_out[4] == value_in[4]);
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}
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TEST_CASE("FPGA_update_sum" , "[FPGA][SpotFinder]") {
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ap_int<SUM2_BITWIDTH> arr_val1[32], arr_val2[32], arr_out[32];
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for (int i = 0; i < 32; i++) {
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arr_val1[i] = 5 * i;
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arr_val2[i] = 3 * i + 2;
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}
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ap_uint<SUM2_BITWIDTH*32> val1 = pack32(arr_val1);
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ap_uint<SUM2_BITWIDTH*32> val2 = pack32(arr_val2);
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update_sum<SUM2_BITWIDTH>(val1, val2);
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unpack32(val1, arr_out);
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for (int i = 0; i < 32; i++)
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REQUIRE(arr_out[i] == 8 * i + 2);
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}
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bool Isigma_cpu(double val, double sum, double sum2, float threshold) {
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double mean = sum / ((2*FPGA_NBX+1) * (2*FPGA_NBX+1));
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double mean2 = sum2 / ((2*FPGA_NBX+1) * (2*FPGA_NBX+1));
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double variance = mean2 - mean * mean;
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double sigma = sqrt(variance);
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double i_over_sigma = (val - mean) / sigma;
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return (i_over_sigma > threshold);
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}
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bool Isigma_fpga(ap_int<16> val, ap_int<SUM_BITWIDTH> sum, ap_uint<SUM2_BITWIDTH> sum2, float threshold) {
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return check_threshold(val, sum, sum2, fpga_strong_pixel_threshold(threshold), -1);
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}
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TEST_CASE("FPGA_spot_check_threshold","[FPGA][SpotFinder]") {
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std::vector<float> threshold_values = {1.0, 3.0, 6.0};
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for (auto threshold: threshold_values) {
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uint32_t uniform_val = 10;
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uint32_t diff = 0;
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for (int16_t val = -100; val < INT16_MAX; val++) {
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uint32_t sum = val + ((2 * FPGA_NBX + 1) * (2 * FPGA_NBX + 1) - 1) * uniform_val;
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uint32_t sum2 = val * val + ((2 * FPGA_NBX + 1) * (2 * FPGA_NBX + 1) - 1) * uniform_val * uniform_val;
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bool cpu = Isigma_cpu(val, sum, sum2, threshold);
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bool fpga = Isigma_fpga(val, sum, sum2, threshold);
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if (cpu != fpga) {
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std::cout << "WRONG!!! " << threshold << " " << val << " " << sum << " " << sum2 << " CPU: " << cpu << " FPGA: " << fpga << std::endl;
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diff++;
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}
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}
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REQUIRE(diff == 0);
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}
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}
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TEST_CASE("FPGA_spot_finder_update_sum","[FPGA][SpotFinder]") {
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STREAM_512 input;
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STREAM_512 output;
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hls::stream<ap_uint<(SUM_BITWIDTH*32)>> sum_out;
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hls::stream<ap_uint<SUM2_BITWIDTH*32>> sum2_out;
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hls::stream<ap_uint<MASK_SUM_BITWIDTH*32>> valid_out;
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std::vector<int16_t> input_frame(RAW_MODULE_SIZE);
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for (int i = 0; i < RAW_MODULE_SIZE; i++) {
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if (i % RAW_MODULE_COLS == 1023)
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input_frame[i] = INT16_MIN;
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else
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input_frame[i] = i % RAW_MODULE_COLS;
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}
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auto input_frame_512 = (ap_uint<512> *) input_frame.data();
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input << packet_512_t{.user = 0};
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for (int i = 0; i < RAW_MODULE_SIZE * sizeof(uint16_t) / 64; i++)
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input << packet_512_t{.data = input_frame_512[i], .user = 0};
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input << packet_512_t{.user = 1};
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spot_finder_update_sum(input, output, sum_out, sum2_out, valid_out);
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REQUIRE(input.size() == 0);
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REQUIRE(output.size() == RAW_MODULE_SIZE * sizeof(uint16_t) / 64 + 2);
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REQUIRE(sum_out.size() == RAW_MODULE_SIZE * sizeof(uint16_t) / 64);
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REQUIRE(sum2_out.size() == RAW_MODULE_SIZE * sizeof(uint16_t) / 64);
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REQUIRE(valid_out.size() == RAW_MODULE_SIZE * sizeof(uint16_t) / 64);
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std::vector<int64_t> sum(RAW_MODULE_SIZE);
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std::vector<int64_t> sum2(RAW_MODULE_SIZE);
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std::vector<int64_t> valid(RAW_MODULE_SIZE);
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for (int i = 0; i < RAW_MODULE_SIZE * sizeof(uint16_t) / 64; i++) {
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ap_uint<32 * SUM_BITWIDTH> tmp_sum;
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ap_uint<32 * SUM2_BITWIDTH> tmp_sum2;
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ap_uint<32 * MASK_SUM_BITWIDTH> tmp_valid;
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sum_out >> tmp_sum;
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sum2_out >> tmp_sum2;
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valid_out >> tmp_valid;
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ap_uint<SUM_BITWIDTH> tmp_sum_unpacked[32];
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ap_uint<SUM2_BITWIDTH> tmp_sum2_unpacked[32];
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ap_uint<MASK_SUM_BITWIDTH> tmp_valid_unpacked[32];
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unpack32(tmp_sum, tmp_sum_unpacked);
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unpack32(tmp_sum2, tmp_sum2_unpacked);
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unpack32(tmp_valid, tmp_valid_unpacked);
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for (int j = 0; j < 32; j++) {
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sum[i * 32 + j] = tmp_sum_unpacked[j];
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sum2[i * 32 + j] = tmp_sum2_unpacked[j];
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valid[i * 32 + j] = tmp_valid_unpacked[j];
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}
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}
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CHECK(sum[1] == (FPGA_NBX+1) * 1);
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CHECK(sum[3] == (FPGA_NBX+1) * 3);
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CHECK(sum[1023] == 0);
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CHECK(sum[1022+200*1024] == (2 * FPGA_NBX+1) * 1022);
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CHECK(sum2[3] == (FPGA_NBX+1) * 3 * 3);
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CHECK(sum2[1023] == 0);
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CHECK(sum2[1022+200*1024] == (2 * FPGA_NBX+1) * 1022 * 1022);
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CHECK(valid[1] == FPGA_NBX + 1);
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CHECK(valid[3] == FPGA_NBX + 1);
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CHECK(valid[1023] == 0);
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CHECK(valid[1023 + 323*1024] == 0);
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CHECK(valid[1+1024] == FPGA_NBX + 1 + 1);
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CHECK(valid[1+1024] == FPGA_NBX + 1 + 1);
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CHECK(valid[1+3*1024] == FPGA_NBX + 1 + 3);
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CHECK(valid[1+200*1024] == 2 * FPGA_NBX + 1);
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CHECK(valid[1+509*1024] == FPGA_NBX + 1 + 2);
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CHECK(valid[1+510*1024] == FPGA_NBX + 1 + 1);
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CHECK(valid[1+511*1024] == FPGA_NBX + 1);
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}
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