Filip Leonarski c330a0ed81 CI: FPGA images are called jfjoch_fpga_{FLOW}.mcs

2024-05-07 14:43:30 +02:00

..

bd_pcie_8x10g.tcl

* Enhancements for XFEL

2024-03-05 20:41:47 +01:00

bd_pcie.tcl

* Enhancements for XFEL

2024-03-05 20:41:47 +01:00

build_pcie_design_8x10g.tcl

* Enhancements for XFEL

2024-03-05 20:41:47 +01:00

build_pcie_design.tcl

Fix spot finding + fix FPGA network LEDs behavior

2023-12-16 09:20:46 +01:00

check_hls.sh

FPGA: Split receiver and FPGA design directories

2023-06-07 21:21:22 +02:00

hbm_cache.tcl

* Enhancements for XFEL

2024-03-05 20:41:47 +01:00

hbm_u55c.tcl

* Enhancements for XFEL

2024-03-05 20:41:47 +01:00

image_processing.tcl

File writer and spot finding improvements

2024-04-08 11:18:50 +02:00

jfjoch.tcl

* Enhancements for XFEL

2024-03-05 20:41:47 +01:00

mac_4x10g.tcl

Modifications in preparation to MAX IV experiment

2024-01-27 21:23:56 +01:00

mac_100g_pcie.tcl

Updates March 2023

2024-03-14 20:26:03 +01:00

network_stack.tcl

* Enhancements for XFEL

2024-03-05 20:41:47 +01:00

pcie_dma.tcl

Extend FPGA functionality

2023-12-09 12:08:39 +01:00

setup_action.sh

Improvements in building Jungfraujoch

2024-05-06 21:28:55 +02:00

synth_and_impl.tcl

CI: FPGA images are called jfjoch_fpga_{FLOW}.mcs

2024-05-07 14:43:30 +02:00

synth_hls_function.tcl

* Enhancements for XFEL

2024-03-05 20:41:47 +01:00