198 lines
10 KiB
Tcl
198 lines
10 KiB
Tcl
## Copyright (2019-2023) Paul Scherrer Institute
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# Hierarchical cell: mac_100g
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proc create_hier_cell_mac_100g { parentCell nameHier } {
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variable script_folder
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if { $parentCell eq "" || $nameHier eq "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_mac_100g() - Empty argument(s)!"}
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return
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}
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# Get object for parentCell
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set parentObj [get_bd_cells $parentCell]
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if { $parentObj == "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
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return
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}
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# Make sure parentObj is hier blk
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set parentType [get_property TYPE $parentObj]
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if { $parentType ne "hier" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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return
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}
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# Save current instance; Restore later
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set oldCurInst [current_bd_instance .]
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# Set parent object as current
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current_bd_instance $parentObj
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# Create cell and set as current instance
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set hier_obj [create_bd_cell -type hier $nameHier]
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current_bd_instance $hier_obj
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# Create interface pins
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create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_eth_in
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create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp
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create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 qsfp_ref
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create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi
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create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_eth_out
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# Create pins
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create_bd_pin -dir I -type rst ap_rst_n
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create_bd_pin -dir I -type clk axiclk
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create_bd_pin -dir O eth_busy_n
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create_bd_pin -dir I -type clk refclk100
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create_bd_pin -dir I -type rst resetn
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create_bd_pin -dir O stat_rx_aligned_n
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# Create instance: axis_data_fifo_rx_0, and set properties
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set axis_data_fifo_rx_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_rx_0 ]
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set_property -dict [ list \
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CONFIG.FIFO_DEPTH {256} \
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CONFIG.IS_ACLK_ASYNC {1} \
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] $axis_data_fifo_rx_0
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# Create instance: axis_data_fifo_rx_1, and set properties
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set axis_data_fifo_rx_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_rx_1 ]
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set_property -dict [ list \
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CONFIG.FIFO_DEPTH {16384} \
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CONFIG.FIFO_MEMORY_TYPE {ultra} \
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CONFIG.ENABLE_ECC {1} \
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] $axis_data_fifo_rx_1
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# Create instance: axis_data_fifo_tx, and set properties
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set axis_data_fifo_tx [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_tx ]
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set_property -dict [ list \
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CONFIG.FIFO_DEPTH {128} \
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CONFIG.FIFO_MODE {2} \
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CONFIG.IS_ACLK_ASYNC {1} \
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] $axis_data_fifo_tx
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# Create instance: axis_register_slice_rx_0, and set properties
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set axis_register_slice_rx_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_rx_0 ]
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set_property -dict [ list \
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CONFIG.REG_CONFIG {16} \
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] $axis_register_slice_rx_0
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# Create instance: axis_register_slice_rx_1, and set properties
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set axis_register_slice_rx_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_rx_1 ]
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set_property -dict [ list \
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CONFIG.REG_CONFIG {16} \
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] $axis_register_slice_rx_1
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# Create instance: axis_register_slice_tx, and set properties
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set axis_register_slice_tx [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_tx ]
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set_property -dict [ list \
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CONFIG.REG_CONFIG {16} \
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] $axis_register_slice_tx
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# Create instance: check_eth_busy_0, and set properties
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set block_name check_eth_busy
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set block_cell_name check_eth_busy_0
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if { [catch {set check_eth_busy_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
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return 1
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} elseif { $check_eth_busy_0 eq "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
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return 1
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}
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# Create instance: cmac_usplus_0, and set properties
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set cmac_usplus_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cmac_usplus:3.1 cmac_usplus_0 ]
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set_property -dict [ list \
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CONFIG.CMAC_CAUI4_MODE {1} \
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CONFIG.CMAC_CORE_SELECT {CMACE4_X0Y3} \
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CONFIG.ENABLE_AXI_INTERFACE {1} \
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CONFIG.ENABLE_PIPELINE_REG {1} \
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CONFIG.GT_DRP_CLK {100.00} \
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CONFIG.GT_GROUP_SELECT {X0Y24~X0Y27} \
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CONFIG.GT_REF_CLK_FREQ {161.1328125} \
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CONFIG.INCLUDE_RS_FEC {1} \
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CONFIG.INCLUDE_STATISTICS_COUNTERS {1} \
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CONFIG.NUM_LANES {4x25} \
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CONFIG.RX_EQ_MODE {AUTO} \
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CONFIG.RX_FLOW_CONTROL {0} \
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CONFIG.TX_FLOW_CONTROL {0} \
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CONFIG.USER_INTERFACE {AXIS} \
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] $cmac_usplus_0
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# Create instance: util_vector_logic_0, and set properties
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set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ]
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set_property -dict [ list \
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CONFIG.C_OPERATION {not} \
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CONFIG.C_SIZE {1} \
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CONFIG.LOGO_FILE {data/sym_notgate.png} \
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] $util_vector_logic_0
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# Create instance: util_vector_logic_1, and set properties
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set util_vector_logic_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_1 ]
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set_property -dict [ list \
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CONFIG.C_OPERATION {not} \
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CONFIG.C_SIZE {1} \
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CONFIG.LOGO_FILE {data/sym_notgate.png} \
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] $util_vector_logic_1
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# Create instance: util_vector_logic_2, and set properties
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set util_vector_logic_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_2 ]
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set_property -dict [ list \
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CONFIG.C_OPERATION {not} \
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CONFIG.C_SIZE {1} \
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CONFIG.LOGO_FILE {data/sym_notgate.png} \
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] $util_vector_logic_2
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# Create instance: util_vector_logic_3, and set properties
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set util_vector_logic_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_3 ]
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set_property -dict [ list \
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CONFIG.C_OPERATION {not} \
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CONFIG.C_SIZE {1} \
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CONFIG.LOGO_FILE {data/sym_notgate.png} \
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] $util_vector_logic_3
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# Create instance: zero_0, and set properties
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set zero_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 zero_0 ]
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set_property -dict [ list \
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CONFIG.CONST_VAL {0} \
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] $zero_0
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# Create interface connections
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connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins qsfp] [get_bd_intf_pins cmac_usplus_0/gt_serial_port]
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connect_bd_intf_net -intf_net axis_data_fifo_rx_0_M_AXIS [get_bd_intf_pins axis_data_fifo_rx_0/M_AXIS] [get_bd_intf_pins axis_register_slice_rx_0/S_AXIS]
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connect_bd_intf_net -intf_net axis_data_fifo_rx_1_M_AXIS [get_bd_intf_pins axis_data_fifo_rx_1/M_AXIS] [get_bd_intf_pins axis_register_slice_rx_1/S_AXIS]
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connect_bd_intf_net -intf_net axis_data_fifo_tx_M_AXIS [get_bd_intf_pins axis_data_fifo_tx/M_AXIS] [get_bd_intf_pins cmac_usplus_0/axis_tx]
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connect_bd_intf_net -intf_net axis_register_slice_rx_0_M_AXIS [get_bd_intf_pins axis_data_fifo_rx_1/S_AXIS] [get_bd_intf_pins axis_register_slice_rx_0/M_AXIS]
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connect_bd_intf_net -intf_net axis_register_slice_rx_1_M_AXIS [get_bd_intf_pins m_axis_eth_in] [get_bd_intf_pins axis_register_slice_rx_1/M_AXIS]
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connect_bd_intf_net -intf_net axis_register_slice_tx_M_AXIS [get_bd_intf_pins axis_data_fifo_tx/S_AXIS] [get_bd_intf_pins axis_register_slice_tx/M_AXIS]
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connect_bd_intf_net -intf_net check_eth_busy_0_M_AXIS [get_bd_intf_pins axis_data_fifo_rx_0/S_AXIS] [get_bd_intf_pins check_eth_busy_0/M_AXIS]
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connect_bd_intf_net -intf_net cmac_usplus_0_axis_rx [get_bd_intf_pins check_eth_busy_0/S_AXIS] [get_bd_intf_pins cmac_usplus_0/axis_rx]
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connect_bd_intf_net -intf_net gt_ref_clk_0_1 [get_bd_intf_pins qsfp_ref] [get_bd_intf_pins cmac_usplus_0/gt_ref_clk]
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connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins cmac_usplus_0/s_axi]
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connect_bd_intf_net -intf_net s_axis_eth_out_1 [get_bd_intf_pins s_axis_eth_out] [get_bd_intf_pins axis_register_slice_tx/S_AXIS]
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# Create port connections
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connect_bd_net -net ap_rst_n_1 [get_bd_pins ap_rst_n] [get_bd_pins util_vector_logic_0/Op1]
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connect_bd_net -net axi_clk_net [get_bd_pins axiclk] [get_bd_pins axis_data_fifo_rx_0/m_axis_aclk] [get_bd_pins axis_data_fifo_rx_1/s_axis_aclk] [get_bd_pins axis_data_fifo_tx/s_axis_aclk] [get_bd_pins axis_register_slice_rx_0/aclk] [get_bd_pins axis_register_slice_rx_1/aclk] [get_bd_pins axis_register_slice_tx/aclk]
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connect_bd_net -net check_eth_busy_0_eth_busy [get_bd_pins check_eth_busy_0/eth_busy] [get_bd_pins util_vector_logic_3/Op1]
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connect_bd_net -net cmac_usplus_0_gt_txusrclk2 [get_bd_pins axis_data_fifo_rx_0/s_axis_aclk] [get_bd_pins axis_data_fifo_tx/m_axis_aclk] [get_bd_pins check_eth_busy_0/clk] [get_bd_pins cmac_usplus_0/gt_txusrclk2] [get_bd_pins cmac_usplus_0/rx_clk]
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connect_bd_net -net cmac_usplus_0_stat_rx_aligned [get_bd_pins cmac_usplus_0/stat_rx_aligned] [get_bd_pins util_vector_logic_2/Op1]
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connect_bd_net -net cmac_usplus_0_usr_rx_reset [get_bd_pins cmac_usplus_0/usr_rx_reset] [get_bd_pins util_vector_logic_1/Op1]
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connect_bd_net -net init_clk_1 [get_bd_pins refclk100] [get_bd_pins cmac_usplus_0/init_clk] [get_bd_pins cmac_usplus_0/s_axi_aclk]
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connect_bd_net -net resetn_1 [get_bd_pins resetn] [get_bd_pins axis_data_fifo_rx_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_tx/s_axis_aresetn] [get_bd_pins axis_register_slice_rx_0/aresetn] [get_bd_pins axis_register_slice_rx_1/aresetn] [get_bd_pins axis_register_slice_tx/aresetn]
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connect_bd_net -net util_vector_logic_0_Res [get_bd_pins cmac_usplus_0/s_axi_sreset] [get_bd_pins cmac_usplus_0/sys_reset] [get_bd_pins util_vector_logic_0/Res]
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connect_bd_net -net util_vector_logic_1_Res [get_bd_pins axis_data_fifo_rx_0/s_axis_aresetn] [get_bd_pins util_vector_logic_1/Res]
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connect_bd_net -net util_vector_logic_2_Res [get_bd_pins stat_rx_aligned_n] [get_bd_pins util_vector_logic_2/Res]
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connect_bd_net -net util_vector_logic_3_Res [get_bd_pins eth_busy_n] [get_bd_pins util_vector_logic_3/Res]
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connect_bd_net -net zero_0_dout [get_bd_pins cmac_usplus_0/core_drp_reset] [get_bd_pins cmac_usplus_0/core_rx_reset] [get_bd_pins cmac_usplus_0/core_tx_reset] [get_bd_pins cmac_usplus_0/drp_clk] [get_bd_pins zero_0/dout]
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# Restore current instance
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current_bd_instance $oldCurInst
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}
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