483 lines
26 KiB
Tcl
483 lines
26 KiB
Tcl
## Copyright (2019-2023) Paul Scherrer Institute
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################################################################
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# This is a generated script based on design: jfjoch_pcie
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#
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# Though there are limitations about the generated script,
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# the main purpose of this utility is to make learning
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# IP Integrator Tcl commands easier.
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################################################################
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namespace eval _tcl {
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proc get_script_folder {} {
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set script_path [file normalize [info script]]
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set script_folder [file dirname $script_path]
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return $script_folder
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}
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}
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variable script_folder
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set script_folder [_tcl::get_script_folder]
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################################################################
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# Check if script is running in correct Vivado version.
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################################################################
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set scripts_vivado_version 2022.1
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set current_vivado_version [version -short]
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if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
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puts ""
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catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
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return 1
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}
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################################################################
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# START
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################################################################
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# To test this script, run the following commands from Vivado Tcl console:
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# source jfjoch_pcie_script.tcl
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# The design that will be created by this Tcl script contains the following
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# module references:
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# gen_xdma_descriptor, action_config, check_eth_busy, resetn_sync
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# Please add the sources of those modules before sourcing this Tcl script.
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# If there is no project opened, this script will create a
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# project, but make sure you do not have an existing project
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# <./myproj/project_1.xpr> in the current working folder.
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set list_projs [get_projects -quiet]
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if { $list_projs eq "" } {
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create_project project_1 myproj -part xcvu35p-fsvh2104-2-e
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}
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# CHANGE DESIGN NAME HERE
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variable design_name
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set design_name jfjoch_pcie
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# If you do not already have an existing IP Integrator design open,
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# you can create a design using the following command:
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# create_bd_design $design_name
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# Creating design if needed
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set errMsg ""
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set nRet 0
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set cur_design [current_bd_design -quiet]
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set list_cells [get_bd_cells -quiet]
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if { ${design_name} eq "" } {
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# USE CASES:
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# 1) Design_name not set
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set errMsg "Please set the variable <design_name> to a non-empty value."
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set nRet 1
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} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
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# USE CASES:
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# 2): Current design opened AND is empty AND names same.
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# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
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# 4): Current design opened AND is empty AND names diff; design_name exists in project.
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if { $cur_design ne $design_name } {
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common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
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set design_name [get_property NAME $cur_design]
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}
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common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
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} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
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# USE CASES:
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# 5) Current design opened AND has components AND same names.
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set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
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set nRet 1
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} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
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# USE CASES:
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# 6) Current opened design, has components, but diff names, design_name exists in project.
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# 7) No opened design, design_name exists in project.
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set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
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set nRet 2
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} else {
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# USE CASES:
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# 8) No opened design, design_name not in project.
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# 9) Current opened design, has components, but diff names, design_name not in project.
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common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
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create_bd_design $design_name
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common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
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current_bd_design $design_name
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}
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common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
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if { $nRet != 0 } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
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return $nRet
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}
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set bCheckIPsPassed 1
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##################################################################
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# CHECK IPs
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##################################################################
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set bCheckIPs 1
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if { $bCheckIPs == 1 } {
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set list_check_ips "\
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xilinx.com:ip:axi_intc:4.1\
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xilinx.com:ip:axi_quad_spi:3.2\
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xilinx.com:ip:clk_wiz:6.0\
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xilinx.com:ip:cms_subsystem:4.0\
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xilinx.com:ip:xlconstant:1.1\
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xilinx.com:ip:proc_sys_reset:5.0\
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xilinx.com:ip:smartconnect:1.0\
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xilinx.com:ip:xlconcat:2.1\
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xilinx.com:ip:axi_protocol_converter:2.1\
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xilinx.com:ip:axi_register_slice:2.1\
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xilinx.com:ip:hbm:1.0\
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xilinx.com:ip:util_vector_logic:2.0\
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psi.ch:hls:adu_histo:1.0\
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xilinx.com:ip:axi_datamover:5.1\
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psi.ch:hls:axis_128_to_512:1.0\
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xilinx.com:ip:axis_data_fifo:2.0\
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psi.ch:hls:axis_broadcast:1.0\
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xilinx.com:ip:axis_register_slice:1.1\
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psi.ch:hls:data_collection_fsm:1.0\
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psi.ch:hls:frame_generator:1.0\
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psi.ch:hls:host_writer:1.0\
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psi.ch:hls:integration:1.0\
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psi.ch:hls:jf_conversion:1.0\
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psi.ch:hls:load_calibration:1.0\
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psi.ch:hls:load_from_hbm:1.0\
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xilinx.com:ip:mailbox:2.1\
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psi.ch:hls:mask_missing:1.0\
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psi.ch:hls:save_to_hbm:1.0\
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psi.ch:hls:spot_finder:1.0\
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psi.ch:hls:stream_merge:1.0\
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psi.ch:hls:timer_host:1.0\
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xilinx.com:ip:cmac_usplus:3.1\
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xilinx.com:ip:axi_firewall:1.2\
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xilinx.com:ip:axis_clock_converter:1.1\
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xilinx.com:ip:util_ds_buf:2.2\
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xilinx.com:ip:xdma:4.1\
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psi.ch:hls:arp:1.0\
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xilinx.com:ip:axis_switch:1.1\
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psi.ch:hls:ethernet:1.0\
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psi.ch:hls:icmp:1.0\
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psi.ch:hls:ipv4:1.0\
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psi.ch:hls:sls_detector:1.0\
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psi.ch:hls:udp:1.0\
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"
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set list_ips_missing ""
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common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
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foreach ip_vlnv $list_check_ips {
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set ip_obj [get_ipdefs -all $ip_vlnv]
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if { $ip_obj eq "" } {
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lappend list_ips_missing $ip_vlnv
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}
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}
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if { $list_ips_missing ne "" } {
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catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
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set bCheckIPsPassed 0
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}
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}
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##################################################################
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# CHECK Modules
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##################################################################
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set bCheckModules 1
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if { $bCheckModules == 1 } {
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set list_check_mods "\
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gen_xdma_descriptor\
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action_config\
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check_eth_busy\
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resetn_sync\
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"
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set list_mods_missing ""
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common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
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foreach mod_vlnv $list_check_mods {
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if { [can_resolve_reference $mod_vlnv] == 0 } {
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lappend list_mods_missing $mod_vlnv
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}
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}
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if { $list_mods_missing ne "" } {
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catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
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common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above."
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set bCheckIPsPassed 0
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}
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}
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if { $bCheckIPsPassed != 1 } {
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common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
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return 3
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}
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##################################################################
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# DESIGN PROCs
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##################################################################
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# Procedure to create entire design; Provide argument to make
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# procedure reusable. If parentCell is "", will use root.
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proc create_root_design { parentCell } {
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variable script_folder
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variable design_name
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if { $parentCell eq "" } {
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set parentCell [get_bd_cells /]
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}
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# Get object for parentCell
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set parentObj [get_bd_cells $parentCell]
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if { $parentObj == "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
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return
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}
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# Make sure parentObj is hier blk
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set parentType [get_property TYPE $parentObj]
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if { $parentType ne "hier" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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return
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}
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# Save current instance; Restore later
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set oldCurInst [current_bd_instance .]
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# Set parent object as current
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current_bd_instance $parentObj
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# Create interface ports
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set pcie0_mgt [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pcie0_mgt ]
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set pcie0_ref [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 pcie0_ref ]
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set qsfp0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp0 ]
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set qsfp0_ref [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 qsfp0_ref ]
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set_property -dict [ list \
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CONFIG.FREQ_HZ {161132812} \
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] $qsfp0_ref
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set ref100 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 ref100 ]
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set_property -dict [ list \
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CONFIG.FREQ_HZ {100000000} \
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] $ref100
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set satellite_uart_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 satellite_uart_0 ]
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# Create ports
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set hbm_cattrip [ create_bd_port -dir O -from 0 -to 0 hbm_cattrip ]
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set pcie_perstn [ create_bd_port -dir I -type rst pcie_perstn ]
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set qsfp0_led_busy [ create_bd_port -dir O -from 0 -to 0 qsfp0_led_busy ]
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set qsfp0_led_conn [ create_bd_port -dir O -from 0 -to 0 qsfp0_led_conn ]
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set satellite_gpio_0 [ create_bd_port -dir I -from 3 -to 0 -type intr satellite_gpio_0 ]
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set_property -dict [ list \
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CONFIG.PortWidth {4} \
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CONFIG.SENSITIVITY {EDGE_RISING} \
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] $satellite_gpio_0
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# Create instance: axi_intc_0, and set properties
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set axi_intc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc_0 ]
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set_property -dict [ list \
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CONFIG.C_IRQ_CONNECTION {1} \
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CONFIG.C_NUM_SW_INTR {2} \
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] $axi_intc_0
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# Create instance: axi_quad_spi_0, and set properties
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set axi_quad_spi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_quad_spi_0 ]
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set_property -dict [ list \
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CONFIG.C_FIFO_DEPTH {256} \
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CONFIG.C_SCK_RATIO {2} \
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CONFIG.C_SPI_MEMORY {2} \
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CONFIG.C_SPI_MODE {2} \
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CONFIG.C_USE_STARTUP {1} \
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CONFIG.C_USE_STARTUP_INT {1} \
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] $axi_quad_spi_0
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# Create instance: clk_wiz_0, and set properties
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set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ]
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set_property -dict [ list \
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CONFIG.CLKOUT1_JITTER {132.683} \
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CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {50.000} \
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CONFIG.CLKOUT2_JITTER {115.831} \
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CONFIG.CLKOUT2_PHASE_ERROR {87.180} \
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CONFIG.CLKOUT2_USED {true} \
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CONFIG.CLKOUT3_JITTER {102.086} \
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CONFIG.CLKOUT3_PHASE_ERROR {87.180} \
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CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {200.000} \
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CONFIG.CLKOUT3_USED {true} \
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CONFIG.MMCM_CLKOUT0_DIVIDE_F {24.000} \
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CONFIG.MMCM_CLKOUT1_DIVIDE {12} \
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CONFIG.MMCM_CLKOUT2_DIVIDE {6} \
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CONFIG.NUM_OUT_CLKS {3} \
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CONFIG.PRIM_SOURCE {Differential_clock_capable_pin} \
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CONFIG.RESET_PORT {reset} \
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CONFIG.RESET_TYPE {ACTIVE_HIGH} \
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CONFIG.USE_LOCKED {false} \
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CONFIG.USE_RESET {false} \
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] $clk_wiz_0
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# Create instance: cms_subsystem_0, and set properties
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set cms_subsystem_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cms_subsystem:4.0 cms_subsystem_0 ]
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# Create instance: hbm_infrastructure
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create_hier_cell_hbm_infrastructure [current_bd_instance .] hbm_infrastructure
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# Create instance: jungfraujoch_0
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create_hier_cell_jungfraujoch [current_bd_instance .] jungfraujoch_0
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# Create instance: mac_100g
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create_hier_cell_mac_100g [current_bd_instance .] mac_100g
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# Create instance: one, and set properties
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set one [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 one ]
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# Create instance: pcie_dma_0
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create_hier_cell_pcie_dma_0 [current_bd_instance .] pcie_dma_0
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# Create instance: proc_sys_reset_pcie_0, and set properties
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set proc_sys_reset_pcie_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_pcie_0 ]
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set_property -dict [ list \
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CONFIG.C_EXT_RST_WIDTH {1} \
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] $proc_sys_reset_pcie_0
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# Create instance: proc_sys_reset_refclk, and set properties
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set proc_sys_reset_refclk [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_refclk ]
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set_property -dict [ list \
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CONFIG.C_EXT_RST_WIDTH {1} \
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] $proc_sys_reset_refclk
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# Create instance: smartconnect_0, and set properties
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set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ]
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set_property -dict [ list \
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CONFIG.NUM_CLKS {4} \
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CONFIG.NUM_MI {6} \
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CONFIG.NUM_SI {1} \
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] $smartconnect_0
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# Create instance: xlconcat_irq, and set properties
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set xlconcat_irq [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_irq ]
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# Create instance: zero, and set properties
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set zero [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 zero ]
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set_property -dict [ list \
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CONFIG.CONST_VAL {0} \
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] $zero
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# Create interface connections
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connect_bd_intf_net -intf_net S_AXIS_100G_1 [get_bd_intf_pins jungfraujoch_0/eth_out] [get_bd_intf_pins mac_100g/s_axis_eth_out]
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connect_bd_intf_net -intf_net cms_subsystem_0_satellite_uart [get_bd_intf_ports satellite_uart_0] [get_bd_intf_pins cms_subsystem_0/satellite_uart]
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connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p0 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_0] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p0]
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connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p1 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_1] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p1]
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connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p2 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_2] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p2]
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connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p3 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_3] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p3]
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connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p4 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_4] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p4]
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connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p5 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_5] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p5]
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connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p6 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_6] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p6]
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connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p7 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_7] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p7]
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connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p8 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_8] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p8]
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connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p9 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_9] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p9]
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connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p10 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_10] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p10]
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connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p11 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_11] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p11]
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connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p12 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_12] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p12]
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connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p13 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_13] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p13]
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connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p14 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_14] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p14]
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connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p15 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_15] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p15]
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connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p16 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_16] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p16]
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connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p17 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_17] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p17]
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connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p18 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_18] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p18]
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connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p19 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_19] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p19]
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connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p20 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_20] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p20]
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connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p21 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_21] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p21]
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connect_bd_intf_net -intf_net jungfraujoch_0_m_axis_c2h_data [get_bd_intf_pins jungfraujoch_0/m_axis_c2h_data] [get_bd_intf_pins pcie_dma_0/s_axis_c2h_data]
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connect_bd_intf_net -intf_net jungfraujoch_0_m_axis_c2h_datamover_cmd [get_bd_intf_pins jungfraujoch_0/m_axis_c2h_datamover_cmd] [get_bd_intf_pins pcie_dma_0/s_axis_c2h_cmd]
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connect_bd_intf_net -intf_net jungfraujoch_0_m_axis_h2c_datamover_cmd [get_bd_intf_pins jungfraujoch_0/m_axis_h2c_datamover_cmd] [get_bd_intf_pins pcie_dma_0/s_axis_h2c_cmd]
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connect_bd_intf_net -intf_net mac_100g_1_M_AXIS_100G [get_bd_intf_pins jungfraujoch_0/eth_in] [get_bd_intf_pins mac_100g/m_axis_eth_in]
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connect_bd_intf_net -intf_net mac_100g_1_qsfp0 [get_bd_intf_ports qsfp0] [get_bd_intf_pins mac_100g/qsfp]
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connect_bd_intf_net -intf_net pcie0_ref_1 [get_bd_intf_ports pcie0_ref] [get_bd_intf_pins pcie_dma_0/pcie_refclk]
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connect_bd_intf_net -intf_net pcie_dma_0_M_AXI [get_bd_intf_pins pcie_dma_0/m_axi_ctrl] [get_bd_intf_pins smartconnect_0/S00_AXI]
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connect_bd_intf_net -intf_net pcie_dma_0_pcie0_mgt [get_bd_intf_ports pcie0_mgt] [get_bd_intf_pins pcie_dma_0/pcie_mgt]
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connect_bd_intf_net -intf_net qsfp0_ref_1 [get_bd_intf_ports qsfp0_ref] [get_bd_intf_pins mac_100g/qsfp_ref]
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connect_bd_intf_net -intf_net ref100_1 [get_bd_intf_ports ref100] [get_bd_intf_pins clk_wiz_0/CLK_IN1_D]
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connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins jungfraujoch_0/s_axi] [get_bd_intf_pins smartconnect_0/M00_AXI]
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connect_bd_intf_net -intf_net s_axi_2 [get_bd_intf_pins mac_100g/s_axi] [get_bd_intf_pins smartconnect_0/M02_AXI]
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connect_bd_intf_net -intf_net s_axis_h2c_data_1 [get_bd_intf_pins jungfraujoch_0/s_axis_h2c_data] [get_bd_intf_pins pcie_dma_0/m_axis_h2c_data]
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connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins smartconnect_0/M01_AXI] [get_bd_intf_pins cms_subsystem_0/s_axi_ctrl]
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connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_quad_spi_0/AXI_LITE] [get_bd_intf_pins smartconnect_0/M03_AXI]
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connect_bd_intf_net -intf_net smartconnect_0_M04_AXI [get_bd_intf_pins axi_intc_0/s_axi] [get_bd_intf_pins smartconnect_0/M04_AXI]
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connect_bd_intf_net -intf_net smartconnect_0_M05_AXI [get_bd_intf_pins pcie_dma_0/s_axi_dma_ctrl] [get_bd_intf_pins smartconnect_0/M05_AXI]
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# Create port connections
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connect_bd_net -net axi_clk_1 [get_bd_pins pcie_dma_0/axi_aclk] [get_bd_pins proc_sys_reset_pcie_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk3]
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connect_bd_net -net axi_quad_spi_0_ip2intc_irpt [get_bd_pins axi_quad_spi_0/ip2intc_irpt] [get_bd_pins xlconcat_irq/In0]
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connect_bd_net -net cms_subsystem_0_interrupt_host [get_bd_pins cms_subsystem_0/interrupt_host] [get_bd_pins xlconcat_irq/In1]
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connect_bd_net -net hbm_infrastructure_hbm_temp_trip_1 [get_bd_ports hbm_cattrip] [get_bd_pins cms_subsystem_0/interrupt_hbm_cattrip] [get_bd_pins hbm_infrastructure/hbm_cattrip]
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connect_bd_net -net hbm_infrastructure_hbm_temperature_0 [get_bd_pins cms_subsystem_0/hbm_temp_1] [get_bd_pins hbm_infrastructure/hbm_temperature_0]
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connect_bd_net -net hbm_infrastructure_hbm_temperature_1 [get_bd_pins cms_subsystem_0/hbm_temp_2] [get_bd_pins hbm_infrastructure/hbm_temperature_1]
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connect_bd_net -net mac_100g_eth_busy_n [get_bd_ports qsfp0_led_busy] [get_bd_pins mac_100g/eth_busy_n]
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connect_bd_net -net mac_100g_stat_rx_aligned_n [get_bd_ports qsfp0_led_conn] [get_bd_pins mac_100g/stat_rx_aligned_n]
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connect_bd_net -net net_refclk50 [get_bd_pins axi_intc_0/s_axi_aclk] [get_bd_pins axi_intc_1/s_axi_aclk] [get_bd_pins axi_quad_spi_0/s_axi_aclk] [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins cms_subsystem_0/aclk_ctrl] [get_bd_pins proc_sys_reset_refclk/slowest_sync_clk] [get_bd_pins proc_sys_reset_refclk1/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk2]
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connect_bd_net -net net_refclk100 [get_bd_pins axi_quad_spi_0/ext_spi_clk] [get_bd_pins clk_wiz_0/clk_out2] [get_bd_pins hbm_infrastructure/refclk100] [get_bd_pins mac_100g/refclk100] [get_bd_pins smartconnect_0/aclk1]
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connect_bd_net -net net_refclk200 [get_bd_pins clk_wiz_0/clk_out3] [get_bd_pins hbm_infrastructure/axi_clk] [get_bd_pins jungfraujoch_0/axi_clk] [get_bd_pins mac_100g/axiclk] [get_bd_pins pcie_dma_0/refclk200] [get_bd_pins smartconnect_0/aclk]
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connect_bd_net -net one_dout [get_bd_pins one/dout] [get_bd_pins cms_subsystem_0/aresetn_ctrl] [get_bd_pins proc_sys_reset_pcie_0/dcm_locked] [get_bd_pins proc_sys_reset_refclk/dcm_locked]
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connect_bd_net -net pcie_dma_0_axi_aresetn [get_bd_pins pcie_dma_0/axi_aresetn] [get_bd_pins proc_sys_reset_pcie_0/ext_reset_in] [get_bd_pins proc_sys_reset_refclk/ext_reset_in] [get_bd_pins smartconnect_0/aresetn]
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connect_bd_net -net pcie_perstn_1 [get_bd_ports pcie_perstn] [get_bd_pins pcie_dma_0/pcie_perstn]
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connect_bd_net -net proc_sys_reset_pcie_0_interconnect_aresetn [get_bd_pins pcie_dma_0/axi_clk_resetn] [get_bd_pins proc_sys_reset_pcie_0/interconnect_aresetn]
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connect_bd_net -net proc_sys_reset_refclk_peripheral_aresetn [get_bd_pins axi_intc_0/s_axi_aresetn] [get_bd_pins axi_quad_spi_0/s_axi_aresetn] [get_bd_pins hbm_infrastructure/axi_resetn] [get_bd_pins jungfraujoch_0/ap_rst_n] [get_bd_pins mac_100g/ap_rst_n] [get_bd_pins proc_sys_reset_refclk/peripheral_aresetn]
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connect_bd_net -net resetn_1 [get_bd_pins jungfraujoch_0/axi_rst_n] [get_bd_pins mac_100g/resetn] [get_bd_pins pcie_dma_0/refclk200_resetn] [get_bd_pins proc_sys_reset_refclk/interconnect_aresetn]
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connect_bd_net -net satellite_gpio_0_1 [get_bd_ports satellite_gpio_0] [get_bd_pins cms_subsystem_0/satellite_gpio]
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connect_bd_net -net usr_irq_req_1 [get_bd_pins axi_intc_0/irq] [get_bd_pins pcie_dma_0/usr_irq_req]
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connect_bd_net -net xlconcat_irq_dout [get_bd_pins axi_intc_0/intr] [get_bd_pins axi_intc_1/intr] [get_bd_pins xlconcat_irq/dout]
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connect_bd_net -net zero_dout [get_bd_pins axi_quad_spi_0/usrcclkts] [get_bd_pins zero/dout]
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# Create address segments
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assign_bd_address -offset 0x00010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_0/action_config_0/s_axi/reg0] -force
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assign_bd_address -offset 0x00020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs mac_100g/cmac_usplus_0/s_axi/Reg] -force
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assign_bd_address -offset 0x00030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_0/mailbox_0/S0_AXI/Reg] -force
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assign_bd_address -offset 0x00040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs axi_quad_spi_0/AXI_LITE/Reg] -force
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assign_bd_address -offset 0x00050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs axi_intc_0/S_AXI/Reg] -force
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assign_bd_address -offset 0x00060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_0/load_calibration_0/s_axi_control/Reg] -force
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assign_bd_address -offset 0x00070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs pcie_dma_0/axi_firewall_0/S_AXI_CTL/Control] -force
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assign_bd_address -offset 0x00080000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_0/frame_generator_0/s_axi_control/Reg] -force
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assign_bd_address -offset 0x00090000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs pcie_dma_0/xdma_0/S_AXI_LITE/CTL0] -force
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assign_bd_address -offset 0x000C0000 -range 0x00040000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs cms_subsystem_0/s_axi_ctrl/Mem] -force
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assign_bd_address
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set_property -dict [list \
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CONFIG.MAX_MODULES_FPGA_PARAM {0x00000010} \
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CONFIG.DESIGN_NUMBER {0} \
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] [get_bd_cells jungfraujoch_0/action_config_0]
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# Restore current instance
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current_bd_instance $oldCurInst
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save_bd_design
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validate_bd_design
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save_bd_design
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}
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# End of create_root_design()
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##################################################################
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# MAIN FLOW
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##################################################################
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create_root_design ""
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