453 lines
16 KiB
C
453 lines
16 KiB
C
// Copyright (2019-2023) Paul Scherrer Institute
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#include "jfjoch_drv.h"
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#include <linux/bitops.h>
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#include <linux/types.h>
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#include <linux/delay.h>
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DEFINE_MUTEX(set_config_mutex);
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DEFINE_MUTEX(set_mac_mutex);
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DEFINE_MUTEX(send_wr_mutex);
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DEFINE_MUTEX(read_wc_mutex);
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void jfjoch_write_register(struct jfjoch_drvdata *drvdata, uint32_t addr, uint32_t val) {
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iowrite32(val, drvdata->bar0 + addr);
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}
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uint32_t jfjoch_read_register(struct jfjoch_drvdata *drvdata, uint32_t addr) {
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return ioread32(drvdata->bar0 + addr);
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}
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void jfjoch_start(struct jfjoch_drvdata *drvdata) {
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// Set PCIe beats counters
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iowrite32((1 << 1), drvdata->bar0 + PCIE_OFFSET + (1<<12) + 0xC0);
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iowrite32((1 << 2), drvdata->bar0 + PCIE_OFFSET + (1<<12) + 0xC0);
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// Start DMA
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// Run C2H
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iowrite32(JFJOCH_DMA_SETTINGS, drvdata->bar0 + PCIE_OFFSET + (1<<12) + 0x04);
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// Set Mailbox FIFOs, so interrupt threshold is 16 messages
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// => This way it ensures that one can always execute read/write operation on the FIFO
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iowrite32(255-16, drvdata->bar0 + MAILBOX_OFFSET + ADDR_MAILBOX_SIT);
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iowrite32(15 , drvdata->bar0 + MAILBOX_OFFSET + ADDR_MAILBOX_RIT);
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// Write Start value to action config register
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iowrite32(0x1, drvdata->bar0 + ACTION_CONFIG_OFFSET);
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}
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void jfjoch_end(struct jfjoch_drvdata *drvdata) {
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// Write cancel register
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iowrite32(0x4, drvdata->bar0 + ACTION_CONFIG_OFFSET);
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// RUN ==> C2H channel 0 control register
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iowrite32(0, drvdata->bar0 + PCIE_OFFSET + (1<<12) + 0x04);
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}
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void jfjoch_cancel(struct jfjoch_drvdata *drvdata) {
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iowrite32(0x4, drvdata->bar0 + ACTION_CONFIG_OFFSET);
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}
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int jfjoch_send_wr(struct jfjoch_drvdata *drvdata, u32 handle) {
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u32 sta;
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dma_addr_t addr = 0;
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u32 parity = 0;
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if (handle != 0xFFFFFFFFLU) {
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if (handle >= nbuffer)
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return -EFAULT;
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addr = drvdata->bufs[handle].dma_address;
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}
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parity = (hweight32(handle) + hweight64(addr)) % 2;
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mutex_lock(&send_wr_mutex);
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sta = ioread32(drvdata->bar0 + MAILBOX_OFFSET + ADDR_MAILBOX_STATUS) & MAILBOX_STA;
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if (!sta) {
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mutex_unlock(&send_wr_mutex);
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return -EAGAIN;
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}
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iowrite32(handle, drvdata->bar0 + MAILBOX_OFFSET + ADDR_MAILBOX_WRDATA);
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iowrite32(PCI_DMA_H(addr), drvdata->bar0 + MAILBOX_OFFSET + ADDR_MAILBOX_WRDATA);
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iowrite32(PCI_DMA_L(addr), drvdata->bar0 + MAILBOX_OFFSET + ADDR_MAILBOX_WRDATA);
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iowrite32(parity, drvdata->bar0 + MAILBOX_OFFSET + ADDR_MAILBOX_WRDATA);
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mutex_unlock(&send_wr_mutex);
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return 0;
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}
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int jfjoch_read_wc(struct jfjoch_drvdata *drvdata, u32 *output) {
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u32 rta;
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int i;
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mutex_lock(&read_wc_mutex);
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rta = ioread32(drvdata->bar0 + MAILBOX_OFFSET + ADDR_MAILBOX_STATUS) & MAILBOX_RTA;
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if (!rta) {
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mutex_unlock(&read_wc_mutex);
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return -EAGAIN;
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}
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for (i = 0; i < 16; i++)
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output[i] = ioread32(drvdata->bar0 + MAILBOX_OFFSET + ADDR_MAILBOX_RDDATA);
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mutex_unlock(&read_wc_mutex);
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return 0;
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}
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void jfjoch_set_config(struct jfjoch_drvdata *drvdata, const struct DataCollectionConfig *config) {
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mutex_lock(&set_config_mutex);
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memcpy_toio((drvdata->bar0) + ACTION_CONFIG_OFFSET + ADDR_NMODULES, config, sizeof(struct DataCollectionConfig));
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mutex_unlock(&set_config_mutex);
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}
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void jfjoch_get_config(struct jfjoch_drvdata *drvdata, struct DataCollectionConfig *config) {
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memcpy_fromio(config, (drvdata->bar0) + ACTION_CONFIG_OFFSET + ADDR_NMODULES, sizeof(struct DataCollectionConfig));
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}
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void jfjoch_get_status(struct jfjoch_drvdata *drvdata, struct DataCollectionStatus *status) {
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memcpy_fromio(status, drvdata->bar0 + ACTION_CONFIG_OFFSET, sizeof(struct DataCollectionStatus));
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}
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void jfjoch_set_mac_addr(struct jfjoch_drvdata *drvdata, u64 *mac_addr) {
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mutex_lock(&set_mac_mutex);
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memcpy_toio((drvdata->bar0) + ACTION_CONFIG_OFFSET + ADDR_MAC_ADDR_LO, mac_addr, sizeof(uint64_t));
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mutex_unlock(&set_mac_mutex);
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}
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void jfjoch_get_mac_addr(struct jfjoch_drvdata *drvdata, u64 *mac_addr) {
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memcpy_fromio(mac_addr, (drvdata->bar0) + ACTION_CONFIG_OFFSET + ADDR_MAC_ADDR_LO, sizeof(uint64_t));
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}
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void jfjoch_set_ipv4_addr(struct jfjoch_drvdata *drvdata, const u32 *addr) {
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mutex_lock(&set_mac_mutex);
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iowrite32(*addr, (drvdata->bar0) + ACTION_CONFIG_OFFSET + ADDR_IPV4_ADDR);
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mutex_unlock(&set_mac_mutex);
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}
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void jfjoch_get_ipv4_addr(struct jfjoch_drvdata *drvdata, u32 *addr) {
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*addr = ioread32((drvdata->bar0) + ACTION_CONFIG_OFFSET + ADDR_IPV4_ADDR);
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}
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u64 jfjoch_read_mac_addr(struct jfjoch_drvdata *drvdata) {
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struct device *const dev = &drvdata->pdev->dev;
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u32 tmp, host_msg_offset, msg_len;
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u32 field_type, field_len;
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u32 i, j;
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u8 output[256];
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u64 mac = 0;
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u64 design_number;
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// Check which card is this
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if (ioread32(drvdata->bar0 + ACTION_CONFIG_OFFSET) & (1<<7))
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design_number = 1;
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else
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design_number = 0;
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if (ioread32(drvdata->bar0 + CMS_OFFSET + ADDR_CMS_CONTROL_REG) & (1 << 5)) {
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dev_err(dev, "Mailbox not available");
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return 0;
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}
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host_msg_offset = ioread32(drvdata->bar0 + CMS_OFFSET + 0x28300);
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dev_info(dev, "Host msg offset %x", host_msg_offset);
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iowrite32(0x04000000, drvdata->bar0 + CMS_OFFSET + 0x28000 + host_msg_offset);
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iowrite32(1<<5, drvdata->bar0 + CMS_OFFSET + ADDR_CMS_CONTROL_REG);
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i = 0;
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while (i < 50) {
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if (!(ioread32(drvdata->bar0 + CMS_OFFSET + ADDR_CMS_CONTROL_REG) & (1 << 5)))
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break;
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msleep(100);
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i++;
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}
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tmp = ioread32(drvdata->bar0 + CMS_OFFSET + ADDR_CMS_CONTROL_REG) & (1 << 5);
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if (tmp) {
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dev_err(dev, "Mailbox not ready %x", tmp);
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return 0;
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}
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tmp = ioread32(drvdata->bar0 + CMS_OFFSET + 0x28304);
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if (tmp) {
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dev_err(dev, "Error in mailbox %x", tmp);
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return 0;
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}
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tmp = ioread32(drvdata->bar0 + CMS_OFFSET + 0x28000 + host_msg_offset);
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dev_info(dev, "Mailbox response %x", tmp);
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if ((tmp & 0xFF000000) != 0x04000000) {
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dev_err(dev, "Opcode in return message doesn't match %x", tmp);
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return 0;
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}
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msg_len = tmp & 0xFFF;
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dev_info(dev, "Mailbox response length %x", msg_len);
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i = 0;
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while (i < msg_len) {
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field_type = ioread8(drvdata->bar0 + CMS_OFFSET + 0x28000 + host_msg_offset + 0x4 + i);
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field_len = ioread8(drvdata->bar0 + CMS_OFFSET + 0x28000 + host_msg_offset + 0x4 + i + 1);
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for (j = 0; j < field_len; j++)
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output[j] = ioread8(drvdata->bar0 + CMS_OFFSET + 0x28000 + host_msg_offset + 0x4 + i + 2 + j);
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output[field_len] = 0x0;
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if (field_type == 0x21)
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dev_info(dev, "Card serial number %s", output);
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if (field_type == 0x4B) {
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dev_info(dev, "MAC Addr %d %02x:%02x:%02x:%02x:%02x:%02x",
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output[0], output[2], output[3], output[4], output[5], output[6], output[7]);
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mac = ((u64)(output[2]))
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| ((u64)(output[3]) << 8)
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| ((u64)(output[4]) << 16)
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| ((u64)(output[5]) << 24)
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| ((u64)(output[6]) << 32)
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| ((u64)(output[7]) << 40);
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mac += (design_number << 40);
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jfjoch_set_mac_addr(drvdata, &mac);
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}
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i += field_len + 2;
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}
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return mac;
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}
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void jfjoch_is_idle(struct jfjoch_drvdata *drvdata, uint32_t *output) {
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if (ioread32(drvdata->bar0 + ACTION_CONFIG_OFFSET + ADDR_CTRL_REGISTER) & CTRL_REGISTER_IDLE)
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*output = 1;
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else
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*output = 0;
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}
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void jfjoch_setup_cms(struct jfjoch_drvdata *drvdata) {
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iowrite32(0x1, drvdata->bar0 + CMS_OFFSET + ADDR_CMS_MB_RESETN_REG);
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iowrite32(1 << 27, drvdata->bar0 + CMS_OFFSET + ADDR_CMS_CONTROL_REG); // enable HBM monitoring
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}
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void jfjoch_setup_network(struct jfjoch_drvdata *drvdata) {
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// Enable RS_FEC
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iowrite32(0x03, drvdata->bar0 + CMAC_OFFSET + 0x107C);
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// Restart TX and RX cores + deassert resets
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iowrite32((1 << 31) + (1 << 30), drvdata->bar0 + CMAC_OFFSET + 0x0004);
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iowrite32(0x0, drvdata->bar0 + CMAC_OFFSET + 0x0004);
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// TX Send RFI
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iowrite32(0x10, drvdata->bar0 + CMAC_OFFSET + 0x000C);
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// Enable RX
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iowrite32(0x1, drvdata->bar0 + CMAC_OFFSET + 0x0014);
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// start communication
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iowrite32(0x1, drvdata->bar0 + CMAC_OFFSET + 0x000C);
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// enable counters
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iowrite32(0, drvdata->bar0 + ACTION_CONFIG_OFFSET);
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}
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void jfjoch_get_env_data(struct jfjoch_drvdata *drvdata, struct DeviceStatus *env_params) {
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env_params->mailbox_status_reg = ioread32(drvdata->bar0 + MAILBOX_OFFSET + 0x10);
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env_params->mailbox_err_reg = ioread32(drvdata->bar0 + MAILBOX_OFFSET + 0x14);
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env_params->fpga_temp_C = ioread32(drvdata->bar0 + CMS_OFFSET + ADDR_CMS_FPGA_TEMP_INS_REG);
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env_params->fpga_pcie_3p3V_I_mA = ioread32(drvdata->bar0 + CMS_OFFSET + ADDR_CMS_3V3PEX_I_IN_INS_REG);
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env_params->fpga_pcie_12V_I_mA = ioread32(drvdata->bar0 + CMS_OFFSET + ADDR_CMS_12VPEX_I_IN_INS_REG);
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env_params->fpga_pcie_3p3V_V_mV = ioread32(drvdata->bar0 + CMS_OFFSET + ADDR_CMS_3V3_PEX_INS_REG);
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env_params->fpga_pcie_12V_V_mV = ioread32(drvdata->bar0 + CMS_OFFSET + ADDR_CMS_12V_PEX_INS_REG);
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env_params->pcie_h2c_descriptors = ioread32(drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0x48);
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env_params->pcie_h2c_beats = ioread32(drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0xCC);
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env_params->pcie_h2c_status = ioread32(drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0x40);
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env_params->pcie_c2h_descriptors = ioread32(drvdata->bar0 + PCIE_OFFSET + (1<<12) + 0x48);
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env_params->pcie_c2h_beats = ioread32(drvdata->bar0 + PCIE_OFFSET + (1<<12) + 0xCC);
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env_params->pcie_c2h_status = ioread32(drvdata->bar0 + PCIE_OFFSET + (1<<12) + 0x40);
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env_params->hbm_0_temp_C = ioread32(drvdata->bar0 + CMS_OFFSET + ADDR_CMS_HBM_TEMP1_INS_REG);
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env_params->hbm_1_temp_C = ioread32(drvdata->bar0 + CMS_OFFSET + ADDR_CMS_HBM_TEMP2_INS_REG);
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// Somehow it is better to ask twice
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env_params->ethernet_aligned = ioread32(drvdata->bar0 + CMAC_OFFSET + 0x0204) & 0x2;
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env_params->ethernet_aligned = ioread32(drvdata->bar0 + CMAC_OFFSET + 0x0204) & 0x2;
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}
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void jfjoch_clr_net_counters(struct jfjoch_drvdata *drvdata) {
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iowrite32(1 << 3, drvdata->bar0 + ACTION_CONFIG_OFFSET);
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iowrite32(0, drvdata->bar0 + ACTION_CONFIG_OFFSET);
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}
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int jfjoch_load_calibration(struct jfjoch_drvdata *drvdata, struct DataCollectionConfig *config) {
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struct device *const dev = &drvdata->pdev->dev;
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u32 i;
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u32 cell_count = config->nmodules * (3 + 3 * config->nstorage_cells);
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if (cell_count > drvdata->nbuf) {
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dev_err(dev, "Not enough buffers to support this card\n");
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return -EINVAL;
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}
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for (i = 0; i < cell_count; i++) {
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u64 addr = drvdata->bufs[i].dma_address;
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iowrite32(PCI_DMA_L(addr), drvdata->bar0 + ADDR_LOAD_CALIBRATION_MEM + i * 2 * 4);
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iowrite32(PCI_DMA_H(addr), drvdata->bar0 + ADDR_LOAD_CALIBRATION_MEM + (i * 2 + 1) * 4);
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}
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// Start DMA
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// Clear counters and RUN H2C
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iowrite32((1 << 1), drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0xC0);
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iowrite32((1 << 2), drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0xC0);
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iowrite32(JFJOCH_DMA_SETTINGS, drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0x04);
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iowrite32(config->nmodules, drvdata->bar0 + ADDR_LOAD_CALIBRATION_MOD);
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iowrite32(config->nstorage_cells, drvdata->bar0 + ADDR_LOAD_CALIBRATION_SC);
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iowrite32(LOAD_CALIBRATION_DEST_CALIB, drvdata->bar0 + ADDR_LOAD_CALIBRATION_DEST);
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iowrite32(0x1, drvdata->bar0 + ADDR_LOAD_CALIBRATION_CTRL);
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i = 0;
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while (i < 1000) {
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if (ioread32(drvdata->bar0 + ADDR_LOAD_CALIBRATION_CTRL) & (1 << 1))
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break;
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msleep(10);
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i++;
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}
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// STOP H2C channel
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iowrite32(0, drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0x04);
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if (i == 1000) {
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dev_err(dev, "Load calibration didn't finish in 10 seconds\n");
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return -ETIMEDOUT;
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}
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return 0;
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}
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int jfjoch_load_integration_map(struct jfjoch_drvdata *drvdata, struct DataCollectionConfig *config) {
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struct device *const dev = &drvdata->pdev->dev;
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u32 i;
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u32 cell_count = config->nmodules;
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if (cell_count > drvdata->nbuf) {
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dev_err(dev, "Not enough buffers to support this card\n");
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return -EINVAL;
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}
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for (i = 0; i < cell_count; i++) {
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u64 addr = drvdata->bufs[i].dma_address;
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iowrite32(PCI_DMA_L(addr), drvdata->bar0 + ADDR_LOAD_CALIBRATION_MEM + i * 2 * 4);
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iowrite32(PCI_DMA_H(addr), drvdata->bar0 + ADDR_LOAD_CALIBRATION_MEM + (i * 2 + 1) * 4);
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}
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// Start DMA
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// Clear counters and RUN H2C
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iowrite32((1 << 1), drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0xC0);
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iowrite32((1 << 2), drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0xC0);
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iowrite32(JFJOCH_DMA_SETTINGS, drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0x04);
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iowrite32(config->nmodules, drvdata->bar0 + ADDR_LOAD_CALIBRATION_MOD);
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iowrite32(LOAD_CALIBRATION_DEST_INTEGRATION, drvdata->bar0 + ADDR_LOAD_CALIBRATION_DEST);
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iowrite32(0x1, drvdata->bar0 + ADDR_LOAD_CALIBRATION_CTRL);
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i = 0;
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while (i < 1000) {
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if (ioread32(drvdata->bar0 + ADDR_LOAD_CALIBRATION_CTRL) & (1 << 1))
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break;
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msleep(10);
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i++;
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}
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// STOP H2C channel
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iowrite32(0, drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0x04);
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if (i == 1000) {
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dev_err(dev, "Load calibration didn't finish in 10 seconds\n");
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return -ETIMEDOUT;
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}
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return 0;
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}
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int jfjoch_load_internal_generator_frame(struct jfjoch_drvdata *drvdata, struct DataCollectionConfig *config) {
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struct device *const dev = &drvdata->pdev->dev;
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u32 i;
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u32 cell_count = config->nmodules;
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if (cell_count > drvdata->nbuf) {
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dev_err(dev, "Not enough buffers to support this card\n");
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return -EINVAL;
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}
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for (i = 0; i < cell_count; i++) {
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u64 addr = drvdata->bufs[i].dma_address;
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iowrite32(PCI_DMA_L(addr), drvdata->bar0 + ADDR_LOAD_CALIBRATION_MEM + i * 2 * 4);
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iowrite32(PCI_DMA_H(addr), drvdata->bar0 + ADDR_LOAD_CALIBRATION_MEM + (i * 2 + 1) * 4);
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}
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// Start DMA
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// Clear counters and RUN H2C
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iowrite32((1 << 1), drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0xC0);
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iowrite32((1 << 2), drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0xC0);
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iowrite32(JFJOCH_DMA_SETTINGS, drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0x04);
|
|
|
|
iowrite32(config->nmodules, drvdata->bar0 + ADDR_LOAD_CALIBRATION_MOD);
|
|
iowrite32(LOAD_CALIBRATION_DEST_FRAME_GEN, drvdata->bar0 + ADDR_LOAD_CALIBRATION_DEST);
|
|
iowrite32(0x1, drvdata->bar0 + ADDR_LOAD_CALIBRATION_CTRL);
|
|
|
|
i = 0;
|
|
while (i < 1000) {
|
|
if (ioread32(drvdata->bar0 + ADDR_LOAD_CALIBRATION_CTRL) & (1 << 1))
|
|
break;
|
|
msleep(10);
|
|
i++;
|
|
}
|
|
|
|
// STOP H2C channel
|
|
iowrite32(0, drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0x04);
|
|
|
|
if (i == 1000) {
|
|
dev_err(dev, "Load calibration didn't finish in 10 seconds\n");
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int jfjoch_run_frame_gen(struct jfjoch_drvdata *drvdata, struct FrameGeneratorConfig *config) {
|
|
struct device *const dev = &drvdata->pdev->dev;
|
|
|
|
if (ioread32(drvdata->bar0 + ADDR_FRAME_GEN_CTRL) & 0x1) {
|
|
dev_err(dev, "Frame generator busy\n");
|
|
return -EBUSY;
|
|
}
|
|
|
|
iowrite32(config->frames, drvdata->bar0 + ADDR_FRAME_GEN_FRAMES);
|
|
iowrite32(config->modules, drvdata->bar0 + ADDR_FRAME_GEN_MODULES);
|
|
iowrite32(config->dest_ipv4_addr, drvdata->bar0 + ADDR_FRAME_GEN_DEST_IPV4_ADDR);
|
|
iowrite32(config->dest_mac_addr & 0xFFFFFFFF, drvdata->bar0 + ADDR_FRAME_GEN_DEST_MAC_LO);
|
|
iowrite32(config->dest_mac_addr >> 32, drvdata->bar0 + ADDR_FRAME_GEN_DEST_MAC_HI);
|
|
iowrite32(config->bunchid & 0xFFFFFFFF, drvdata->bar0 + ADDR_FRAME_GEN_BUNCHID_LO);
|
|
iowrite32(config->bunchid >> 32, drvdata->bar0 + ADDR_FRAME_GEN_BUNCHID_HI);
|
|
iowrite32(config->exptime, drvdata->bar0 + ADDR_FRAME_GEN_EXPTIME);
|
|
iowrite32(config->debug, drvdata->bar0 + ADDR_FRAME_GEN_DEBUG);
|
|
iowrite32(0x1, drvdata->bar0 + ADDR_FRAME_GEN_CTRL);
|
|
return 0;
|
|
}
|
|
|
|
u32 jfjoch_get_c2h_descriptors(struct jfjoch_drvdata *drvdata) {
|
|
return ioread32(drvdata->bar0 + PCIE_OFFSET + (1<<12) + 0x48);
|
|
}
|
|
|
|
void jfjoch_set_spot_finder_parameters(struct jfjoch_drvdata *drvdata, struct SpotFinderParameters *params) {
|
|
iowrite32(params->count_threshold, drvdata->bar0 + ADDR_SPOT_FINDER_THRESHOLD);
|
|
iowrite32(params->snr_threshold, drvdata->bar0 + ADDR_SPOT_FINDER_SNR);
|
|
} |