123 lines
4.2 KiB
C++
123 lines
4.2 KiB
C++
// Copyright (2019-2023) Paul Scherrer Institute
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#include "hls_jfjoch.h"
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void save_to_hbm(STREAM_512 &data_in,
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STREAM_512 &data_out,
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hls::stream<axis_addr> &addr_in,
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hls::stream<axis_completion > &m_axis_completion,
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hls::stream<ap_uint<16>> &s_axis_free_handles,
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hls::stream<ap_axiu<256,1,1,1> > &hbm_out_0,
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hls::stream<ap_axiu<256,1,1,1> > &hbm_out_1,
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hls::stream<axis_datamover_ctrl> &datamover_0_cmd,
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hls::stream<axis_datamover_ctrl> &datamover_1_cmd,
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ap_uint<32> hbm_size_bytes) {
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#pragma HLS INTERFACE ap_ctrl_none port=return
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#pragma HLS INTERFACE register both axis port=data_in
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#pragma HLS INTERFACE register both axis port=data_out
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#pragma HLS INTERFACE register both axis port=addr_in
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#pragma HLS INTERFACE register both axis port=m_axis_completion
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#pragma HLS INTERFACE register both axis port=s_axis_free_handles
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#pragma HLS INTERFACE register both axis port=hbm_out_0
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#pragma HLS INTERFACE register both axis port=hbm_out_1
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#pragma HLS INTERFACE register both axis port=datamover_0_cmd
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#pragma HLS INTERFACE register both axis port=datamover_1_cmd
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#pragma HLS INTERFACE mode=ap_none port=hbm_size_bytes
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axis_completion cmpl[MAX_MODULES_FPGA*2];
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for (int i = 0; i < MAX_MODULES_FPGA*2; i++) {
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#pragma HLS UNROLL
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cmpl[i].frame_number = UINT64_MAX;
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cmpl[i].packet_mask = 0;
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cmpl[i].last = 0;
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}
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axis_addr addr;
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addr_in >> addr;
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packet_512_t packet_in;
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data_in >> packet_in;
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data_out << packet_in;
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ap_uint<32> offset_hbm_0 = 12 * hbm_size_bytes / 32;
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ap_uint<32> offset_hbm_1 = 14 * hbm_size_bytes / 32;
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addr_in >> addr;
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Loop_good_packet:
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while (!addr.last) {
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// Process one UDP packet per iteration
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#pragma HLS PIPELINE II=128
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ap_uint<64> frame_number = addr.frame_number;
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ap_uint<5> module_number = addr.module;
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ap_uint<7> eth_packet = addr.eth_packet;
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ap_uint<5> id = module_number * 2 + (frame_number % 2);
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ap_uint<16> curr_handle = 0;
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if (cmpl[id].frame_number != frame_number) {
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if (cmpl[id].packet_mask != 0)
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m_axis_completion << cmpl[id];
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cmpl[id].module = addr.module;
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cmpl[id].frame_number = addr.frame_number;
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cmpl[id].timestamp = addr.timestamp;
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cmpl[id].exptime = addr.exptime;
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cmpl[id].debug = addr.debug;
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cmpl[id].bunchid = addr.bunchid;
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cmpl[id].last = 0;
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cmpl[id].packet_mask = ap_uint<128>(1) << eth_packet;
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cmpl[id].packet_count = 1;
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curr_handle = s_axis_free_handles.read();
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cmpl[id].handle = curr_handle;
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} else {
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cmpl[id].packet_mask |= ap_uint<128>(1) << eth_packet;
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cmpl[id].packet_count++;
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}
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size_t offset = ((cmpl[id].handle / 2) * RAW_MODULE_SIZE * sizeof(uint16_t) + eth_packet * 8192) / 64;
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if (cmpl[id].handle % 2 == 1)
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offset += hbm_size_bytes / 32;
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setup_datamover(datamover_0_cmd, (offset_hbm_0 + offset) * 32, 4096);
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setup_datamover(datamover_1_cmd, (offset_hbm_1 + offset) * 32, 4096);
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for (int i = 0; i < 128; i++) {
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data_in >> packet_in;
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ap_axiu<256,1,1,1> packet_out;
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packet_out.keep = UINT32_MAX;
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packet_out.strb = UINT32_MAX;
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packet_out.user = 0;
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packet_out.dest = 0;
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packet_out.id = 0;
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packet_out.last = (i == 127);
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packet_out.data = packet_in.data(255, 0);
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hbm_out_0 << packet_out;
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packet_out.data = packet_in.data(511, 256);
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hbm_out_1 << packet_out;
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}
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addr_in >> addr;
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}
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for (ap_uint<8> m = 0; m < MAX_MODULES_FPGA * 2; m++) {
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#pragma HLS PIPELINE II=16
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if (cmpl[m].packet_mask != 0)
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m_axis_completion << cmpl[m];
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}
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data_in >> packet_in;
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data_out << packet_in;
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m_axis_completion << axis_completion{.last = 1};
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ap_uint<16> tmp = s_axis_free_handles.read();
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while (tmp != UINT16_MAX)
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tmp = s_axis_free_handles.read();
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}
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