35 lines
760 B
Verilog
35 lines
760 B
Verilog
// Copyright (2019-2023) Paul Scherrer Institute
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`timescale 1ns / 1ps
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module resetn_sync (
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(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
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(* X_INTERFACE_PARAMETER = "ASSOCIATED_RESET out_resetn" *)
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input clk,
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(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 in_resetn RST" *)
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(* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *)
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input in_resetn,
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(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 out_resetn RST" *)
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(* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *)
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output out_resetn
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);
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(* ASYNC_REG = "TRUE" *) reg q0, q1, q2;
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always @(posedge clk or negedge in_resetn)
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if (~in_resetn)
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q0 <= 1'b0;
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else
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q0 <= in_resetn;
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always @(posedge clk)
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begin
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q1 <= q0;
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q2 <= q1;
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end
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assign out_resetn = q2;
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endmodule
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