38 lines
1.2 KiB
Verilog
38 lines
1.2 KiB
Verilog
// Copyright (2019-2023) Paul Scherrer Institute
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`timescale 1ns / 1ps
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module check_datamover_error(
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output reg err_encountered,
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(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
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(* X_INTERFACE_PARAMETER = "ASSOCIATED_RESET resetn, ASSOCIATED_BUSIF S_AXIS" *)
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input clk,
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(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 resetn RST" *)
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(* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *)
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input resetn,
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(* X_INTERFACE_PARAMETER = "HAS_TLAST 1,HAS_TKEEP 1,HAS_TREADY 1,TUSER_WIDTH 0,TDATA_NUM_BYTES 1" *)
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(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
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input [7:0] S_AXIS_tdata,
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(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TKEEP" *)
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input S_AXIS_tkeep,
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(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *)
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input S_AXIS_tlast,
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(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
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input S_AXIS_tvalid,
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(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
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output S_AXIS_tready
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);
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assign S_AXIS_tready = resetn;
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always @(posedge clk) begin
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if (!resetn)
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err_encountered <= 0;
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else if (S_AXIS_tvalid)
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err_encountered <= !S_AXIS_tdata[7];
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end
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endmodule
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