The GPU engines are built per worker per step, and each took its page-locked host buffers with cudaHostAlloc / cudaHostRegister and gave them back with cudaFreeHost / cudaHostUnregister. Those calls map and lock pages under the process's memory-map lock, so all workers queue behind each other: on the 5080 workstation a myoglobin run made ~3400 of them (6-22 thread-s, depending on the load), 9gdj ~10400 (124 thread-s); on a four-socket host they cost 20-30 ms each. - CudaHostPtr takes its memory from a pool: a freed buffer is kept in a power-of-two size class for the next engine, up to 512 MiB in all; a buffer above 64 MiB is never kept. Rugnux::Run hands the pool back at its end. - PinnedVector (std::vector with the pool's allocator) replaces the registered vectors of AdaptiveSpotFinderGPU and ImagePreprocessorGPU; the Bragg predictors download into a pooled pinned buffer and copy into their output, instead of registering it. - BSLZ4DecoderGPU copies the compressed chunk into a pooled pinned buffer before the upload, so it is one DMA instead of the driver's pageable staging (9gdj: 163 GB pageable H2D, 52 s of copy time, -> 147 GB pinned, 13 s). Measured with nsys on the workstation: myob 3398 -> 1396 calls (674 of them the release at the end), cytc 2986 -> 1270, 9gdj 10428 -> 1748 (124 -> 3.7 thread-s). Output identical (p.hkl md5 on myob, cytc, 9gdj; CI tier battery). Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01EizBKhTqrAYago9KJG3dA3
136 lines
8.1 KiB
C++
136 lines
8.1 KiB
C++
// SPDX-FileCopyrightText: 2026 Filip Leonarski, Paul Scherrer Institute <filip.leonarski@psi.ch>
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// SPDX-License-Identifier: GPL-3.0-only
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#pragma once
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// GPU adaptive spot finder that FUSES azimuthal integration and spot finding into one image pass.
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//
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// The CPU adaptive finder (AdaptiveSpotFinderCPU) and the azimuthal integrator both bin every pixel
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// into resolution rings and reduce (sum / sum^2 / count). Today azint runs on the GPU while the
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// adaptive finder re-does the identical per-ring reduction on the HOST - a wasted second pass over a
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// ~10 MP image. This engine does the ring reduction on the GPU and drives BOTH products from it:
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// - the azimuthal-integration profile (mean intensity per ring, in flat-field-corrected space), and
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// - the per-ring background (mean, sigma, peak-excluded via two sigma-clip passes) that sets the
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// self-calibrating spot-detection threshold (in raw photon counts).
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// The ring threshold is the photon-count FLOOR and nothing more: this engine derives from the classic
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// ImageSpotFinderGPU and intersects the ring mask with that engine's local-box SNR mask, exactly as
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// AdaptiveSpotFinderCPU does on the host (the reason the local test is not optional is written out
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// there). The result is left in the inherited bit buffer, still on the device, and the inherited
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// SpotExtractorGPU builds the spots from it.
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//
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// Numerically it reproduces AdaptiveSpotFinderCPU: the same three-pass robust background, the same
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// per-ring threshold formula (shared via AdaptiveThreshold.h, computed on the host once per frame),
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// and the same intersection with the local test. The only differences from the CPU are those inherent
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// to a GPU reduction (float per-ring accumulation in atomic order vs the CPU's serial double sums),
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// which shift a handful of borderline pixels at most. The corrected sums for the azint profile are
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// accumulated in the SAME plain first pass, so one reduction feeds both products.
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#include <memory>
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#include <vector>
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#include "ImageSpotFinderGPU.h"
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#include "SpotExtractorGPU.h"
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#include "SpotFindingSettings.h"
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#include "../../common/AzimuthalIntegrationProfile.h"
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#include "../../common/AzimuthalIntegrationMapping.h"
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#include "../indexing/CUDAMemHelpers.h"
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#include "../indexing/CudaSharedTables.h"
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class AdaptiveSpotFinderGPU : public ImageSpotFinderGPU {
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const AzimuthalIntegrationMapping &mapping;
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const int nbins;
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const size_t npix;
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int reduce_threads = 256;
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int reduce_blocks = 0; // global-atomics fallback
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int reduce_blocks_plain = 0; // as many blocks as actually fit, per shared-memory footprint
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int reduce_blocks_clip = 0;
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int flag_threads = 256;
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int flag_blocks = 0;
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size_t shared_plain = 0; // per-block shared bytes for the plain pass (raw + corrected rings)
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size_t shared_clip = 0; // per-block shared bytes for a sigma-clip pass (raw rings only)
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bool use_shared = true; // false -> nbins too large for shared memory, use the global-atomics kernel
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// Static mapping inputs: geometry-only, so one copy per GPU shared with every other engine on it
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// (see CudaSharedTables.h) rather than one copy per worker thread.
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std::shared_ptr<CudaDevicePtr<uint16_t>> gpu_pixel_to_bin;
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std::shared_ptr<CudaDevicePtr<float>> gpu_corrections;
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// Raw per-ring accumulators (re-zeroed each pass) + derived stats used to clip and threshold.
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// double, like the CPU engine's ring accumulators: the ring sigma is the cancelling difference
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// sum2/n - m^2, and the block atomics that fill these arrive in an arbitrary order.
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CudaDevicePtr<unsigned long long> gpu_sum;
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CudaDevicePtr<unsigned long long> gpu_sum2;
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CudaDevicePtr<uint32_t> gpu_count;
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CudaDevicePtr<float> gpu_mean; // per-ring raw mean (clip predicate)
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CudaDevicePtr<float> gpu_sigma; // per-ring raw sigma (clip predicate)
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// The plain pass's valid pixels as a per-ring histogram of their values, and the (ring, value) of
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// those outside [0, HIST_VALUES) - so the sigma-clip passes need not re-read the image. A list
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// longer than overflow_cap is only counted, and the clip passes then read the image instead.
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// Allocated only on the shared-memory path (few rings).
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CudaDevicePtr<uint32_t> gpu_hist;
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CudaDevicePtr<int2> gpu_overflow;
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CudaDevicePtr<uint32_t> gpu_overflow_n;
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uint32_t overflow_cap = 0;
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// Corrected per-ring accumulators (plain first pass only) -> azimuthal-integration profile.
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// Fixed point (CORR_FIXED in the .cu), so the sums do not depend on the order the atomics arrive in.
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CudaDevicePtr<unsigned long long> gpu_sum_corr;
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CudaDevicePtr<unsigned long long> gpu_sum2_corr;
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// Per-ring detection threshold (host-computed, uploaded) and the ring-threshold mask that is
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// intersected into the inherited bit buffer.
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CudaDevicePtr<float> gpu_thr;
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CudaDevicePtr<uint32_t> gpu_ring;
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// Per 32-pixel word of the image: the largest value of the frame (as an order-keeping unsigned
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// key, noted by the plain pass) and the range of rings its pixels fall in (geometry, filled once).
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// Together they let flag_strong skip the words that cannot hold a strong pixel.
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CudaDevicePtr<uint32_t> gpu_word_max;
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CudaDevicePtr<ushort2> gpu_word_range;
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// Host mirrors of the small per-ring transfers.
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PinnedVector<unsigned long long> host_sum; // clipped raw sum } input to the host threshold computation
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PinnedVector<unsigned long long> host_sum2; // clipped raw sum^2 } (exact integers - see the kernel)
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PinnedVector<uint32_t> host_count; // clipped raw count }
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std::vector<float> host_thr; // per-ring threshold (empty -> frame had no valid pixels)
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std::vector<float> host_bkg; // clipped per-ring mean, NaN where the ring is too sparse to trust
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PinnedVector<unsigned long long> prof_sum; // plain corrected sum } azimuthal-integration profile
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PinnedVector<unsigned long long> prof_sum2; // plain corrected sum^2 } (fixed point)
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PinnedVector<uint32_t> prof_count; // plain pixel count }
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// The pinned arrays above are each a device-to-host copy once per frame. A D2H copy into PAGEABLE
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// memory blocks the host until it completes, whatever stream it was issued on - which would stall
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// Detect() between the plain pass and the clip passes, with the device then idle while the host
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// enqueues them. In pinned memory the copies are genuinely asynchronous.
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AzimuthalIntegrationProfile last_profile; // filled every Run(), retrievable via GetProfile()
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// One reduction pass over the image into the raw accumulators. clip_k <= 0 -> plain pass (all
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// valid pixels); clip_k > 0 -> keep only pixels within clip_k sigma of the current gpu_mean.
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// accumulate_corrected additionally fills gpu_sum_corr/gpu_sum2_corr for the profile (plain pass).
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void ReducePass(const ImagePreprocessorBuffer &image, float clip_k, bool accumulate_corrected);
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// Finalize gpu_mean/gpu_sigma from the current raw accumulators (per ring).
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void FinalizeStats();
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// Host: per-ring threshold from the clipped raw stats and the single knob E (false pixels/frame).
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void ComputeThresholds(const SpotFindingSettings &settings);
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public:
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static constexpr int32_t HIST_VALUES = 1024; // as AdaptiveSpotFinderCPU
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AdaptiveSpotFinderGPU(const AzimuthalIntegrationMapping &mapping, std::shared_ptr<CudaStream> stream);
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// Waits for the stream: its pooled buffers are freed before the base class's (see CudaDevicePtr).
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~AdaptiveSpotFinderGPU() override { if (stream) cudaStreamSynchronize(*stream); }
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AdaptiveSpotFinderGPU(const AdaptiveSpotFinderGPU &) = delete;
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AdaptiveSpotFinderGPU &operator=(const AdaptiveSpotFinderGPU &) = delete;
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void Detect(const ImagePreprocessorBuffer &image, const SpotFindingSettings &settings) override;
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// The azimuthal profile computed as a byproduct of the last Detect() - lets this engine replace the
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// separate azint pass in the analysis pipeline.
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[[nodiscard]] const AzimuthalIntegrationProfile &GetProfile() const { return last_profile; }
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[[nodiscard]] const std::vector<float> &GetRingBackground() const override { return host_bkg; }
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};
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