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Jungfraujoch/common/AzimuthalIntegrationSettings.h
T
leonarski_fandClaude Fable 5 347228d008
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jfjoch_process: azimuthal-integration CLI + default 0.01 1/A q-spacing
Add -q/--azim-q-spacing, --azim-min-q, --azim-max-q, --azim-phi-bins (mirroring
jfjoch_azint) so offline processing can set the radial binning, applied before
the azint mapping is built. Set the AzimuthalIntegrationSettings default spacing
to 0.01 1/A (was 0.05): the coarse default barely resolved the narrow ice rings,
diluting the ice-ring score. Finer binning sharpens it a lot with no effect on
processing - EP_cs_01-17 ice score 4.6->7.3 (max 11->23), clean cytC stays ~1.0,
and space group / cell / ISa / completeness are unchanged (cytC, InsI3, MyoB,
pding4_001 verified full-image). Documented in JFJOCH_PROCESS.md.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
2026-07-02 17:24:05 +02:00

57 lines
2.2 KiB
C++

// SPDX-FileCopyrightText: 2024 Filip Leonarski, Paul Scherrer Institute <filip.leonarski@psi.ch>
// SPDX-License-Identifier: GPL-3.0-only
#pragma once
#include "JFJochMath.h"
#include <optional>
#include <cstdint>
class AzimuthalIntegrationSettings {
constexpr static float minQ_recipA = 1e-5;
constexpr static float maxQ_recipA = 10.0;
bool solid_angle_correction = true;
bool polarization_correction = true;
float high_q_recipA = 5.0;
float low_q_recipA = 0.1;
float bkg_estimate_high_q_recipA = 2.0f * PI / 3.0;
float bkg_estimate_low_q_recipA = 2.0f * PI / 5.0;
float q_spacing = 0.01;
int32_t azim_bins = 1;
// Compute azimuthal integration on the CPU instead of the FPGA during the FPGA
// acquisition workflow. Lifts the FPGA bin-count limit and adds standard-deviation output.
bool force_cpu_in_fpga_workflow = false;
int32_t q_bins= 0;
int32_t total_bins = 0;
void UpdateBinCount();
public:
AzimuthalIntegrationSettings();
AzimuthalIntegrationSettings& SolidAngleCorrection(bool input);
AzimuthalIntegrationSettings& PolarizationCorrection(bool input);
AzimuthalIntegrationSettings& QRange_recipA(float low, float high);
AzimuthalIntegrationSettings& QSpacing_recipA(float input);
AzimuthalIntegrationSettings& BkgEstimateQRange_recipA(float low, float high);
AzimuthalIntegrationSettings& AzimuthalBinCount(int32_t input);
AzimuthalIntegrationSettings& ForceCPUinFPGAWorkflow(bool input);
[[nodiscard]] bool IsSolidAngleCorrection() const;
[[nodiscard]] bool IsPolarizationCorrection() const;
[[nodiscard]] float GetHighQ_recipA() const;
[[nodiscard]] float GetLowQ_recipA() const;
[[nodiscard]] float GetQSpacing_recipA() const;
[[nodiscard]] int32_t GetBinCount() const;
[[nodiscard]] int32_t GetQBinCount() const;
[[nodiscard]] int32_t GetAzimuthalBinCount() const;
[[nodiscard]] bool IsForceCPUinFPGAWorkflow() const;
[[nodiscard]] float GetBkgEstimateLowQ_recipA() const;
[[nodiscard]] float GetBkgEstimateHighQ_recipA() const;
[[nodiscard]] uint16_t QToBin(float q) const;
[[nodiscard]] uint16_t GetBin(float q, float phi_deg) const;
};