Files
Jungfraujoch/fpga/hls/writer_split.cpp

54 lines
1.5 KiB
C++

// Copyright (2019-2023) Paul Scherrer Institute
// SPDX-License-Identifier: GPL-3.0-or-later
#include "hls_jfjoch.h"
void writer_split(STREAM_512 &data_in,
STREAM_512 &data_out_1,
STREAM_512 &data_out_2,
hls::stream<ap_uint<ADDR_STREAM_WIDTH> > &addr_in,
hls::stream<ap_uint<ADDR_STREAM_WIDTH> > &addr_out_1,
hls::stream<ap_uint<ADDR_STREAM_WIDTH> > &addr_out_2) {
#pragma HLS INTERFACE register both axis port=data_in
#pragma HLS INTERFACE register both axis port=data_out_1
#pragma HLS INTERFACE register both axis port=data_out_2
#pragma HLS INTERFACE register both axis port=addr_in
#pragma HLS INTERFACE register both axis port=addr_out_1
#pragma HLS INTERFACE register both axis port=addr_out_2
#pragma HLS INTERFACE ap_ctrl_none port=return
packet_512_t packet;
ap_uint<ADDR_STREAM_WIDTH> addr;
addr_in >> addr;
addr_out_1 << addr;
addr_out_2 << addr;
data_in >> packet;
data_out_1 << packet;
data_out_2 << packet;
addr_in >> addr;
addr_out_1 << addr;
addr_out_2 << addr;
Loop_good_packet:
while (!addr_last_flag(addr)) {
#pragma HLS PIPELINE II=128
for (int i = 0; i < 128; i++) {
data_in >> packet;
data_out_1 << packet;
data_out_2 << packet;
}
addr_in >> addr;
addr_out_1 << addr;
addr_out_2 << addr;
}
data_in >> packet;
data_out_1 << packet;
data_out_2 << packet;
}