37 lines
835 B
Tcl
37 lines
835 B
Tcl
## Copyright (2019-2023) Paul Scherrer Institute
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open_project $env(HLS_TOP_FUNCTION) -reset
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set_top $env(HLS_TOP_FUNCTION)
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add_files $env(SRC_DIR)/$env(HLS_FILE)
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if { [info exists ::env(HLS_TB_FILE)] } {
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if {$env(HLS_TB_FILE) != ""} {
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add_files -tb $env(SRC_DIR)/$env(HLS_TB_FILE)
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}
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}
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open_solution solution1
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# Outcome will work for all Virtex US+ HBM FPGAs (this is mostly for utilization statistics)
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set_part xcu55c-fsvh2892-2L-e
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create_clock -period 3.2 -name default
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config_interface -m_axi_addr64=true
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config_schedule -enable_dsp_full_reg=true
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if { [info exists ::env(HLS_TB_FILE)] } {
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if {$env(HLS_TB_FILE) != ""} {
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csim_design
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}
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}
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csynth_design
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config_export -vendor {psi.ch} -version 1.0 -ipname $env(HLS_TOP_FUNCTION) -format ip_catalog -rtl verilog
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export_design
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close_project
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exit
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